Lines Matching refs:r6

61 	and	r6, r8, r7
63 	add	r6, r6, r9, lsr #1
65 	add	r6, r6, r9, lsr #2
67 	add	r6, r6, r9, lsr #3
68 	add	r6, r6, r6, lsr #8
69 	add	r6, r6, r6, lsr #4
70 	and	r6, r6, #15			@ r6 = no. of registers to transfer.
74 	subne	r7, r7, r6, lsl #2		@ Undo increment
75 	addeq	r7, r7, r6, lsl #2		@ Undo decrement
85 	andne	r6, r8, #0xf00			@ { immediate high nibble
86 	orrne	r6, r9, r6, lsr #4		@   combine nibbles } else
87 	ldreq	r6, [r2, r9, lsl #2]		@ { load Rm value }
92 	subne	r7, r7, r6			@ Undo incrmenet
93 	addeq	r7, r7, r6			@ Undo decrement
101 	movs	r6, r8, lsl #20			@ Get offset
106 	subne	r7, r7, r6, lsr #20		@ Undo increment
107 	addeq	r7, r7, r6, lsr #20		@ Undo decrement
116 	ldr	r6, [r2, r7, lsl #2]		@ Get register 'Rm'
124 	mov	r6, r6, lsl r9			@ 0: LSL #!0
132 	mov	r6, r6, lsr r9			@ 4: LSR #!0
134 	mov	r6, r6, lsr #32			@ 5: LSR #32
140 	mov	r6, r6, asr r9			@ 8: ASR #!0
142 	mov	r6, r6, asr #32			@ 9: ASR #32
148 	mov	r6, r6, ror r9			@ C: ROR #!0
150 	mov	r6, r6, rrx			@ D: RRX
191 	and	r6, r8, #0x55			@ hweight8(r8) + R bit
193 	add	r6, r6, r9, lsr #1
194 	and	r9, r6, #0xcc
195 	and	r6, r6, #0x33
196 	add	r6, r6, r9, lsr #2
198 	adc	r6, r6, r6, lsr #4		@ high + low nibble + R bit
199 	and	r6, r6, #15			@ number of regs to transfer
202 	addeq	r7, r7, r6, lsl #2		@ increment SP if PUSH
203 	subne	r7, r7, r6, lsl #2		@ decrement SP if POP
208 	and	r6, r8, #0x55			@ hweight8(r8)
210 	add	r6, r6, r9, lsr #1
211 	and	r9, r6, #0xcc
212 	and	r6, r6, #0x33
213 	add	r6, r6, r9, lsr #2
214 	add	r6, r6, r6, lsr #4
217 	and	r6, r6, #15			@ number of regs to transfer
218 	sub	r7, r7, r6, lsl #2		@ always decrement