Lines Matching refs:MK_BMSK_

14 #define MK_BMSK_(x) (1<<x)  macro
128 #define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)
130 #define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)
132 #define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)
134 #define ASTAT_AC0_COPY     MK_BMSK_(ASTAT_AC0_COPY_P)
136 #define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)
138 #define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)
140 #define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)
142 #define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)
144 #define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)
146 #define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)
148 #define ASTAT_V            MK_BMSK_(ASTAT_V_P)
150 #define ASTAT_V_COPY       MK_BMSK_(ASTAT_V_COPY_P)
177 #define SEQSTAT_EXCAUSE        (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
178                                 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
179                                 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
180                                 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
181                                 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
182                                 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
186 #define SEQSTAT_SFTRESET       (MK_BMSK_(SEQSTAT_SFTRESET_P))
189 #define SEQSTAT_HWERRCAUSE     (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
190                                 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
191                                 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
192                                 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
193                                 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
222 #define SYSCFG_SSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P )
224 #define SYSCFG_CCEN           MK_BMSK_(SYSCFG_CCEN_P )
226 #define SYSCFG_SNEN	       MK_BMSK_(SYSCFG_SNEN_P)
512 #define EVT_EMU       MK_BMSK_(EVT_EMU_P   )	/* Emulator interrupt mask */
513 #define EVT_RST       MK_BMSK_(EVT_RST_P   )	/* Reset interrupt mask */
514 #define EVT_NMI       MK_BMSK_(EVT_NMI_P   )	/* Non Maskable interrupt mask */
515 #define EVT_EVX       MK_BMSK_(EVT_EVX_P   )	/* Exception mask */
516 #define EVT_IRPTEN    MK_BMSK_(EVT_IRPTEN_P)	/* Global interrupt enable mask */
517 #define EVT_IVHW      MK_BMSK_(EVT_IVHW_P  )	/* Hardware Error interrupt mask */
518 #define EVT_IVTMR     MK_BMSK_(EVT_IVTMR_P )	/* Timer interrupt mask */
519 #define EVT_IVG7      MK_BMSK_(EVT_IVG7_P  )	/* IVG7 interrupt mask */
520 #define EVT_IVG8      MK_BMSK_(EVT_IVG8_P  )	/* IVG8 interrupt mask */
521 #define EVT_IVG9      MK_BMSK_(EVT_IVG9_P  )	/* IVG9 interrupt mask */
522 #define EVT_IVG10     MK_BMSK_(EVT_IVG10_P )	/* IVG10 interrupt mask */
523 #define EVT_IVG11     MK_BMSK_(EVT_IVG11_P )	/* IVG11 interrupt mask */
524 #define EVT_IVG12     MK_BMSK_(EVT_IVG12_P )	/* IVG12 interrupt mask */
525 #define EVT_IVG13     MK_BMSK_(EVT_IVG13_P )	/* IVG13 interrupt mask */
526 #define EVT_IVG14     MK_BMSK_(EVT_IVG14_P )	/* IVG14 interrupt mask */
527 #define EVT_IVG15     MK_BMSK_(EVT_IVG15_P )	/* IVG15 interrupt mask */