Lines Matching refs:reset
167 ;; Start MII clock to make sure it is running when tranceiver is reset
369 move.d $r0, [$r1]; assert ATA bus-reset
397 ;; reset dma4 and wait for completion
399 moveq IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
403 cmp.b IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
407 ;; reset dma5 and wait for completion
409 moveq IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
413 cmp.b IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
476 move.b $r0,[R_DMA_CH6_CMD] ; reset (ser0 dma out)
477 move.b $r0,[R_DMA_CH7_CMD] ; reset (ser0 dma in)
478 1: move.b [R_DMA_CH6_CMD],$r0 ; wait for reset cycle to finish
483 1: move.b [R_DMA_CH7_CMD],$r0 ; wait for reset cycle to finish
490 moveq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
491 move.b $r0,[R_DMA_CH8_CMD] ; reset (ser1 dma out)
492 move.b $r0,[R_DMA_CH9_CMD] ; reset (ser1 dma in)
493 1: move.b [R_DMA_CH8_CMD],$r0 ; wait for reset cycle to finish
495 cmpq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
498 1: move.b [R_DMA_CH9_CMD],$r0 ; wait for reset cycle to finish
500 cmpq IO_STATE (R_DMA_CH9_CMD, cmd, reset),$r0