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71 Setting this option causes the FR-V atomic operations to be mostly
84 else must be kmapped.
94 with a lot of RAM, this can be wasteful of precious low memory.
106 itself to start there. It must be greater than 0, and it must be
110 The base address must also be aligned such that the SDRAM controller
111 can decode it. For instance, a 512MB SDRAM bank must be 512MB aligned.
158 the affected cacheline to be read into the cache first before being
160 is filled and a cacheline needs to be displaced from the cache to
169 cacheline is also in cache, it will be updated too.
218 This causes appropriate flags to be passed to the compiler to
233 This causes appropriate flags to be passed to the compiler to
263 Select this option if the MB93091 CPU board is going to be used with
269 Select this option if the MB93091 CPU board is going to be used
278 Select this option if the MB93493 multimedia chip is going to be
285 This option controls what data, if any, should be placed in the GP
298 Note that modules will always be compiled with this feature disabled
299 as the module data will not be in range of the GP base address.
334 a fully featured MMU is available, this can be done through page
335 table settings, but if not, a region has to be set aside and marked
339 available memory for use in this manner. The memory will then be