Lines Matching refs:gr31
74 movgs gr31,psr
113 movgs gr31,psr
150 srlicc.p gr31,#26,gr0,icc0
152 srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
162 and gr31,gr30,gr31
164 add gr30,gr31,gr31
165 ldi @(gr31,#0),gr30 /* fetch the PTE */
169 sti.p gr30,@(gr31,#0) /* update the PTE */
176 movsg iampr1,gr31
177 andicc gr31,#xAMPRx_V,gr0,icc0
178 setlos.p 0xfffff000,gr31
181 movsg iamlr1,gr31
182 movgs gr31,tplr /* set TPLR.CXN */
183 tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
185 movsg dampr1,gr31
186 ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
187 movgs gr31,tppr
188 movsg iamlr1,gr31 /* set TPLR.CXN */
189 movgs gr31,tplr
190 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
191 movsg tpxr,gr31 /* check the TLB write error flag */
192 andicc.p gr31,#TPXR_E,gr0,icc0
193 setlos #0xfffff000,gr31
199 and gr29,gr31,gr29
200 movsg cxnr,gr31
201 or gr29,gr31,gr29
305 movsg dampr1,gr31
306 andicc gr31,#xAMPRx_V,gr0,icc0
307 setlos.p 0xfffff000,gr31
310 movsg damlr1,gr31
311 movgs gr31,tplr /* set TPLR.CXN */
312 tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
314 movsg dampr1,gr31
315 ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
316 movgs gr31,tppr
317 movsg damlr1,gr31 /* set TPLR.CXN */
318 movgs gr31,tplr
319 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
320 movsg tpxr,gr31 /* check the TLB write error flag */
321 andicc.p gr31,#TPXR_E,gr0,icc0
322 setlos #0xfffff000,gr31
328 and gr29,gr31,gr29
329 movsg cxnr,gr31
330 or gr29,gr31,gr29
431 movsg dampr1,gr31
432 andicc gr31,#xAMPRx_V,gr0,icc0
433 setlos.p 0xfffff000,gr31
436 movsg dampr1,gr31
437 movgs gr31,tppr
438 movsg damlr1,gr31 /* set TPLR.CXN */
439 movgs gr31,tplr
440 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
441 movsg tpxr,gr31 /* check the TLB write error flag */
442 andicc.p gr31,#TPXR_E,gr0,icc0
443 setlos #0xfffff000,gr31
449 and gr28,gr31,gr28
450 movsg cxnr,gr31
451 or gr28,gr31,gr28
551 movsg dampr1,gr31
552 andicc gr31,#xAMPRx_V,gr0,icc0
553 setlos.p 0xfffff000,gr31
556 movsg dampr1,gr31
557 movgs gr31,tppr
558 movsg damlr1,gr31 /* set TPLR.CXN */
559 movgs gr31,tplr
560 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
561 movsg tpxr,gr31 /* check the TLB write error flag */
562 andicc.p gr31,#TPXR_E,gr0,icc0
563 setlos #0xfffff000,gr31
569 and gr28,gr31,gr28
570 movsg cxnr,gr31
571 or gr28,gr31,gr28
598 and gr31,gr30,gr31
603 srli gr28,#26,gr31 /* calculate PGE offset */
604 slli gr31,#8,gr31 /* and clear bottom bits */
607 ld @(gr31,gr30),gr30 /* access the PGE */
615 slli.p gr31,#18,gr31
618 movgs gr31,scr1
622 srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */