Lines Matching refs:t1
128 srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
129 andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
130 beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
132 addiu t0, t1, 1
133 ori t1, zero, 1
134 sllv t1, t1, t0
156 addu t0, t0, t1 /* add bytes in a line */
166 move t1, zero
179 cache Index_Store_Tag_D, 0(t1)
182 addiu t1, t1, 32 /* 32 bytes in a line */
198 or t1, zero, zero /* T1 = starting cache index (0) */
208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
216 la t1, KSEG0 /* T1 = cached memory base address */
217 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
233 or t1, zero, zero /* T1 = starting cache index (0) */
247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
254 la t1, KSEG0 /* T1 = cached memory base address */
255 lw zero, 0x0000(t1) /* (dummy read of first memory word) */