Lines Matching refs:li
65 li r24,0 /* CPU number */
113 li r0,0
158 li r4, 0 /* higer 32bit */
204 li r3,0
220 li r0,0
352 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
384 li r13,0
450 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
480 li r13,0
522 li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
528 li r10,0xf85 /* Mask to apply from PTE */
566 li r12,0 /* MMUCR = 0 */
589 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
598 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
600 li r12,0
663 li r12,0 /* MMUCR = 0 */
673 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
681 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
683 li r12,0
739 li r10,0xf85 /* Mask to apply from PTE */
775 li r3,MachineCheckA@l
880 li r4,0 /* Start at TLB entry 0 */
881 li r3,0 /* Set PAGEID inval value */
914 li r4, 0 /* Load the kernel physical address */
918 li r0,0
923 li r5,0
937 li r5,0
940 li r0,63 /* TLB slot 63 */
958 li r6,0
975 li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
976 li r0,62 /* TLB slot 0 */
1027 li r0,0
1040 li r0,0
1081 li r5,0
1126 li r0,0
1137 li r5,0
1189 li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)