152 static int __init phy_wait_for_ack(struct pci_channel *chan)  in phy_wait_for_ack()  argument
157 		if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))  in phy_wait_for_ack()
166 static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)  in pci_wait_for_irq()  argument
171 		if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)  in pci_wait_for_irq()
180 static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr,  in phy_write_reg()  argument
189 	pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);  in phy_write_reg()
190 	pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);  in phy_write_reg()
192 	phy_wait_for_ack(chan);  in phy_write_reg()
195 	pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);  in phy_write_reg()
196 	pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);  in phy_write_reg()
198 	phy_wait_for_ack(chan);  in phy_write_reg()
203 	struct pci_channel *chan = port->hose;  in pcie_clk_init()  local
238 	clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR);  in pcie_clk_init()
258 	struct pci_channel *chan = port->hose;  in phy_init()  local
264 	phy_write_reg(chan, 0x60, 0xf, 0x004b008b);  in phy_init()
265 	phy_write_reg(chan, 0x61, 0xf, 0x00007b41);  in phy_init()
266 	phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);  in phy_init()
267 	phy_write_reg(chan, 0x65, 0xf, 0x09070907);  in phy_init()
268 	phy_write_reg(chan, 0x66, 0xf, 0x00000010);  in phy_init()
269 	phy_write_reg(chan, 0x74, 0xf, 0x0007001c);  in phy_init()
270 	phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);  in phy_init()
271 	phy_write_reg(chan, 0xb0, 0xf, 0x00000610);  in phy_init()
274 	phy_write_reg(chan, 0x67, 0x1, 0x00000400);  in phy_init()
280 		if (pci_read_reg(chan, SH4A_PCIEPHYSR))  in phy_init()
291 	struct pci_channel *chan = port->hose;  in pcie_reset()  local
293 	pci_write_reg(chan, 1, SH4A_PCIESRSTR);  in pcie_reset()
294 	pci_write_reg(chan, 0, SH4A_PCIETCTLR);  in pcie_reset()
295 	pci_write_reg(chan, 0, SH4A_PCIESRSTR);  in pcie_reset()
296 	pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);  in pcie_reset()
301 	struct pci_channel *chan = port->hose;  in pcie_init()  local
315 	pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1);  in pcie_init()
318 	data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);  in pcie_init()
327 	pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);  in pcie_init()
330 	pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);  in pcie_init()
333 	data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);  in pcie_init()
336 	pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);  in pcie_init()
339 	data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);  in pcie_init()
342 	pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);  in pcie_init()
345 	data = pci_read_reg(chan, SH4A_PCIETLCTLR);  in pcie_init()
348 	pci_write_reg(chan, data, SH4A_PCIETLCTLR);  in pcie_init()
354 	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);  in pcie_init()
357 	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);  in pcie_init()
367 		pci_write_reg(chan, memphys + SZ_512M, SH4A_PCIELAR1);  in pcie_init()
368 		pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,  in pcie_init()
375 		pci_write_reg(chan, 0, SH4A_PCIELAR1);  in pcie_init()
376 		pci_write_reg(chan, 0, SH4A_PCIELAMR1);  in pcie_init()
383 	pci_write_reg(chan, memphys, SH4A_PCIELAR0);  in pcie_init()
384 	pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);  in pcie_init()
387 	data = pci_read_reg(chan, SH4A_PCIETCTLR);  in pcie_init()
389 	pci_write_reg(chan, data, SH4A_PCIETCTLR);  in pcie_init()
395 	data = pci_read_reg(chan, SH4A_PCIEDLINTENR);  in pcie_init()
397 	pci_write_reg(chan, data, SH4A_PCIEDLINTENR);  in pcie_init()
400 	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);  in pcie_init()
402 	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);  in pcie_init()
409 	ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);  in pcie_init()
411 	data = pci_read_reg(chan, SH4A_PCIEPCICONF1);  in pcie_init()
415 	pci_write_reg(chan, data, SH4A_PCIEPCICONF1);  in pcie_init()
417 	pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);  in pcie_init()
418 	pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);  in pcie_init()
423 		data = pci_read_reg(chan, SH4A_PCIEMACSR);  in pcie_init()
430 	for (i = win = 0; i < chan->nr_resources; i++) {  in pcie_init()
431 		struct resource *res = chan->resources + i;  in pcie_init()
442 		pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));  in pcie_init()
450 		pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win));  in pcie_init()
452 		pci_write_reg(chan, upper_32_bits(res->start),  in pcie_init()
454 		pci_write_reg(chan, lower_32_bits(res->start),  in pcie_init()
461 		pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win));  in pcie_init()