Lines Matching refs:RS
35 #define RS 0x200 /* skip between registers */ macro
37 #define A RS /* A-side data */
38 #define DIRB (2*RS) /* B-side direction (1=output) */
39 #define DIRA (3*RS) /* A-side direction (1=output) */
40 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
41 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
42 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
43 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
44 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
45 #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */
46 #define SR (10*RS) /* Shift register */
47 #define ACR (11*RS) /* Auxiliary control register */
48 #define PCR (12*RS) /* Peripheral control register */
49 #define IFR (13*RS) /* Interrupt flag register */
50 #define IER (14*RS) /* Interrupt enable register */
51 #define ANH (15*RS) /* A-side data, no handshake */