Lines Matching refs:uint32
42 uint32 control; /* enable, et al */
43 uint32 addr; /* descriptor ring base address (4K aligned) */
44 uint32 ptr; /* last descriptor posted to chip */
45 uint32 status; /* current active descriptor, et al */
54 uint32 fifoaddr; /* diag address */
55 uint32 fifodatalow; /* low 32bits of data */
56 uint32 fifodatahigh; /* high 32bits of data */
57 uint32 pad; /* reserved */
65 uint32 ctrl; /* misc control bits & bufcount */
66 uint32 addr; /* data buffer address */
79 #define XC_XE ((uint32)1 << 0) /* transmit enable */
80 #define XC_SE ((uint32)1 << 1) /* transmit suspend request */
81 #define XC_LE ((uint32)1 << 2) /* loopback enable */
82 #define XC_FL ((uint32)1 << 4) /* flush request */
85 #define XC_PD ((uint32)1 << 11) /* parity check disable */
86 #define XC_AE ((uint32)3 << 16) /* address extension bits */
145 #define RC_RE ((uint32)1 << 0) /* receive enable */
148 #define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
149 #define RC_SH ((uint32)1 << 9) /* separate rx header descriptor enable */
150 #define RC_OC ((uint32)1 << 10) /* overflow continue */
151 #define RC_PD ((uint32)1 << 11) /* parity check disable */
152 #define RC_AE ((uint32)3 << 16) /* address extension bits */
199 #define CTRL_AE ((uint32)3 << 16) /* address extension bits */
201 #define CTRL_PARITY ((uint32)3 << 18) /* parity bit */
202 #define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
203 #define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
204 #define CTRL_EOF ((uint32)1 << 30) /* end of frame */
205 #define CTRL_SOF ((uint32)1 << 31) /* start of frame */
214 uint32 control; /* enable, et al */
215 uint32 ptr; /* last descriptor posted to chip */
216 uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
217 uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
218 uint32 status0; /* current descriptor, xmt state */
219 uint32 status1; /* active descriptor, xmt error */
228 uint32 fifoaddr; /* diag address */
229 uint32 fifodatalow; /* low 32bits of data */
230 uint32 fifodatahigh; /* high 32bits of data */
231 uint32 pad; /* reserved */
239 uint32 ctrl1; /* misc control bits */
240 uint32 ctrl2; /* buffer count and address extension */
241 uint32 addrlow; /* memory address of the date buffer, bits 31:0 */
242 uint32 addrhigh; /* memory address of the date buffer, bits 63:32 */
383 #define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
384 #define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
385 #define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
386 #define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */