Lines Matching refs:uint

36 	uint	socitype;		/* SOCI_SB, SOCI_AI */
38 	uint	bustype;		/* SI_BUS, PCI_BUS */
39 	uint	buscoretype;		/* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
40 	uint	buscorerev;		/* buscore rev */
41 	uint	buscoreidx;		/* buscore index */
47 	uint	boardtype;		/* board type */
48 	uint    boardrev;               /* board rev */
49 	uint	boardvendor;		/* board vendor */
50 	uint	boardflags;		/* board flags */
51 	uint	boardflags2;		/* board flags2 */
52 	uint	chip;			/* chip number */
53 	uint	chiprev;		/* chip revision */
54 	uint	chippkg;		/* chip package option */
57 	uint    socirev;		/* SOC interconnect rev */
154 extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
155                        void *sdh, char **vars, uint *varsz);
160 extern uint si_corelist(si_t *sih, uint coreid[]);
161 extern uint si_coreid(si_t *sih);
162 extern uint si_flag(si_t *sih);
163 extern uint si_flag_alt(si_t *sih);
164 extern uint si_intflag(si_t *sih);
165 extern uint si_coreidx(si_t *sih);
166 extern uint si_coreunit(si_t *sih);
167 extern uint si_corevendor(si_t *sih);
168 extern uint si_corerev(si_t *sih);
171 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
173 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
174 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
180 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
181 extern void *si_setcoreidx(si_t *sih, uint coreidx);
182 extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
183 extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
184 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
186 extern uint32 si_addrspace(si_t *sih, uint asidx);
187 extern uint32 si_addrspacesize(si_t *sih, uint asidx);
188 extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
193 extern uint si_chip_hostif(si_t *sih);
198 extern void si_pci_setup(si_t *sih, uint coremask);
207 extern bool si_clkctl_cc(si_t *sih, uint mode);
208 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
220 extern void si_watchdog(si_t *sih, uint ticks);
234 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
250 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
255 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
316 extern void si_chippkg_set(si_t *sih, uint);
332 extern uint si_pll_reset(si_t *sih);
340 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
350 extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
360 extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val);
364 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);