52 static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, void *regs,
53                               uint bustype, void *sdh, char **vars, uint *varsz);
54 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh);
55 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
56 	uint *origidx, void *regs);
77 si_attach(uint devid, osl_t *osh, void *regs,  in si_attach()
78                        uint bustype, void *sdh, char **vars, uint *varsz)  in si_attach()
142 si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh)  in si_buscore_prep()
186 si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,  in si_buscore_setup()
187 	uint *origidx, void *regs)  in si_buscore_setup()
190 	uint i;  in si_buscore_setup()
191 	uint pciidx, pcieidx, pcirev, pcierev;  in si_buscore_setup()
222 	sii->pub.buscorerev = (uint)NOREV;  in si_buscore_setup()
226 	pcirev = pcierev = (uint)NOREV;  in si_buscore_setup()
230 		uint cid, crev;  in si_buscore_setup()
313 si_doattach(si_info_t *sii, uint devid, osl_t *osh, void *regs,  in si_doattach()
314                        uint bustype, void *sdh, char **vars, uint *varsz)  in si_doattach()
320 	uint origidx;  in si_doattach()
436 			uint clkdiv;  in si_doattach()
489 	uint idx;  in si_detach()
561 uint
577 uint
592 uint
616 uint
625 uint
635 uint
639 	uint idx;  in si_coreunit()
640 	uint coreid;  in si_coreunit()
641 	uint coreunit;  in si_coreunit()
642 	uint i;  in si_coreunit()
660 uint
681 uint
697 uint
698 si_findcoreidx(si_t *sih, uint coreid, uint coreunit)  in si_findcoreidx()
701 	uint found;  in si_findcoreidx()
702 	uint i;  in si_findcoreidx()
719 uint
720 si_corelist(si_t *sih, uint coreid[])  in si_corelist()
726 	bcopy((uchar*)sii->coreid, (uchar*)coreid, (sii->numcores * sizeof(uint)));  in si_corelist()
760 si_setcore(si_t *sih, uint coreid, uint coreunit)  in si_setcore()
762 	uint idx;  in si_setcore()
781 si_setcoreidx(si_t *sih, uint coreidx)  in si_setcoreidx()
797 si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)  in si_switch_core()
825 si_restore_core(si_t *sih, uint coreid, uint intr_val)  in si_restore_core()
853 si_addrspace(si_t *sih, uint asidx)  in si_addrspace()
868 si_addrspacesize(si_t *sih, uint asidx)  in si_addrspacesize()
883 si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size)  in si_coreaddrspaceX()
950 uint
959 uint
960 si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)  in si_corereg()
1123 si_watchdog(si_t *sih, uint ticks)  in si_watchdog()
1125 	uint nb, maxt;  in si_watchdog()
1184 static uint
1207 static uint
1211 	uint div;  in si_slowclk_freq()
1248 	uint slowmaxfreq, pll_delay, slowclk;  in si_clkctl_setdelay()
1249 	uint pll_on_delay, fref_sel_delay;  in si_clkctl_setdelay()
1276 	uint origidx = 0;  in si_clkctl_init()
1323 	uint regoff;  in si_gpiocontrol()
1345 	uint regoff;  in si_gpioouten()
1367 	uint regoff;  in si_gpioout()
1447 	uint regoff;  in si_gpioin()
1457 	uint regoff;  in si_gpiointpolarity()
1474 	uint regoff;  in si_gpiointmask()
1512 	uint offs;  in si_gpiopull()
1522 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val)  in si_gpioevent()
1524 	uint offs;  in si_gpioevent()
1630 	uint offs;  in si_gpio_int_enable()
1641 static uint
1644 	uint banksize, bankinfo;  in socram_banksize()
1645 	uint bankidx = idx | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT);  in socram_banksize()
1659 	uint origidx;  in si_socdevram()
1660 	uint intr_val = 0;  in si_socdevram()
1663 	uint corerev;  in si_socdevram()
1734 	uint origidx;  in si_socdevram_remap_isenb()
1735 	uint intr_val = 0;  in si_socdevram_remap_isenb()
1738 	uint corerev;  in si_socdevram_remap_isenb()
1796 	uint origidx;  in si_socdevram_size()
1797 	uint intr_val = 0;  in si_socdevram_size()
1801 	uint corerev;  in si_socdevram_size()
1844 	uint origidx;  in si_socdevram_remap_size()
1845 	uint intr_val = 0;  in si_socdevram_remap_size()
1849 	uint corerev;  in si_socdevram_remap_size()
1911 	uint origidx;  in si_socram_size()
1912 	uint intr_val = 0;  in si_socram_size()
1916 	uint corerev;  in si_socram_size()
1918 	uint memsize = 0;  in si_socram_size()
1943 		uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;  in si_socram_size()
1944 		uint bsz = (coreinfo & SRCI_SRBSZ_MASK);  in si_socram_size()
1945 		uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;  in si_socram_size()
1953 		uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;  in si_socram_size()
1975 	uint origidx;  in si_tcm_size()
1976 	uint intr_val = 0;  in si_tcm_size()
1980 	uint memsize = 0;  in si_tcm_size()
2037 	uint origidx;  in si_socram_srmem_size()
2038 	uint intr_val = 0;  in si_socram_srmem_size()
2042 	uint corerev;  in si_socram_srmem_size()
2044 	uint memsize = 0;  in si_socram_srmem_size()
2069 		uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;  in si_socram_srmem_size()
2094 	uint origidx;  in si_btcgpiowar()
2095 	uint intr_val = 0;  in si_btcgpiowar()
2127 	uint origidx;  in si_chipcontrl_btshd0_4331()
2129 	uint intr_val = 0;  in si_chipcontrl_btshd0_4331()
2162 	uint origidx;  in si_chipcontrl_restore()
2176 	uint origidx;  in si_chipcontrl_read()
2192 	uint origidx;  in si_chipcontrl_epa4331()
2230 	uint origidx;  in si_chipcontrl_srom4360()
2259 	uint origidx;  in si_chipcontrl_epa4331_wowl()
2288 uint
2291 	uint err = 0;  in si_pll_reset()
2302 	uint origidx;  in si_epa_4313war()
2333 	uint origidx;  in si_btcombo_p250_4313_war()
2352 	uint origidx;  in si_btc_enable_chipcontrol()
2370 	uint origidx;  in si_btcombo_43228_war()
2408 		uint origidx;  in si_is_sprom_available()
2480 	uint origidx;  in si_get_sromctl()
2499 	uint origidx;  in si_set_sromctl()
2519 uint
2522 	uint origidx;  in si_core_wrapperreg()
2523 	uint ret_val;  in si_core_wrapperreg()