55 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
61 static uint32 si_gpioreservation = 0;
101 static uint32	wd_msticks;		/* watchdog timer ticks normalized to ms */
186 si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,  in si_buscore_setup()
317 	uint32 w, savewin;  in si_doattach()
339 		savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));  in si_doattach()
457 			uint32 gpiopullup = 0, gpiopulldown = 0;  in si_doattach()
569 		return R_REG(sii->osh, ((uint32 *)(uintptr)  in si_intflag()
852 uint32
867 uint32
883 si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size)  in si_coreaddrspaceX()
892 uint32
893 si_core_cflags(si_t *sih, uint32 mask, uint32 val)  in si_core_cflags()
908 si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)  in si_core_cflags_wo()
920 uint32
921 si_core_sflags(si_t *sih, uint32 mask, uint32 val)  in si_core_sflags()
951 si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val)  in si_wrapperreg()
975 si_core_disable(si_t *sih, uint32 bits)  in si_core_disable()
986 si_core_reset(si_t *sih, uint32 bits, uint32 resetbits)  in si_core_reset()
1000 	uint32 cflags;  in si_corebist()
1021 static uint32
1022 factor6(uint32 x)  in factor6()
1036 uint32
1037 si_clock_rate(uint32 pll_type, uint32 n, uint32 m)  in si_clock_rate()
1039 	uint32 n1, n2, clock, m1, m2, m3, mc;  in si_clock_rate()
1165 si_watchdog_ms(si_t *sih, uint32 ms)  in si_watchdog_ms()
1170 uint32 si_watchdog_msticks(void)  in si_watchdog_msticks()
1193 		    (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) &  in si_slowclk_src()
1210 	uint32 slowclk;  in si_slowclk_freq()
1320 uint32
1321 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority)  in si_gpiocontrol()
1342 uint32
1343 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority)  in si_gpioouten()
1364 uint32
1365 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority)  in si_gpioout()
1386 uint32
1387 si_gpioreserve(si_t *sih, uint32 gpio_bitmask, uint8 priority)  in si_gpioreserve()
1417 uint32
1418 si_gpiorelease(si_t *sih, uint32 gpio_bitmask, uint8 priority)  in si_gpiorelease()
1444 uint32
1454 uint32
1455 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority)  in si_gpiointpolarity()
1471 uint32
1472 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority)  in si_gpiointmask()
1488 uint32
1489 si_gpioled(si_t *sih, uint32 mask, uint32 val)  in si_gpioled()
1499 uint32
1500 si_gpiotimerval(si_t *sih, uint32 mask, uint32 gpiotimerval)  in si_gpiotimerval()
1509 uint32
1510 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val)  in si_gpiopull()
1521 uint32
1522 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val)  in si_gpioevent()
1542 si_gpio_handler_register(si_t *sih, uint32 event,  in si_gpio_handler_register()
1607 	uint32 level = si_gpioin(sih);  in si_gpio_handler_process()
1608 	uint32 levelp = si_gpiointpolarity(sih, 0, 0, 0);  in si_gpio_handler_process()
1609 	uint32 edge = si_gpioevent(sih, GPIO_REGEVT, 0, 0);  in si_gpio_handler_process()
1610 	uint32 edgep = si_gpioevent(sih, GPIO_REGEVT_INTPOL, 0, 0);  in si_gpio_handler_process()
1615 			uint32 status = (h->level ? level : edge) & h->event;  in si_gpio_handler_process()
1616 			uint32 polarity = (h->level ? levelp : edgep) & h->event;  in si_gpio_handler_process()
1627 uint32
1684 		uint32 extcinfo;  in si_socdevram()
1687 		uint32 bankidx, bankinfo;  in si_socdevram()
1739 	uint32 extcinfo;  in si_socdevram_remap_isenb()
1742 	uint32 bankidx, bankinfo;  in si_socdevram_remap_isenb()
1792 uint32
1798 	uint32 memsize = 0;  in si_socdevram_size()
1819 		uint32 extcinfo;  in si_socdevram_size()
1840 uint32
1846 	uint32 memsize = 0, banksz;  in si_socdevram_remap_size()
1850 	uint32 extcinfo;  in si_socdevram_remap_size()
1853 	uint32 bankidx, bankinfo;  in si_socdevram_remap_size()
1907 uint32
1917 	uint32 coreinfo;  in si_socram_size()
1971 uint32
1979 	uint32 corecap;  in si_tcm_size()
1981 	uint32 nab = 0;  in si_tcm_size()
1982 	uint32 nbb = 0;  in si_tcm_size()
1983 	uint32 totb = 0;  in si_tcm_size()
1984 	uint32 bxinfo = 0;  in si_tcm_size()
1985 	uint32 idx = 0;  in si_tcm_size()
1986 	uint32 *arm_cap_reg;  in si_tcm_size()
1987 	uint32 *arm_bidx;  in si_tcm_size()
1988 	uint32 *arm_binfo;  in si_tcm_size()
2006 	arm_cap_reg = (uint32 *)(regs + SI_CR4_CAP);  in si_tcm_size()
2013 	arm_bidx = (uint32 *)(regs + SI_CR4_BANKIDX);  in si_tcm_size()
2014 	arm_binfo = (uint32 *)(regs + SI_CR4_BANKINFO);  in si_tcm_size()
2033 uint32
2043 	uint32 coreinfo;  in si_socram_srmem_size()
2128 	uint32 val;  in si_chipcontrl_btshd0_4331()
2158 si_chipcontrl_restore(si_t *sih, uint32 val)  in si_chipcontrl_restore()
2171 uint32
2177 	uint32 val;  in si_chipcontrl_read()
2193 	uint32 val;  in si_chipcontrl_epa4331()
2231 	uint32 val;  in si_chipcontrl_srom4360()
2260 	uint32 val;  in si_chipcontrl_epa4331_wowl()
2387 	uint32 w;  in si_deviceremoved()
2395 		w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_VID, sizeof(uint32));  in si_deviceremoved()
2410 		uint32 sromctrl;  in si_is_sprom_available()
2432 		uint32 spromotp;  in si_is_sprom_available()
2477 uint32 si_get_sromctl(si_t *sih)  in si_get_sromctl()
2481 	uint32 sromctl;  in si_get_sromctl()
2496 int si_set_sromctl(si_t *sih, uint32 value)  in si_set_sromctl()
2520 si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val)  in si_core_wrapperreg()