Lines Matching refs:MVS_GBL_CTL
166 mw32(MVS_GBL_CTL, 0); in mvs_64xx_chip_reset()
167 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()
185 mw32(MVS_GBL_CTL, 0); in mvs_64xx_chip_reset()
186 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()
191 mw32_f(MVS_GBL_CTL, HBA_RST); in mvs_64xx_chip_reset()
199 if (!(mr32(MVS_GBL_CTL) & HBA_RST)) in mvs_64xx_chip_reset()
202 if (mr32(MVS_GBL_CTL) & HBA_RST) { in mvs_64xx_chip_reset()
440 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_interrupt_enable()
441 mw32(MVS_GBL_CTL, tmp | INT_EN); in mvs_64xx_interrupt_enable()
449 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_interrupt_disable()
450 mw32(MVS_GBL_CTL, tmp & ~INT_EN); in mvs_64xx_interrupt_disable()