102 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in handle_rx_dm()
142 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in handle_rx_dm()
144 	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in handle_rx_dm()
159 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in handle_rx()
244 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in handle_delta_cts()
290 	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_reset()
291 	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_reset()
292 	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_reset()
293 	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);  in msm_reset()
294 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_reset()
295 	msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);  in msm_reset()
306 		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_set_mctrl()
316 		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);  in msm_break_ctl()
318 		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);  in msm_break_ctl()
380 		msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_set_baud_rate()
398 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_set_baud_rate()
400 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_set_baud_rate()
456 		msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_startup()
462 	msm_write(port, data, UART_CR);	/* enable TX & RX */  in msm_startup()
474 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_startup()
475 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_startup()
825 		msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_console_setup()
826 		msm_write(port, UART_CR_TX_ENABLE, UART_CR);  in msm_console_setup()