Lines Matching defs:edge_compatibility_bits
304 struct edge_compatibility_bits { struct
308 __u32 VendEnableSuspend : 1; // 0001 Set if device supports ION_ENABLE_SUSPEND
309 __u32 VendUnused : 31; // Available for future expansion, must be 0
315 __u32 IOSPOpen : 1; // 0001 OPEN / OPEN_RSP (Currently must be 1)
316 __u32 IOSPClose : 1; // 0002 CLOSE
317 __u32 IOSPChase : 1; // 0004 CHASE / CHASE_RSP
318 __u32 IOSPSetRxFlow : 1; // 0008 SET_RX_FLOW
319 __u32 IOSPSetTxFlow : 1; // 0010 SET_TX_FLOW
320 __u32 IOSPSetXChar : 1; // 0020 SET_XON_CHAR/SET_XOFF_CHAR
321 __u32 IOSPRxCheck : 1; // 0040 RX_CHECK_REQ/RX_CHECK_RSP
322 __u32 IOSPSetClrBreak : 1; // 0080 SET_BREAK/CLEAR_BREAK
323 __u32 IOSPWriteMCR : 1; // 0100 MCR register writes (set/clr DTR/RTS)
324 __u32 IOSPWriteLCR : 1; // 0200 LCR register writes (wordlen/stop/parity)
325 __u32 IOSPSetBaudRate : 1; // 0400 setting Baud rate (writes to LCR.80h and DLL/DLM register)
326 …32 IOSPDisableIntPipe : 1; // 0800 Do not use the interrupt pipe for TxCredits or RxButesAvailable
327 __u32 IOSPRxDataAvail : 1; // 1000 Return status of RX Fifo (Data available in Fifo)
328 __u32 IOSPTxPurge : 1; // 2000 Purge TXBuffer and/or Fifo in Edgeport hardware
329 __u32 IOSPUnused : 18; // Available for future expansion, must be 0
333 __u32 TrueEdgeport : 1; // 0001 Set if device is a 'real' Edgeport
335 __u32 GenUnused : 31; // Available for future expansion, must be 0