1 #ifndef DIBX000_COMMON_H 2 #define DIBX000_COMMON_H 3 4 enum dibx000_i2c_interface { 5 DIBX000_I2C_INTERFACE_TUNER = 0, 6 DIBX000_I2C_INTERFACE_GPIO_1_2 = 1, 7 DIBX000_I2C_INTERFACE_GPIO_3_4 = 2, 8 DIBX000_I2C_INTERFACE_GPIO_6_7 = 3 9 }; 10 11 struct dibx000_i2c_master { 12 #define DIB3000MC 1 13 #define DIB7000 2 14 #define DIB7000P 11 15 #define DIB7000MC 12 16 #define DIB8000 13 17 u16 device_rev; 18 19 enum dibx000_i2c_interface selected_interface; 20 21 /* struct i2c_adapter tuner_i2c_adap; */ 22 struct i2c_adapter gated_tuner_i2c_adap; 23 struct i2c_adapter master_i2c_adap_gpio12; 24 struct i2c_adapter master_i2c_adap_gpio34; 25 struct i2c_adapter master_i2c_adap_gpio67; 26 27 struct i2c_adapter *i2c_adap; 28 u8 i2c_addr; 29 30 u16 base_reg; 31 32 /* for the I2C transfer */ 33 struct i2c_msg msg[34]; 34 u8 i2c_write_buffer[8]; 35 u8 i2c_read_buffer[2]; 36 struct mutex i2c_buffer_lock; 37 }; 38 39 extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, 40 u16 device_rev, struct i2c_adapter *i2c_adap, 41 u8 i2c_addr); 42 extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master 43 *mst, 44 enum dibx000_i2c_interface 45 intf, int gating); 46 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst); 47 extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst); 48 extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed); 49 50 extern u32 systime(void); 51 52 #define BAND_LBAND 0x01 53 #define BAND_UHF 0x02 54 #define BAND_VHF 0x04 55 #define BAND_SBAND 0x08 56 #define BAND_FM 0x10 57 #define BAND_CBAND 0x20 58 59 #define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \ 60 (freq_kHz) <= 115000 ? BAND_FM : \ 61 (freq_kHz) <= 250000 ? BAND_VHF : \ 62 (freq_kHz) <= 863000 ? BAND_UHF : \ 63 (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND ) 64 65 struct dibx000_agc_config { 66 /* defines the capabilities of this AGC-setting - using the BAND_-defines */ 67 u8 band_caps; 68 69 u16 setup; 70 71 u16 inv_gain; 72 u16 time_stabiliz; 73 74 u8 alpha_level; 75 u16 thlock; 76 77 u8 wbd_inv; 78 u16 wbd_ref; 79 u8 wbd_sel; 80 u8 wbd_alpha; 81 82 u16 agc1_max; 83 u16 agc1_min; 84 u16 agc2_max; 85 u16 agc2_min; 86 87 u8 agc1_pt1; 88 u8 agc1_pt2; 89 u8 agc1_pt3; 90 91 u8 agc1_slope1; 92 u8 agc1_slope2; 93 94 u8 agc2_pt1; 95 u8 agc2_pt2; 96 97 u8 agc2_slope1; 98 u8 agc2_slope2; 99 100 u8 alpha_mant; 101 u8 alpha_exp; 102 103 u8 beta_mant; 104 u8 beta_exp; 105 106 u8 perform_agc_softsplit; 107 108 struct { 109 u16 min; 110 u16 max; 111 u16 min_thres; 112 u16 max_thres; 113 } split; 114 }; 115 116 struct dibx000_bandwidth_config { 117 u32 internal; 118 u32 sampling; 119 120 u8 pll_prediv; 121 u8 pll_ratio; 122 u8 pll_range; 123 u8 pll_reset; 124 u8 pll_bypass; 125 126 u8 enable_refdiv; 127 u8 bypclk_div; 128 u8 IO_CLK_en_core; 129 u8 ADClkSrc; 130 u8 modulo; 131 132 u16 sad_cfg; 133 134 u32 ifreq; 135 u32 timf; 136 137 u32 xtal_hz; 138 }; 139 140 enum dibx000_adc_states { 141 DIBX000_SLOW_ADC_ON = 0, 142 DIBX000_SLOW_ADC_OFF, 143 DIBX000_ADC_ON, 144 DIBX000_ADC_OFF, 145 DIBX000_VBG_ENABLE, 146 DIBX000_VBG_DISABLE, 147 }; 148 149 #define BANDWIDTH_TO_KHZ(v) ((v) / 1000) 150 #define BANDWIDTH_TO_HZ(v) ((v) * 1000) 151 152 /* Chip output mode. */ 153 #define OUTMODE_HIGH_Z 0 154 #define OUTMODE_MPEG2_PAR_GATED_CLK 1 155 #define OUTMODE_MPEG2_PAR_CONT_CLK 2 156 #define OUTMODE_MPEG2_SERIAL 7 157 #define OUTMODE_DIVERSITY 4 158 #define OUTMODE_MPEG2_FIFO 5 159 #define OUTMODE_ANALOG_ADC 6 160 161 #define INPUT_MODE_OFF 0x11 162 #define INPUT_MODE_DIVERSITY 0x12 163 #define INPUT_MODE_MPEG 0x13 164 165 enum frontend_tune_state { 166 CT_TUNER_START = 10, 167 CT_TUNER_STEP_0, 168 CT_TUNER_STEP_1, 169 CT_TUNER_STEP_2, 170 CT_TUNER_STEP_3, 171 CT_TUNER_STEP_4, 172 CT_TUNER_STEP_5, 173 CT_TUNER_STEP_6, 174 CT_TUNER_STEP_7, 175 CT_TUNER_STOP, 176 177 CT_AGC_START = 20, 178 CT_AGC_STEP_0, 179 CT_AGC_STEP_1, 180 CT_AGC_STEP_2, 181 CT_AGC_STEP_3, 182 CT_AGC_STEP_4, 183 CT_AGC_STOP, 184 185 CT_DEMOD_START = 30, 186 CT_DEMOD_STEP_1, 187 CT_DEMOD_STEP_2, 188 CT_DEMOD_STEP_3, 189 CT_DEMOD_STEP_4, 190 CT_DEMOD_STEP_5, 191 CT_DEMOD_STEP_6, 192 CT_DEMOD_STEP_7, 193 CT_DEMOD_STEP_8, 194 CT_DEMOD_STEP_9, 195 CT_DEMOD_STEP_10, 196 CT_DEMOD_SEARCH_NEXT = 41, 197 CT_DEMOD_STEP_LOCKED, 198 CT_DEMOD_STOP, 199 200 CT_DONE = 100, 201 CT_SHUTDOWN, 202 203 }; 204 205 struct dvb_frontend_parametersContext { 206 #define CHANNEL_STATUS_PARAMETERS_UNKNOWN 0x01 207 #define CHANNEL_STATUS_PARAMETERS_SET 0x02 208 u8 status; 209 u32 tune_time_estimation[2]; 210 s32 tps_available; 211 u16 tps[9]; 212 }; 213 214 #define FE_STATUS_TUNE_FAILED 0 215 #define FE_STATUS_TUNE_TIMED_OUT -1 216 #define FE_STATUS_TUNE_TIME_TOO_SHORT -2 217 #define FE_STATUS_TUNE_PENDING -3 218 #define FE_STATUS_STD_SUCCESS -4 219 #define FE_STATUS_FFT_SUCCESS -5 220 #define FE_STATUS_DEMOD_SUCCESS -6 221 #define FE_STATUS_LOCKED -7 222 #define FE_STATUS_DATA_LOCKED -8 223 224 #define FE_CALLBACK_TIME_NEVER 0xffffffff 225 226 #define ABS(x) ((x < 0) ? (-x) : (x)) 227 228 #define DATA_BUS_ACCESS_MODE_8BIT 0x01 229 #define DATA_BUS_ACCESS_MODE_16BIT 0x02 230 #define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10 231 232 struct dibGPIOFunction { 233 #define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1 234 #define BOARD_GPIO_COMPONENT_DEMOD 2 235 u8 component; 236 237 #define BOARD_GPIO_FUNCTION_BOARD_ON 1 238 #define BOARD_GPIO_FUNCTION_BOARD_OFF 2 239 #define BOARD_GPIO_FUNCTION_COMPONENT_ON 3 240 #define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4 241 #define BOARD_GPIO_FUNCTION_SUBBAND_PWM 5 242 #define BOARD_GPIO_FUNCTION_SUBBAND_GPIO 6 243 u8 function; 244 245 /* mask, direction and value are used specify which GPIO to change GPIO0 246 * is LSB and possible GPIO31 is MSB. The same bit-position as in the 247 * mask is used for the direction and the value. Direction == 1 is OUT, 248 * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN 249 * value has no meaning. 250 * 251 * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be 252 * used to do the PWM. Direction gives the PWModulator to be used. 253 * Value gives the PWM value in device-dependent scale. 254 */ 255 u32 mask; 256 u32 direction; 257 u32 value; 258 }; 259 260 #define MAX_NB_SUBBANDS 8 261 struct dibSubbandSelection { 262 u8 size; /* Actual number of subbands. */ 263 struct { 264 u16 f_mhz; 265 struct dibGPIOFunction gpio; 266 } subband[MAX_NB_SUBBANDS]; 267 }; 268 269 #define DEMOD_TIMF_SET 0x00 270 #define DEMOD_TIMF_GET 0x01 271 #define DEMOD_TIMF_UPDATE 0x02 272 273 #define MPEG_ON_DIBTX 1 274 #define DIV_ON_DIBTX 2 275 #define ADC_ON_DIBTX 3 276 #define DEMOUT_ON_HOSTBUS 4 277 #define DIBTX_ON_HOSTBUS 5 278 #define MPEG_ON_HOSTBUS 6 279 280 #endif 281