1 2menuconfig CRYPTO_HW 3 bool "Hardware crypto devices" 4 default y 5 ---help--- 6 Say Y here to get to see options for hardware crypto devices and 7 processors. This option alone does not add any kernel code. 8 9 If you say N, all options in this submenu will be skipped and disabled. 10 11if CRYPTO_HW 12 13config CRYPTO_DEV_PADLOCK 14 tristate "Support for VIA PadLock ACE" 15 depends on X86 && !UML 16 help 17 Some VIA processors come with an integrated crypto engine 18 (so called VIA PadLock ACE, Advanced Cryptography Engine) 19 that provides instructions for very fast cryptographic 20 operations with supported algorithms. 21 22 The instructions are used only when the CPU supports them. 23 Otherwise software encryption is used. 24 25config CRYPTO_DEV_PADLOCK_AES 26 tristate "PadLock driver for AES algorithm" 27 depends on CRYPTO_DEV_PADLOCK 28 select CRYPTO_BLKCIPHER 29 select CRYPTO_AES 30 help 31 Use VIA PadLock for AES algorithm. 32 33 Available in VIA C3 and newer CPUs. 34 35 If unsure say M. The compiled module will be 36 called padlock-aes. 37 38config CRYPTO_DEV_PADLOCK_SHA 39 tristate "PadLock driver for SHA1 and SHA256 algorithms" 40 depends on CRYPTO_DEV_PADLOCK 41 select CRYPTO_HASH 42 select CRYPTO_SHA1 43 select CRYPTO_SHA256 44 help 45 Use VIA PadLock for SHA1/SHA256 algorithms. 46 47 Available in VIA C7 and newer processors. 48 49 If unsure say M. The compiled module will be 50 called padlock-sha. 51 52config CRYPTO_DEV_GEODE 53 tristate "Support for the Geode LX AES engine" 54 depends on X86_32 && PCI 55 select CRYPTO_ALGAPI 56 select CRYPTO_BLKCIPHER 57 help 58 Say 'Y' here to use the AMD Geode LX processor on-board AES 59 engine for the CryptoAPI AES algorithm. 60 61 To compile this driver as a module, choose M here: the module 62 will be called geode-aes. 63 64config ZCRYPT 65 tristate "Support for PCI-attached cryptographic adapters" 66 depends on S390 67 select HW_RANDOM 68 help 69 Select this option if you want to use a PCI-attached cryptographic 70 adapter like: 71 + PCI Cryptographic Accelerator (PCICA) 72 + PCI Cryptographic Coprocessor (PCICC) 73 + PCI-X Cryptographic Coprocessor (PCIXCC) 74 + Crypto Express2 Coprocessor (CEX2C) 75 + Crypto Express2 Accelerator (CEX2A) 76 + Crypto Express3 Coprocessor (CEX3C) 77 + Crypto Express3 Accelerator (CEX3A) 78 79config CRYPTO_SHA1_S390 80 tristate "SHA1 digest algorithm" 81 depends on S390 82 select CRYPTO_HASH 83 help 84 This is the s390 hardware accelerated implementation of the 85 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). 86 87 It is available as of z990. 88 89config CRYPTO_SHA256_S390 90 tristate "SHA256 digest algorithm" 91 depends on S390 92 select CRYPTO_HASH 93 help 94 This is the s390 hardware accelerated implementation of the 95 SHA256 secure hash standard (DFIPS 180-2). 96 97 It is available as of z9. 98 99config CRYPTO_SHA512_S390 100 tristate "SHA384 and SHA512 digest algorithm" 101 depends on S390 102 select CRYPTO_HASH 103 help 104 This is the s390 hardware accelerated implementation of the 105 SHA512 secure hash standard. 106 107 It is available as of z10. 108 109config CRYPTO_DES_S390 110 tristate "DES and Triple DES cipher algorithms" 111 depends on S390 112 select CRYPTO_ALGAPI 113 select CRYPTO_BLKCIPHER 114 help 115 This is the s390 hardware accelerated implementation of the 116 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). 117 118 As of z990 the ECB and CBC mode are hardware accelerated. 119 As of z196 the CTR mode is hardware accelerated. 120 121config CRYPTO_AES_S390 122 tristate "AES cipher algorithms" 123 depends on S390 124 select CRYPTO_ALGAPI 125 select CRYPTO_BLKCIPHER 126 help 127 This is the s390 hardware accelerated implementation of the 128 AES cipher algorithms (FIPS-197). 129 130 As of z9 the ECB and CBC modes are hardware accelerated 131 for 128 bit keys. 132 As of z10 the ECB and CBC modes are hardware accelerated 133 for all AES key sizes. 134 As of z196 the CTR mode is hardware accelerated for all AES 135 key sizes and XTS mode is hardware accelerated for 256 and 136 512 bit keys. 137 138config S390_PRNG 139 tristate "Pseudo random number generator device driver" 140 depends on S390 141 default "m" 142 help 143 Select this option if you want to use the s390 pseudo random number 144 generator. The PRNG is part of the cryptographic processor functions 145 and uses triple-DES to generate secure random numbers like the 146 ANSI X9.17 standard. User-space programs access the 147 pseudo-random-number device through the char device /dev/prandom. 148 149 It is available as of z9. 150 151config CRYPTO_GHASH_S390 152 tristate "GHASH digest algorithm" 153 depends on S390 154 select CRYPTO_HASH 155 help 156 This is the s390 hardware accelerated implementation of the 157 GHASH message digest algorithm for GCM (Galois/Counter Mode). 158 159 It is available as of z196. 160 161config CRYPTO_DEV_MV_CESA 162 tristate "Marvell's Cryptographic Engine" 163 depends on PLAT_ORION 164 select CRYPTO_ALGAPI 165 select CRYPTO_AES 166 select CRYPTO_BLKCIPHER2 167 select CRYPTO_HASH 168 help 169 This driver allows you to utilize the Cryptographic Engines and 170 Security Accelerator (CESA) which can be found on the Marvell Orion 171 and Kirkwood SoCs, such as QNAP's TS-209. 172 173 Currently the driver supports AES in ECB and CBC mode without DMA. 174 175config CRYPTO_DEV_NIAGARA2 176 tristate "Niagara2 Stream Processing Unit driver" 177 select CRYPTO_DES 178 select CRYPTO_ALGAPI 179 depends on SPARC64 180 help 181 Each core of a Niagara2 processor contains a Stream 182 Processing Unit, which itself contains several cryptographic 183 sub-units. One set provides the Modular Arithmetic Unit, 184 used for SSL offload. The other set provides the Cipher 185 Group, which can perform encryption, decryption, hashing, 186 checksumming, and raw copies. 187 188config CRYPTO_DEV_HIFN_795X 189 tristate "Driver HIFN 795x crypto accelerator chips" 190 select CRYPTO_DES 191 select CRYPTO_ALGAPI 192 select CRYPTO_BLKCIPHER 193 select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG 194 depends on PCI 195 depends on !ARCH_DMA_ADDR_T_64BIT 196 help 197 This option allows you to have support for HIFN 795x crypto adapters. 198 199config CRYPTO_DEV_HIFN_795X_RNG 200 bool "HIFN 795x random number generator" 201 depends on CRYPTO_DEV_HIFN_795X 202 help 203 Select this option if you want to enable the random number generator 204 on the HIFN 795x crypto adapters. 205 206source drivers/crypto/caam/Kconfig 207 208config CRYPTO_DEV_TALITOS 209 tristate "Talitos Freescale Security Engine (SEC)" 210 select CRYPTO_ALGAPI 211 select CRYPTO_AUTHENC 212 select HW_RANDOM 213 depends on FSL_SOC 214 help 215 Say 'Y' here to use the Freescale Security Engine (SEC) 216 to offload cryptographic algorithm computation. 217 218 The Freescale SEC is present on PowerQUICC 'E' processors, such 219 as the MPC8349E and MPC8548E. 220 221 To compile this driver as a module, choose M here: the module 222 will be called talitos. 223 224config CRYPTO_DEV_IXP4XX 225 tristate "Driver for IXP4xx crypto hardware acceleration" 226 depends on ARCH_IXP4XX 227 select CRYPTO_DES 228 select CRYPTO_ALGAPI 229 select CRYPTO_AUTHENC 230 select CRYPTO_BLKCIPHER 231 help 232 Driver for the IXP4xx NPE crypto engine. 233 234config CRYPTO_DEV_PPC4XX 235 tristate "Driver AMCC PPC4xx crypto accelerator" 236 depends on PPC && 4xx 237 select CRYPTO_HASH 238 select CRYPTO_ALGAPI 239 select CRYPTO_BLKCIPHER 240 help 241 This option allows you to have support for AMCC crypto acceleration. 242 243config CRYPTO_DEV_OMAP_SHAM 244 tristate "Support for OMAP SHA1/MD5 hw accelerator" 245 depends on ARCH_OMAP2 || ARCH_OMAP3 246 select CRYPTO_SHA1 247 select CRYPTO_MD5 248 help 249 OMAP processors have SHA1/MD5 hw accelerator. Select this if you 250 want to use the OMAP module for SHA1/MD5 algorithms. 251 252config CRYPTO_DEV_OMAP_AES 253 tristate "Support for OMAP AES hw engine" 254 depends on ARCH_OMAP2 || ARCH_OMAP3 255 select CRYPTO_AES 256 help 257 OMAP processors have AES module accelerator. Select this if you 258 want to use the OMAP module for AES algorithms. 259 260config CRYPTO_DEV_PICOXCELL 261 tristate "Support for picoXcell IPSEC and Layer2 crypto engines" 262 depends on ARCH_PICOXCELL && HAVE_CLK 263 select CRYPTO_AES 264 select CRYPTO_AUTHENC 265 select CRYPTO_ALGAPI 266 select CRYPTO_DES 267 select CRYPTO_CBC 268 select CRYPTO_ECB 269 select CRYPTO_SEQIV 270 help 271 This option enables support for the hardware offload engines in the 272 Picochip picoXcell SoC devices. Select this for IPSEC ESP offload 273 and for 3gpp Layer 2 ciphering support. 274 275 Saying m here will build a module named pipcoxcell_crypto. 276 277config CRYPTO_DEV_S5P 278 tristate "Support for Samsung S5PV210 crypto accelerator" 279 depends on ARCH_S5PV210 280 select CRYPTO_AES 281 select CRYPTO_ALGAPI 282 select CRYPTO_BLKCIPHER 283 help 284 This option allows you to have support for S5P crypto acceleration. 285 Select this to offload Samsung S5PV210 or S5PC110 from AES 286 algorithms execution. 287 288config CRYPTO_DEV_TEGRA_AES 289 tristate "Support for TEGRA AES hw engine" 290 depends on ARCH_TEGRA 291 select CRYPTO_AES 292 help 293 TEGRA processors have AES module accelerator. Select this if you 294 want to use the TEGRA module for AES algorithms. 295 296 To compile this driver as a module, choose M here: the module 297 will be called tegra-aes. 298 299endif # CRYPTO_HW 300