1 #ifndef _IOP13XX_HW_H_
2 #define _IOP13XX_HW_H_
3
4 #ifndef __ASSEMBLY__
5 /* The ATU offsets can change based on the strapping */
6 extern u32 iop13xx_atux_pmmr_offset;
7 extern u32 iop13xx_atue_pmmr_offset;
8 void iop13xx_init_early(void);
9 void iop13xx_init_irq(void);
10 void iop13xx_map_io(void);
11 void iop13xx_platform_init(void);
12 void iop13xx_add_tpmi_devices(void);
13 void iop13xx_init_irq(void);
14 void iop13xx_restart(char, const char *);
15
16 /* CPUID CP6 R0 Page 0 */
iop13xx_cpu_id(void)17 static inline int iop13xx_cpu_id(void)
18 {
19 int id;
20 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
21 return id;
22 }
23
24 /* WDTCR CP6 R7 Page 9 */
read_wdtcr(void)25 static inline u32 read_wdtcr(void)
26 {
27 u32 val;
28 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
29 return val;
30 }
write_wdtcr(u32 val)31 static inline void write_wdtcr(u32 val)
32 {
33 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
34 }
35
36 /* WDTSR CP6 R8 Page 9 */
read_wdtsr(void)37 static inline u32 read_wdtsr(void)
38 {
39 u32 val;
40 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
41 return val;
42 }
write_wdtsr(u32 val)43 static inline void write_wdtsr(u32 val)
44 {
45 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
46 }
47
48 /* RCSR - Reset Cause Status Register */
read_rcsr(void)49 static inline u32 read_rcsr(void)
50 {
51 u32 val;
52 asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
53 return val;
54 }
55
56 extern unsigned long get_iop_tick_rate(void);
57 #endif
58
59 /*
60 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
61 */
62 #define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
63 #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
64
65 /* PCI MAP
66 * bus range cpu phys cpu virt note
67 * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
68 * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
69 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
70 *
71 * IO MAP
72 * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
73 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
74 */
75 #define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
76 #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
77 #define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
78 #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
79 #define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
80 #define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
81 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
82 #define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
83 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
84 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
85 (IOP13XX_PCIX_LOWER_IO_PA\
86 - IOP13XX_PCIX_LOWER_IO_VA))
87
88 #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
89 #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
90 #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
91 #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
92 IOP13XX_PCIX_LOWER_MEM_BA)
93 #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
94 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
95 #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
96 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
97
98 #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
99 #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
100 #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
101 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
102 #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
103 IOP13XX_PCIX_LOWER_MEM_BA)
104
105 /* PCI-E ranges */
106 #define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
107 #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
108 #define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
109 #define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
110 #define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
111 #define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
112 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
113 #define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
114 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
115 #define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
116 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
117 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
118 (IOP13XX_PCIE_LOWER_IO_PA\
119 - IOP13XX_PCIE_LOWER_IO_VA))
120
121 #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
122 #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
123 #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
124 #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
125 IOP13XX_PCIE_LOWER_MEM_BA)
126 #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
127 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
128 #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
129 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
130
131 /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
132 #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
133 #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
134 #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
135 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
136 #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
137 IOP13XX_PCIE_LOWER_MEM_BA)
138
139 /* PBI Ranges */
140 #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
141 #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
142 #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
143 #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
144 #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
145 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
146
147 /*
148 * IOP13XX chipset registers
149 */
150 #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
151 #define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
152 #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
153 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
154 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
155 #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
156 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
157 #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
158 (IOP13XX_PMMR_PHYS_MEM_BASE\
159 - IOP13XX_PMMR_VIRT_MEM_BASE))
160 #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
161 (IOP13XX_PMMR_PHYS_MEM_BASE\
162 - IOP13XX_PMMR_VIRT_MEM_BASE))
163 #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
164 #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
165 #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
166 #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
167 #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
168 #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
169 #define IOP13XX_PMMR_SIZE 0x00080000
170
171 /*=================== Defines for Platform Devices =====================*/
172 #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
173 #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
174 #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
175 #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
176
177 #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
178 #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
179 #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
180 #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
181 #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
182 #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
183
184 /* ATU selection flags */
185 /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
186 #define IOP13XX_INIT_ATU_DEFAULT (0)
187 #define IOP13XX_INIT_ATU_ATUX (1 << 0)
188 #define IOP13XX_INIT_ATU_ATUE (1 << 1)
189 #define IOP13XX_INIT_ATU_NONE (1 << 2)
190
191 /* UART selection flags */
192 /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
193 #define IOP13XX_INIT_UART_DEFAULT (0)
194 #define IOP13XX_INIT_UART_0 (1 << 0)
195 #define IOP13XX_INIT_UART_1 (1 << 1)
196
197 /* I2C selection flags */
198 /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
199 #define IOP13XX_INIT_I2C_DEFAULT (0)
200 #define IOP13XX_INIT_I2C_0 (1 << 0)
201 #define IOP13XX_INIT_I2C_1 (1 << 1)
202 #define IOP13XX_INIT_I2C_2 (1 << 2)
203
204 /* ADMA selection flags */
205 /* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
206 #define IOP13XX_INIT_ADMA_DEFAULT (0)
207 #define IOP13XX_INIT_ADMA_0 (1 << 0)
208 #define IOP13XX_INIT_ADMA_1 (1 << 1)
209 #define IOP13XX_INIT_ADMA_2 (1 << 2)
210
211 /* Platform devices */
212 #define IQ81340_NUM_UART 2
213 #define IQ81340_NUM_I2C 3
214 #define IQ81340_NUM_PHYS_MAP_FLASH 1
215 #define IQ81340_NUM_ADMA 3
216 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
217 IQ81340_NUM_I2C + \
218 IQ81340_NUM_PHYS_MAP_FLASH + \
219 IQ81340_NUM_ADMA)
220
221 /*========================== PMMR offsets for key registers ============*/
222 #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
223 #define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
224 #define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
225 #define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
226 #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
227 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
228 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580
229 #define IOP13XX_MU_PMMR_OFFSET 0x00004000
230 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
231 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
232
233 #define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
234 #define IOP13XX_CONTROLLER_ONLY (1 << 14)
235 #define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
236
237 #define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
238 #define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
239 IOP13XX_PMON_PMMR_OFFSET)
240 #define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
241 IOP13XX_PMON_PMMR_OFFSET)
242
243 #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
244 #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
245 #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
246 #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
247
248 #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
249 #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
250 #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
251 #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
252
253 #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
254 #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
255 #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
256 #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
257
258 #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
259 #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
260
261 /*================================ATU===================================*/
262 #define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
263 iop13xx_atux_pmmr_offset + (ofs))
264
265 #define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
266 iop13xx_atux_pmmr_offset + 0x2)
267
268 #define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
269 iop13xx_atux_pmmr_offset + 0x4)
270 #define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
271 iop13xx_atux_pmmr_offset + 0x6)
272
273 #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
274 #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
275 #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
276 #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
277 #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
278 #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
279 #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
280 #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
281 #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
282 #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
283 #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
284 #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
285 #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
286 #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
287 #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
288 #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
289 #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
290 #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
291 #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
292 #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
293 #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
294 #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
295 #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
296 #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
297
298 #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
299 #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
300 #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
301 #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
302 #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
303 #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
304 #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
305 #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
306 #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
307 #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
308 #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
309 #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
310 #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
311 #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
312
313 #define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
314 #define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
315 #define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
316 #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
317 #define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
318 #define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
319
320 #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
321 #define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
322 #define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
323 #define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
324 #define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
325 #define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
326 #define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
327 #define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
328 #define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
329 #define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
330 #define IOP13XX_ATUX_STAT_BIST (1 << 8 )
331 #define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
332 #define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
333 #define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
334 #define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
335 #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
336 #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
337
338 #define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
339 #define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
340 #define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
341
342 #define IOP13XX_ATUX_IALR_DISABLE 0x00000001
343 #define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
344
345 #define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
346 iop13xx_atue_pmmr_offset + (ofs))
347
348 #define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
349 iop13xx_atue_pmmr_offset + 0x2)
350 #define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
351 iop13xx_atue_pmmr_offset + 0x4)
352 #define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
353 iop13xx_atue_pmmr_offset + 0x6)
354
355 #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
356 #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
357 #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
358 #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
359 #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
360 #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
361 #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
362 #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
363 #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
364 #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
365 #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
366 #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
367 #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
368 #define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
369 #define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
370 #define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
371 iop13xx_atue_pmmr_offset + 0xe2)
372 #define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
373 #define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
374 #define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
375 #define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
376 #define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
377 #define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
378 #define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
379 #define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
380 #define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
381
382 #define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
383 #define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
384 #define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
385 #define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
386 #define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
387 #define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
388
389 #define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
390 #define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
391
392 #define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
393 #define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
394 #define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
395 #define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
396 #define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
397 #define IOP13XX_ATUE_OCCAR_EXT_REG (8)
398 #define IOP13XX_ATUE_OCCAR_REG (2)
399
400 #define IOP13XX_ATUE_PCSR_BUS_NUM (24)
401 #define IOP13XX_ATUE_PCSR_DEV_NUM (19)
402 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
403 #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
404 #define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
405 #define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
406 #define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
407
408 #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
409 #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
410 #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
411
412 #define IOP13XX_ATUE_PCSR_CORE_RESET (8)
413 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
414
415 #define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
416 #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
417 #define IOP13XX_ATUE_STAT_PME (1 << 27)
418 #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
419 #define IOP13XX_ATUE_STAT_IVM (1 << 25)
420 #define IOP13XX_ATUE_STAT_BIST (1 << 24)
421 #define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
422 #define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
423 #define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
424 #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
425 #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
426 #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
427 #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
428 #define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
429 #define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
430 #define IOP13XX_ATUE_STAT_CRS (1 << 7 )
431 #define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
432 #define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
433 #define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
434 #define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
435 #define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
436 #define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
437 #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
438
439 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
440 #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
441 #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
442 #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
443 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
444 #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
445 #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
446 #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
447 #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
448 #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
449 #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
450 #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
451 #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
452 #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
453 #define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
454
455 #define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
456 #define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
457 #define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
458 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
459 /*=======================================================================*/
460
461 /*============================MESSAGING UNIT=============================*/
462 #define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
463 (ofs))
464
465 #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
466 #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
467 #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
468 #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
469 #define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
470 #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
471 #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
472 #define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
473 #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
474 #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
475 #define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
476 #define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
477 #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
478 #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
479 #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
480 #define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
481
482 #define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
483 #define IOP13XX_MU_BASE_PHYS (0xff000000)
484 #define IOP13XX_MU_BASE_PCI (0xff000000)
485 #define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
486 #define IOP13XX_MU_MIMR_CORE_SELECT (15)
487 /*=======================================================================*/
488
489 /*==============================ADMA UNITS===============================*/
490 #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
491 #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
492
493 /*==============================XSI BRIDGE===============================*/
494 #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
495 #define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
496 #define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
497 #define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
498 IOP13XX_PMMR_VIRT_TO_PHYS(\
499 IOP13XX_ATUE_OCCDR))\
500 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
501 #define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
502 IOP13XX_PMMR_VIRT_TO_PHYS(\
503 IOP13XX_ATUX_OCCDR))\
504 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
505 /*=======================================================================*/
506
507 #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
508 (ofs))
509
510 #define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
511 #define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
512 #define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
513 #define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
514 #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
515 #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
516
517 #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
518
519 /* Watchdog timer definitions */
520 #define IOP_WDTCR_EN_ARM 0x1e1e1e1e
521 #define IOP_WDTCR_EN 0xe1e1e1e1
522 #define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
523 #define IOP_WDTCR_DIS 0xf1f1f1f1
524 #define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
525 #define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
526 #define IOP13XX_WDTCR_IB_RESET (1 << 0)
527
528 #endif /* _IOP13XX_HW_H_ */
529