1 /* arch/arm/mach-s3c2410/include/mach/irqs.h 2 * 3 * Copyright (c) 2003-2005 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12 #ifndef __ASM_ARCH_IRQS_H 13 #define __ASM_ARCH_IRQS_H __FILE__ 14 15 /* we keep the first set of CPU IRQs out of the range of 16 * the ISA space, so that the PC104 has them to itself 17 * and we don't end up having to do horrible things to the 18 * standard ISA drivers.... 19 */ 20 21 #define S3C2410_CPUIRQ_OFFSET (16) 22 23 #define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) 24 25 /* main cpu interrupts */ 26 #define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ 27 #define IRQ_EINT1 S3C2410_IRQ(1) 28 #define IRQ_EINT2 S3C2410_IRQ(2) 29 #define IRQ_EINT3 S3C2410_IRQ(3) 30 #define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ 31 #define IRQ_EINT8t23 S3C2410_IRQ(5) 32 #define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ 33 #define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ 34 #define IRQ_BATT_FLT S3C2410_IRQ(7) 35 #define IRQ_TICK S3C2410_IRQ(8) /* 24 */ 36 #define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ 37 #define IRQ_TIMER0 S3C2410_IRQ(10) 38 #define IRQ_TIMER1 S3C2410_IRQ(11) 39 #define IRQ_TIMER2 S3C2410_IRQ(12) 40 #define IRQ_TIMER3 S3C2410_IRQ(13) 41 #define IRQ_TIMER4 S3C2410_IRQ(14) 42 #define IRQ_UART2 S3C2410_IRQ(15) 43 #define IRQ_LCD S3C2410_IRQ(16) /* 32 */ 44 #define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ 45 #define IRQ_DMA1 S3C2410_IRQ(18) 46 #define IRQ_DMA2 S3C2410_IRQ(19) 47 #define IRQ_DMA3 S3C2410_IRQ(20) 48 #define IRQ_SDI S3C2410_IRQ(21) 49 #define IRQ_SPI0 S3C2410_IRQ(22) 50 #define IRQ_UART1 S3C2410_IRQ(23) 51 #define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ 52 #define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ 53 #define IRQ_USBD S3C2410_IRQ(25) 54 #define IRQ_USBH S3C2410_IRQ(26) 55 #define IRQ_IIC S3C2410_IRQ(27) 56 #define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ 57 #define IRQ_SPI1 S3C2410_IRQ(29) 58 #define IRQ_RTC S3C2410_IRQ(30) 59 #define IRQ_ADCPARENT S3C2410_IRQ(31) 60 61 /* interrupts generated from the external interrupts sources */ 62 #define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ 63 #define IRQ_EINT5 S3C2410_IRQ(33) 64 #define IRQ_EINT6 S3C2410_IRQ(34) 65 #define IRQ_EINT7 S3C2410_IRQ(35) 66 #define IRQ_EINT8 S3C2410_IRQ(36) 67 #define IRQ_EINT9 S3C2410_IRQ(37) 68 #define IRQ_EINT10 S3C2410_IRQ(38) 69 #define IRQ_EINT11 S3C2410_IRQ(39) 70 #define IRQ_EINT12 S3C2410_IRQ(40) 71 #define IRQ_EINT13 S3C2410_IRQ(41) 72 #define IRQ_EINT14 S3C2410_IRQ(42) 73 #define IRQ_EINT15 S3C2410_IRQ(43) 74 #define IRQ_EINT16 S3C2410_IRQ(44) 75 #define IRQ_EINT17 S3C2410_IRQ(45) 76 #define IRQ_EINT18 S3C2410_IRQ(46) 77 #define IRQ_EINT19 S3C2410_IRQ(47) 78 #define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ 79 #define IRQ_EINT21 S3C2410_IRQ(49) 80 #define IRQ_EINT22 S3C2410_IRQ(50) 81 #define IRQ_EINT23 S3C2410_IRQ(51) 82 83 #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) 84 #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) 85 86 #define IRQ_LCD_FIFO S3C2410_IRQ(52) 87 #define IRQ_LCD_FRAME S3C2410_IRQ(53) 88 89 /* IRQs for the interal UARTs, and ADC 90 * these need to be ordered in number of appearance in the 91 * SUBSRC mask register 92 */ 93 94 #define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) 95 96 #define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ 97 #define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) 98 #define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) 99 100 #define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ 101 #define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) 102 #define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) 103 104 #define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ 105 #define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) 106 #define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) 107 108 #define IRQ_TC S3C2410_IRQSUB(9) 109 #define IRQ_ADC S3C2410_IRQSUB(10) 110 111 /* extra irqs for s3c2412 */ 112 113 #define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) 114 115 #define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) 116 #define IRQ_S3C2412_CF S3C2410_IRQSUB(14) 117 118 119 #define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) 120 #define IRQ_S3C2416_DMA S3C2410_IRQ(17) 121 #define IRQ_S3C2416_UART3 S3C2410_IRQ(18) 122 #define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) 123 #define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) 124 125 #define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) 126 #define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) 127 #define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) 128 #define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) 129 #define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) 130 #define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) 131 #define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) 132 #define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) 133 #define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) 134 #define IRQ_S32416_WDT S3C2410_IRQSUB(27) 135 #define IRQ_S32416_AC97 S3C2410_IRQSUB(28) 136 137 138 /* extra irqs for s3c2440 */ 139 140 #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ 141 #define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ 142 #define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) 143 #define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) 144 145 /* irqs for s3c2443 */ 146 147 #define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ 148 #define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ 149 #define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ 150 #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ 151 #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ 152 153 #define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ 154 155 #define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 156 #define IRQ_HSMMC1 IRQ_S3C2443_HSMMC 157 158 #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) 159 #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) 160 #define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) 161 #define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) 162 163 #define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) 164 #define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) 165 #define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) 166 #define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) 167 #define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) 168 #define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) 169 170 /* UART3 */ 171 #define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) 172 #define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) 173 #define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) 174 175 #define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) 176 #define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) 177 178 #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) 179 #define NR_IRQS (IRQ_S3C2443_AC97+1) 180 #else 181 #define NR_IRQS (IRQ_S3C2440_AC97+1) 182 #endif 183 184 /* compatibility define. */ 185 #define IRQ_UART3 IRQ_S3C2443_UART3 186 #define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 187 #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 188 #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 189 190 #define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 191 #define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 192 193 #ifdef CONFIG_CPU_S3C2440 194 #define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 195 #else 196 #define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 197 #endif 198 199 /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ 200 #define FIQ_START IRQ_EINT0 201 202 #endif /* __ASM_ARCH_IRQ_H */ 203