1 /* 2 saa7146.h - definitions philips saa7146 based cards 3 Copyright (C) 1999 Nathan Laredo (laredo@gnu.org) 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 #ifndef __SAA7146_REG__ 21 #define __SAA7146_REG__ 22 #define SAA7146_BASE_ODD1 0x00 23 #define SAA7146_BASE_EVEN1 0x04 24 #define SAA7146_PROT_ADDR1 0x08 25 #define SAA7146_PITCH1 0x0c 26 #define SAA7146_PAGE1 0x10 27 #define SAA7146_NUM_LINE_BYTE1 0x14 28 #define SAA7146_BASE_ODD2 0x18 29 #define SAA7146_BASE_EVEN2 0x1c 30 #define SAA7146_PROT_ADDR2 0x20 31 #define SAA7146_PITCH2 0x24 32 #define SAA7146_PAGE2 0x28 33 #define SAA7146_NUM_LINE_BYTE2 0x2c 34 #define SAA7146_BASE_ODD3 0x30 35 #define SAA7146_BASE_EVEN3 0x34 36 #define SAA7146_PROT_ADDR3 0x38 37 #define SAA7146_PITCH3 0x3c 38 #define SAA7146_PAGE3 0x40 39 #define SAA7146_NUM_LINE_BYTE3 0x44 40 #define SAA7146_PCI_BT_V1 0x48 41 #define SAA7146_PCI_BT_V2 0x49 42 #define SAA7146_PCI_BT_V3 0x4a 43 #define SAA7146_PCI_BT_DEBI 0x4b 44 #define SAA7146_PCI_BT_A 0x4c 45 #define SAA7146_DD1_INIT 0x50 46 #define SAA7146_DD1_STREAM_B 0x54 47 #define SAA7146_DD1_STREAM_A 0x56 48 #define SAA7146_BRS_CTRL 0x58 49 #define SAA7146_HPS_CTRL 0x5c 50 #define SAA7146_HPS_V_SCALE 0x60 51 #define SAA7146_HPS_V_GAIN 0x64 52 #define SAA7146_HPS_H_PRESCALE 0x68 53 #define SAA7146_HPS_H_SCALE 0x6c 54 #define SAA7146_BCS_CTRL 0x70 55 #define SAA7146_CHROMA_KEY_RANGE 0x74 56 #define SAA7146_CLIP_FORMAT_CTRL 0x78 57 #define SAA7146_DEBI_CONFIG 0x7c 58 #define SAA7146_DEBI_COMMAND 0x80 59 #define SAA7146_DEBI_PAGE 0x84 60 #define SAA7146_DEBI_AD 0x88 61 #define SAA7146_I2C_TRANSFER 0x8c 62 #define SAA7146_I2C_STATUS 0x90 63 #define SAA7146_BASE_A1_IN 0x94 64 #define SAA7146_PROT_A1_IN 0x98 65 #define SAA7146_PAGE_A1_IN 0x9C 66 #define SAA7146_BASE_A1_OUT 0xa0 67 #define SAA7146_PROT_A1_OUT 0xa4 68 #define SAA7146_PAGE_A1_OUT 0xa8 69 #define SAA7146_BASE_A2_IN 0xac 70 #define SAA7146_PROT_A2_IN 0xb0 71 #define SAA7146_PAGE_A2_IN 0xb4 72 #define SAA7146_BASE_A2_OUT 0xb8 73 #define SAA7146_PROT_A2_OUT 0xbc 74 #define SAA7146_PAGE_A2_OUT 0xc0 75 #define SAA7146_RPS_PAGE0 0xc4 76 #define SAA7146_RPS_PAGE1 0xc8 77 #define SAA7146_RPS_THRESH0 0xcc 78 #define SAA7146_RPS_THRESH1 0xd0 79 #define SAA7146_RPS_TOV0 0xd4 80 #define SAA7146_RPS_TOV1 0xd8 81 #define SAA7146_IER 0xdc 82 #define SAA7146_GPIO_CTRL 0xe0 83 #define SAA7146_EC1SSR 0xe4 84 #define SAA7146_EC2SSR 0xe8 85 #define SAA7146_ECT1R 0xec 86 #define SAA7146_ECT2R 0xf0 87 #define SAA7146_ACON1 0xf4 88 #define SAA7146_ACON2 0xf8 89 #define SAA7146_MC1 0xfc 90 #define SAA7146_MC2 0x100 91 #define SAA7146_RPS_ADDR0 0x104 92 #define SAA7146_RPS_ADDR1 0x108 93 #define SAA7146_ISR 0x10c 94 #define SAA7146_PSR 0x110 95 #define SAA7146_SSR 0x114 96 #define SAA7146_EC1R 0x118 97 #define SAA7146_EC2R 0x11c 98 #define SAA7146_VDP1 0x120 99 #define SAA7146_VDP2 0x124 100 #define SAA7146_VDP3 0x128 101 #define SAA7146_ADP1 0x12c 102 #define SAA7146_ADP2 0x130 103 #define SAA7146_ADP3 0x134 104 #define SAA7146_ADP4 0x138 105 #define SAA7146_DDP 0x13c 106 #define SAA7146_LEVEL_REP 0x140 107 #define SAA7146_FB_BUFFER1 0x144 108 #define SAA7146_FB_BUFFER2 0x148 109 #define SAA7146_A_TIME_SLOT1 0x180 110 #define SAA7146_A_TIME_SLOT2 0x1C0 111 112 /* bitfield defines */ 113 #define MASK_31 0x80000000 114 #define MASK_30 0x40000000 115 #define MASK_29 0x20000000 116 #define MASK_28 0x10000000 117 #define MASK_27 0x08000000 118 #define MASK_26 0x04000000 119 #define MASK_25 0x02000000 120 #define MASK_24 0x01000000 121 #define MASK_23 0x00800000 122 #define MASK_22 0x00400000 123 #define MASK_21 0x00200000 124 #define MASK_20 0x00100000 125 #define MASK_19 0x00080000 126 #define MASK_18 0x00040000 127 #define MASK_17 0x00020000 128 #define MASK_16 0x00010000 129 #define MASK_15 0x00008000 130 #define MASK_14 0x00004000 131 #define MASK_13 0x00002000 132 #define MASK_12 0x00001000 133 #define MASK_11 0x00000800 134 #define MASK_10 0x00000400 135 #define MASK_09 0x00000200 136 #define MASK_08 0x00000100 137 #define MASK_07 0x00000080 138 #define MASK_06 0x00000040 139 #define MASK_05 0x00000020 140 #define MASK_04 0x00000010 141 #define MASK_03 0x00000008 142 #define MASK_02 0x00000004 143 #define MASK_01 0x00000002 144 #define MASK_00 0x00000001 145 #define MASK_B0 0x000000ff 146 #define MASK_B1 0x0000ff00 147 #define MASK_B2 0x00ff0000 148 #define MASK_B3 0xff000000 149 #define MASK_W0 0x0000ffff 150 #define MASK_W1 0xffff0000 151 #define MASK_PA 0xfffffffc 152 #define MASK_PR 0xfffffffe 153 #define MASK_ER 0xffffffff 154 #define MASK_NONE 0x00000000 155 156 #define SAA7146_PAGE_MAP_EN MASK_11 157 /* main control register 1 */ 158 #define SAA7146_MC1_MRST_N MASK_15 159 #define SAA7146_MC1_ERPS1 MASK_13 160 #define SAA7146_MC1_ERPS0 MASK_12 161 #define SAA7146_MC1_EDP MASK_11 162 #define SAA7146_MC1_EVP MASK_10 163 #define SAA7146_MC1_EAP MASK_09 164 #define SAA7146_MC1_EI2C MASK_08 165 #define SAA7146_MC1_TR_E_DEBI MASK_07 166 #define SAA7146_MC1_TR_E_1 MASK_06 167 #define SAA7146_MC1_TR_E_2 MASK_05 168 #define SAA7146_MC1_TR_E_3 MASK_04 169 #define SAA7146_MC1_TR_E_A2_OUT MASK_03 170 #define SAA7146_MC1_TR_E_A2_IN MASK_02 171 #define SAA7146_MC1_TR_E_A1_OUT MASK_01 172 #define SAA7146_MC1_TR_E_A1_IN MASK_00 173 /* main control register 2 */ 174 #define SAA7146_MC2_RPS_SIG4 MASK_15 175 #define SAA7146_MC2_RPS_SIG3 MASK_14 176 #define SAA7146_MC2_RPS_SIG2 MASK_13 177 #define SAA7146_MC2_RPS_SIG1 MASK_12 178 #define SAA7146_MC2_RPS_SIG0 MASK_11 179 #define SAA7146_MC2_UPLD_D1_B MASK_10 180 #define SAA7146_MC2_UPLD_D1_A MASK_09 181 #define SAA7146_MC2_UPLD_BRS MASK_08 182 #define SAA7146_MC2_UPLD_HPS_H MASK_06 183 #define SAA7146_MC2_UPLD_HPS_V MASK_05 184 #define SAA7146_MC2_UPLD_DMA3 MASK_04 185 #define SAA7146_MC2_UPLD_DMA2 MASK_03 186 #define SAA7146_MC2_UPLD_DMA1 MASK_02 187 #define SAA7146_MC2_UPLD_DEBI MASK_01 188 #define SAA7146_MC2_UPLD_I2C MASK_00 189 /* Primary Status Register and Interrupt Enable/Status Registers */ 190 #define SAA7146_PSR_PPEF MASK_31 191 #define SAA7146_PSR_PABO MASK_30 192 #define SAA7146_PSR_PPED MASK_29 193 #define SAA7146_PSR_RPS_I1 MASK_28 194 #define SAA7146_PSR_RPS_I0 MASK_27 195 #define SAA7146_PSR_RPS_LATE1 MASK_26 196 #define SAA7146_PSR_RPS_LATE0 MASK_25 197 #define SAA7146_PSR_RPS_E1 MASK_24 198 #define SAA7146_PSR_RPS_E0 MASK_23 199 #define SAA7146_PSR_RPS_TO1 MASK_22 200 #define SAA7146_PSR_RPS_TO0 MASK_21 201 #define SAA7146_PSR_UPLD MASK_20 202 #define SAA7146_PSR_DEBI_S MASK_19 203 #define SAA7146_PSR_DEBI_E MASK_18 204 #define SAA7146_PSR_I2C_S MASK_17 205 #define SAA7146_PSR_I2C_E MASK_16 206 #define SAA7146_PSR_A2_IN MASK_15 207 #define SAA7146_PSR_A2_OUT MASK_14 208 #define SAA7146_PSR_A1_IN MASK_13 209 #define SAA7146_PSR_A1_OUT MASK_12 210 #define SAA7146_PSR_AFOU MASK_11 211 #define SAA7146_PSR_V_PE MASK_10 212 #define SAA7146_PSR_VFOU MASK_09 213 #define SAA7146_PSR_FIDA MASK_08 214 #define SAA7146_PSR_FIDB MASK_07 215 #define SAA7146_PSR_PIN3 MASK_06 216 #define SAA7146_PSR_PIN2 MASK_05 217 #define SAA7146_PSR_PIN1 MASK_04 218 #define SAA7146_PSR_PIN0 MASK_03 219 #define SAA7146_PSR_ECS MASK_02 220 #define SAA7146_PSR_EC3S MASK_01 221 #define SAA7146_PSR_EC0S MASK_00 222 /* Secondary Status Register */ 223 #define SAA7146_SSR_PRQ MASK_31 224 #define SAA7146_SSR_PMA MASK_30 225 #define SAA7146_SSR_RPS_RE1 MASK_29 226 #define SAA7146_SSR_RPS_PE1 MASK_28 227 #define SAA7146_SSR_RPS_A1 MASK_27 228 #define SAA7146_SSR_RPS_RE0 MASK_26 229 #define SAA7146_SSR_RPS_PE0 MASK_25 230 #define SAA7146_SSR_RPS_A0 MASK_24 231 #define SAA7146_SSR_DEBI_TO MASK_23 232 #define SAA7146_SSR_DEBI_EF MASK_22 233 #define SAA7146_SSR_I2C_EA MASK_21 234 #define SAA7146_SSR_I2C_EW MASK_20 235 #define SAA7146_SSR_I2C_ER MASK_19 236 #define SAA7146_SSR_I2C_EL MASK_18 237 #define SAA7146_SSR_I2C_EF MASK_17 238 #define SAA7146_SSR_V3P MASK_16 239 #define SAA7146_SSR_V2P MASK_15 240 #define SAA7146_SSR_V1P MASK_14 241 #define SAA7146_SSR_VF3 MASK_13 242 #define SAA7146_SSR_VF2 MASK_12 243 #define SAA7146_SSR_VF1 MASK_11 244 #define SAA7146_SSR_AF2_IN MASK_10 245 #define SAA7146_SSR_AF2_OUT MASK_09 246 #define SAA7146_SSR_AF1_IN MASK_08 247 #define SAA7146_SSR_AF1_OUT MASK_07 248 #define SAA7146_SSR_VGT MASK_05 249 #define SAA7146_SSR_LNQG MASK_04 250 #define SAA7146_SSR_EC5S MASK_03 251 #define SAA7146_SSR_EC4S MASK_02 252 #define SAA7146_SSR_EC2S MASK_01 253 #define SAA7146_SSR_EC1S MASK_00 254 /* I2C status register */ 255 #define SAA7146_I2C_ABORT MASK_07 256 #define SAA7146_I2C_SPERR MASK_06 257 #define SAA7146_I2C_APERR MASK_05 258 #define SAA7146_I2C_DTERR MASK_04 259 #define SAA7146_I2C_DRERR MASK_03 260 #define SAA7146_I2C_AL MASK_02 261 #define SAA7146_I2C_ERR MASK_01 262 #define SAA7146_I2C_BUSY MASK_00 263 /* output formats */ 264 #define SAA7146_YUV422 0 265 #define SAA7146_RGB16 0 266 #define SAA7146_YUV444 1 267 #define SAA7146_RGB24 1 268 #define SAA7146_ARGB32 2 269 #define SAA7146_YUV411 3 270 #define SAA7146_ARGB15 3 271 #define SAA7146_YUV2 4 272 #define SAA7146_RGAB15 4 273 #define SAA7146_Y8 6 274 #define SAA7146_YUV8 7 275 #define SAA7146_RGB8 7 276 #define SAA7146_YUV444p 8 277 #define SAA7146_YUV422p 9 278 #define SAA7146_YUV420p 10 279 #define SAA7146_YUV1620 11 280 #define SAA7146_Y1 13 281 #define SAA7146_Y2 14 282 #define SAA7146_YUV1 15 283 #endif 284