1 /* Copyright 2008-2012 Broadcom Corporation 2 * 3 * Unless you and Broadcom execute a separate written software license 4 * agreement governing use of this software, this software is licensed to you 5 * under the terms of the GNU General Public License version 2, available 6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 7 * 8 * Notwithstanding the above, under no circumstances may you combine this 9 * software in any way with any other Broadcom software provided under a 10 * license other than the GPL, without Broadcom's express prior written 11 * consent. 12 * 13 * Written by Yaniv Rosner 14 * 15 */ 16 17 #ifndef BNX2X_LINK_H 18 #define BNX2X_LINK_H 19 20 21 22 /***********************************************************/ 23 /* Defines */ 24 /***********************************************************/ 25 #define DEFAULT_PHY_DEV_ADDR 3 26 #define E2_DEFAULT_PHY_DEV_ADDR 5 27 28 29 30 #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO 31 #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX 32 #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX 33 #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH 34 #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE 35 36 #define NET_SERDES_IF_XFI 1 37 #define NET_SERDES_IF_SFI 2 38 #define NET_SERDES_IF_KR 3 39 #define NET_SERDES_IF_DXGXS 4 40 41 #define SPEED_AUTO_NEG 0 42 #define SPEED_20000 20000 43 44 #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14 45 #define SFP_EEPROM_VENDOR_NAME_SIZE 16 46 #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25 47 #define SFP_EEPROM_VENDOR_OUI_SIZE 3 48 #define SFP_EEPROM_PART_NO_ADDR 0x28 49 #define SFP_EEPROM_PART_NO_SIZE 16 50 #define SFP_EEPROM_REVISION_ADDR 0x38 51 #define SFP_EEPROM_REVISION_SIZE 4 52 #define SFP_EEPROM_SERIAL_ADDR 0x44 53 #define SFP_EEPROM_SERIAL_SIZE 16 54 #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ 55 #define SFP_EEPROM_DATE_SIZE 6 56 #define PWR_FLT_ERR_MSG_LEN 250 57 58 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \ 59 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) 60 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \ 61 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ 62 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) 63 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \ 64 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) 65 66 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ 67 #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) 68 /* Single Media board contains single external phy */ 69 #define SINGLE_MEDIA(params) (params->num_phys == 2) 70 /* Dual Media board contains two external phy with different media */ 71 #define DUAL_MEDIA(params) (params->num_phys == 3) 72 73 #define FW_PARAM_PHY_ADDR_MASK 0x000000FF 74 #define FW_PARAM_PHY_TYPE_MASK 0x0000FF00 75 #define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000 76 #define FW_PARAM_MDIO_CTRL_OFFSET 16 77 #define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ 78 FW_PARAM_PHY_ADDR_MASK) 79 #define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ 80 FW_PARAM_PHY_TYPE_MASK) 81 #define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ 82 FW_PARAM_MDIO_CTRL_MASK) >> \ 83 FW_PARAM_MDIO_CTRL_OFFSET) 84 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ 85 (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET) 86 87 88 #define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170 89 #define PFC_BRB_FULL_LB_XON_THRESHOLD 250 90 91 #define MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) 92 93 #define BMAC_CONTROL_RX_ENABLE 2 94 /***********************************************************/ 95 /* Structs */ 96 /***********************************************************/ 97 #define INT_PHY 0 98 #define EXT_PHY1 1 99 #define EXT_PHY2 2 100 #define MAX_PHYS 3 101 102 /* Same configuration is shared between the XGXS and the first external phy */ 103 #define LINK_CONFIG_SIZE (MAX_PHYS - 1) 104 #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \ 105 0 : (_phy_idx - 1)) 106 /***********************************************************/ 107 /* bnx2x_phy struct */ 108 /* Defines the required arguments and function per phy */ 109 /***********************************************************/ 110 struct link_vars; 111 struct link_params; 112 struct bnx2x_phy; 113 114 typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params, 115 struct link_vars *vars); 116 typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params, 117 struct link_vars *vars); 118 typedef void (*link_reset_t)(struct bnx2x_phy *phy, 119 struct link_params *params); 120 typedef void (*config_loopback_t)(struct bnx2x_phy *phy, 121 struct link_params *params); 122 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len); 123 typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params); 124 typedef void (*set_link_led_t)(struct bnx2x_phy *phy, 125 struct link_params *params, u8 mode); 126 typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy, 127 struct link_params *params, u32 action); 128 129 struct bnx2x_phy { 130 u32 type; 131 132 /* Loaded during init */ 133 u8 addr; 134 u8 def_md_devad; 135 u16 flags; 136 /* Require HW lock */ 137 #define FLAGS_HW_LOCK_REQUIRED (1<<0) 138 /* No Over-Current detection */ 139 #define FLAGS_NOC (1<<1) 140 /* Fan failure detection required */ 141 #define FLAGS_FAN_FAILURE_DET_REQ (1<<2) 142 /* Initialize first the XGXS and only then the phy itself */ 143 #define FLAGS_INIT_XGXS_FIRST (1<<3) 144 #define FLAGS_WC_DUAL_MODE (1<<4) 145 #define FLAGS_4_PORT_MODE (1<<5) 146 #define FLAGS_REARM_LATCH_SIGNAL (1<<6) 147 #define FLAGS_SFP_NOT_APPROVED (1<<7) 148 #define FLAGS_MDC_MDIO_WA (1<<8) 149 #define FLAGS_DUMMY_READ (1<<9) 150 #define FLAGS_MDC_MDIO_WA_B0 (1<<10) 151 #define FLAGS_TX_ERROR_CHECK (1<<12) 152 153 /* preemphasis values for the rx side */ 154 u16 rx_preemphasis[4]; 155 156 /* preemphasis values for the tx side */ 157 u16 tx_preemphasis[4]; 158 159 /* EMAC address for access MDIO */ 160 u32 mdio_ctrl; 161 162 u32 supported; 163 164 u32 media_type; 165 #define ETH_PHY_UNSPECIFIED 0x0 166 #define ETH_PHY_SFP_FIBER 0x1 167 #define ETH_PHY_XFP_FIBER 0x2 168 #define ETH_PHY_DA_TWINAX 0x3 169 #define ETH_PHY_BASE_T 0x4 170 #define ETH_PHY_KR 0xf0 171 #define ETH_PHY_CX4 0xf1 172 #define ETH_PHY_NOT_PRESENT 0xff 173 174 /* The address in which version is located*/ 175 u32 ver_addr; 176 177 u16 req_flow_ctrl; 178 179 u16 req_line_speed; 180 181 u32 speed_cap_mask; 182 183 u16 req_duplex; 184 u16 rsrv; 185 /* Called per phy/port init, and it configures LASI, speed, autoneg, 186 duplex, flow control negotiation, etc. */ 187 config_init_t config_init; 188 189 /* Called due to interrupt. It determines the link, speed */ 190 read_status_t read_status; 191 192 /* Called when driver is unloading. Should reset the phy */ 193 link_reset_t link_reset; 194 195 /* Set the loopback configuration for the phy */ 196 config_loopback_t config_loopback; 197 198 /* Format the given raw number into str up to len */ 199 format_fw_ver_t format_fw_ver; 200 201 /* Reset the phy (both ports) */ 202 hw_reset_t hw_reset; 203 204 /* Set link led mode (on/off/oper)*/ 205 set_link_led_t set_link_led; 206 207 /* PHY Specific tasks */ 208 phy_specific_func_t phy_specific_func; 209 #define DISABLE_TX 1 210 #define ENABLE_TX 2 211 }; 212 213 /* Inputs parameters to the CLC */ 214 struct link_params { 215 216 u8 port; 217 218 /* Default / User Configuration */ 219 u8 loopback_mode; 220 #define LOOPBACK_NONE 0 221 #define LOOPBACK_EMAC 1 222 #define LOOPBACK_BMAC 2 223 #define LOOPBACK_XGXS 3 224 #define LOOPBACK_EXT_PHY 4 225 #define LOOPBACK_EXT 5 226 #define LOOPBACK_UMAC 6 227 #define LOOPBACK_XMAC 7 228 229 /* Device parameters */ 230 u8 mac_addr[6]; 231 232 u16 req_duplex[LINK_CONFIG_SIZE]; 233 u16 req_flow_ctrl[LINK_CONFIG_SIZE]; 234 235 u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ 236 237 /* shmem parameters */ 238 u32 shmem_base; 239 u32 shmem2_base; 240 u32 speed_cap_mask[LINK_CONFIG_SIZE]; 241 u32 switch_cfg; 242 #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH 243 #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH 244 #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT 245 246 u32 lane_config; 247 248 /* Phy register parameter */ 249 u32 chip_id; 250 251 /* features */ 252 u32 feature_config_flags; 253 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) 254 #define FEATURE_CONFIG_PFC_ENABLED (1<<1) 255 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) 256 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) 257 #define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9) 258 #define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10) 259 /* Will be populated during common init */ 260 struct bnx2x_phy phy[MAX_PHYS]; 261 262 /* Will be populated during common init */ 263 u8 num_phys; 264 265 u8 rsrv; 266 u16 hw_led_mode; /* part of the hw_config read from the shmem */ 267 u32 multi_phy_config; 268 269 /* Device pointer passed to all callback functions */ 270 struct bnx2x *bp; 271 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when 272 req_flow_ctrl is set to AUTO */ 273 }; 274 275 /* Output parameters */ 276 struct link_vars { 277 u8 phy_flags; 278 #define PHY_XGXS_FLAG (1<<0) 279 #define PHY_SGMII_FLAG (1<<1) 280 #define PHY_PHYSICAL_LINK_FLAG (1<<2) 281 #define PHY_HALF_OPEN_CONN_FLAG (1<<3) 282 #define PHY_OVER_CURRENT_FLAG (1<<4) 283 284 u8 mac_type; 285 #define MAC_TYPE_NONE 0 286 #define MAC_TYPE_EMAC 1 287 #define MAC_TYPE_BMAC 2 288 #define MAC_TYPE_UMAC 3 289 #define MAC_TYPE_XMAC 4 290 291 u8 phy_link_up; /* internal phy link indication */ 292 u8 link_up; 293 294 u16 line_speed; 295 u16 duplex; 296 297 u16 flow_ctrl; 298 u16 ieee_fc; 299 300 /* The same definitions as the shmem parameter */ 301 u32 link_status; 302 u8 fault_detected; 303 u8 rsrv1; 304 u16 periodic_flags; 305 #define PERIODIC_FLAGS_LINK_EVENT 0x0001 306 307 u32 aeu_int_mask; 308 u8 rx_tx_asic_rst; 309 u8 turn_to_run_wc_rt; 310 u16 rsrv2; 311 }; 312 313 /***********************************************************/ 314 /* Functions */ 315 /***********************************************************/ 316 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars); 317 318 /* Reset the link. Should be called when driver or interface goes down 319 Before calling phy firmware upgrade, the reset_ext_phy should be set 320 to 0 */ 321 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 322 u8 reset_ext_phy); 323 324 /* bnx2x_link_update should be called upon link interrupt */ 325 int bnx2x_link_update(struct link_params *params, struct link_vars *vars); 326 327 /* use the following phy functions to read/write from external_phy 328 In order to use it to read/write internal phy registers, use 329 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as 330 the register */ 331 int bnx2x_phy_read(struct link_params *params, u8 phy_addr, 332 u8 devad, u16 reg, u16 *ret_val); 333 334 int bnx2x_phy_write(struct link_params *params, u8 phy_addr, 335 u8 devad, u16 reg, u16 val); 336 337 /* Reads the link_status from the shmem, 338 and update the link vars accordingly */ 339 void bnx2x_link_status_update(struct link_params *input, 340 struct link_vars *output); 341 /* returns string representing the fw_version of the external phy */ 342 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, 343 u16 len); 344 345 /* Set/Unset the led 346 Basically, the CLC takes care of the led for the link, but in case one needs 347 to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to 348 blink the led, and LED_MODE_OFF to set the led off.*/ 349 int bnx2x_set_led(struct link_params *params, 350 struct link_vars *vars, u8 mode, u32 speed); 351 #define LED_MODE_OFF 0 352 #define LED_MODE_ON 1 353 #define LED_MODE_OPER 2 354 #define LED_MODE_FRONT_PANEL_OFF 3 355 356 /* bnx2x_handle_module_detect_int should be called upon module detection 357 interrupt */ 358 void bnx2x_handle_module_detect_int(struct link_params *params); 359 360 /* Get the actual link status. In case it returns 0, link is up, 361 otherwise link is down*/ 362 int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 363 u8 is_serdes); 364 365 /* One-time initialization for external phy after power up */ 366 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], 367 u32 shmem2_base_path[], u32 chip_id); 368 369 /* Reset the external PHY using GPIO */ 370 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port); 371 372 /* Reset the external of SFX7101 */ 373 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy); 374 375 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ 376 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 377 struct link_params *params, u16 addr, 378 u8 byte_cnt, u8 *o_buf); 379 380 void bnx2x_hw_reset_phy(struct link_params *params); 381 382 /* Checks if HW lock is required for this phy/board type */ 383 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, 384 u32 shmem2_base); 385 386 /* Check swap bit and adjust PHY order */ 387 u32 bnx2x_phy_selection(struct link_params *params); 388 389 /* Probe the phys on board, and populate them in "params" */ 390 int bnx2x_phy_probe(struct link_params *params); 391 392 /* Checks if fan failure detection is required on one of the phys on board */ 393 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base, 394 u32 shmem2_base, u8 port); 395 396 397 398 /* DCBX structs */ 399 400 /* Number of maximum COS per chip */ 401 #define DCBX_E2E3_MAX_NUM_COS (2) 402 #define DCBX_E3B0_MAX_NUM_COS_PORT0 (6) 403 #define DCBX_E3B0_MAX_NUM_COS_PORT1 (3) 404 #define DCBX_E3B0_MAX_NUM_COS ( \ 405 MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \ 406 DCBX_E3B0_MAX_NUM_COS_PORT1)) 407 408 #define DCBX_MAX_NUM_COS ( \ 409 MAXVAL(DCBX_E3B0_MAX_NUM_COS, \ 410 DCBX_E2E3_MAX_NUM_COS)) 411 412 /* PFC port configuration params */ 413 struct bnx2x_nig_brb_pfc_port_params { 414 /* NIG */ 415 u32 pause_enable; 416 u32 llfc_out_en; 417 u32 llfc_enable; 418 u32 pkt_priority_to_cos; 419 u8 num_of_rx_cos_priority_mask; 420 u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS]; 421 u32 llfc_high_priority_classes; 422 u32 llfc_low_priority_classes; 423 /* BRB */ 424 u32 cos0_pauseable; 425 u32 cos1_pauseable; 426 }; 427 428 429 /* ETS port configuration params */ 430 struct bnx2x_ets_bw_params { 431 u8 bw; 432 }; 433 434 struct bnx2x_ets_sp_params { 435 /** 436 * valid values are 0 - 5. 0 is highest strict priority. 437 * There can't be two COS's with the same pri. 438 */ 439 u8 pri; 440 }; 441 442 enum bnx2x_cos_state { 443 bnx2x_cos_state_strict = 0, 444 bnx2x_cos_state_bw = 1, 445 }; 446 447 struct bnx2x_ets_cos_params { 448 enum bnx2x_cos_state state ; 449 union { 450 struct bnx2x_ets_bw_params bw_params; 451 struct bnx2x_ets_sp_params sp_params; 452 } params; 453 }; 454 455 struct bnx2x_ets_params { 456 u8 num_of_cos; /* Number of valid COS entries*/ 457 struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS]; 458 }; 459 460 /** 461 * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB 462 * when link is already up 463 */ 464 int bnx2x_update_pfc(struct link_params *params, 465 struct link_vars *vars, 466 struct bnx2x_nig_brb_pfc_port_params *pfc_params); 467 468 469 /* Used to configure the ETS to disable */ 470 int bnx2x_ets_disabled(struct link_params *params, 471 struct link_vars *vars); 472 473 /* Used to configure the ETS to BW limited */ 474 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, 475 const u32 cos1_bw); 476 477 /* Used to configure the ETS to strict */ 478 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos); 479 480 481 /* Configure the COS to ETS according to BW and SP settings.*/ 482 int bnx2x_ets_e3b0_config(const struct link_params *params, 483 const struct link_vars *vars, 484 struct bnx2x_ets_params *ets_params); 485 /* Read pfc statistic*/ 486 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, 487 u32 pfc_frames_sent[2], 488 u32 pfc_frames_received[2]); 489 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, 490 u32 chip_id, u32 shmem_base, u32 shmem2_base, 491 u8 port); 492 493 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 494 struct link_params *params); 495 496 void bnx2x_period_func(struct link_params *params, struct link_vars *vars); 497 498 #endif /* BNX2X_LINK_H */ 499