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1 /*******************************************************************
2  * This file is part of the Emulex Linux Device Driver for         *
3  * Fibre Channel Host Bus Adapters.                                *
4  * Copyright (C) 2004-2011 Emulex.  All rights reserved.           *
5  * EMULEX and SLI are trademarks of Emulex.                        *
6  * www.emulex.com                                                  *
7  *                                                                 *
8  * This program is free software; you can redistribute it and/or   *
9  * modify it under the terms of version 2 of the GNU General       *
10  * Public License as published by the Free Software Foundation.    *
11  * This program is distributed in the hope that it will be useful. *
12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
17  * more details, a copy of which can be found in the file COPYING  *
18  * included with this package.                                     *
19  *******************************************************************/
20 
21 #define FDMI_DID        0xfffffaU
22 #define NameServer_DID  0xfffffcU
23 #define SCR_DID         0xfffffdU
24 #define Fabric_DID      0xfffffeU
25 #define Bcast_DID       0xffffffU
26 #define Mask_DID        0xffffffU
27 #define CT_DID_MASK     0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
30 
31 #define PT2PT_LocalID	1
32 #define PT2PT_RemoteID	2
33 
34 #define FF_DEF_EDTOV          2000	/* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV            15	/* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV             2	/* Default RA_TOV (2s) */
37 #define FF_DEF_ARBTOV         1900	/* Default ARB_TOV (1900ms) */
38 
39 #define LPFC_BUF_RING0        64	/* Number of buffers to post to RING
40 					   0 */
41 
42 #define FCELSSIZE             1024	/* maximum ELS transfer size */
43 
44 #define LPFC_FCP_RING            0	/* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING          1	/* ring 1 for other protocols */
46 #define LPFC_ELS_RING            2	/* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING       3
48 
49 #define SLI2_IOCB_CMD_R0_ENTRIES    172	/* SLI-2 FCP command ring entries */
50 #define SLI2_IOCB_RSP_R0_ENTRIES    134	/* SLI-2 FCP response ring entries */
51 #define SLI2_IOCB_CMD_R1_ENTRIES      4	/* SLI-2 extra command ring entries */
52 #define SLI2_IOCB_RSP_R1_ENTRIES      4	/* SLI-2 extra response ring entries */
53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36	/* SLI-2 extra FCP cmd ring entries */
54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52	/* SLI-2 extra FCP rsp ring entries */
55 #define SLI2_IOCB_CMD_R2_ENTRIES     20	/* SLI-2 ELS command ring entries */
56 #define SLI2_IOCB_RSP_R2_ENTRIES     20	/* SLI-2 ELS response ring entries */
57 #define SLI2_IOCB_CMD_R3_ENTRIES      0
58 #define SLI2_IOCB_RSP_R3_ENTRIES      0
59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61 
62 #define SLI2_IOCB_CMD_SIZE	32
63 #define SLI2_IOCB_RSP_SIZE	32
64 #define SLI3_IOCB_CMD_SIZE	128
65 #define SLI3_IOCB_RSP_SIZE	64
66 
67 #define LPFC_UNREG_ALL_RPIS_VPORT	0xffff
68 #define LPFC_UNREG_ALL_DFLT_RPIS	0xffffffff
69 
70 /* vendor ID used in SCSI netlink calls */
71 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
72 
73 #define FW_REV_STR_SIZE	32
74 /* Common Transport structures and definitions */
75 
76 union CtRevisionId {
77 	/* Structure is in Big Endian format */
78 	struct {
79 		uint32_t Revision:8;
80 		uint32_t InId:24;
81 	} bits;
82 	uint32_t word;
83 };
84 
85 union CtCommandResponse {
86 	/* Structure is in Big Endian format */
87 	struct {
88 		uint32_t CmdRsp:16;
89 		uint32_t Size:16;
90 	} bits;
91 	uint32_t word;
92 };
93 
94 #define FC4_FEATURE_INIT 0x2
95 #define FC4_FEATURE_TARGET 0x1
96 
97 struct lpfc_sli_ct_request {
98 	/* Structure is in Big Endian format */
99 	union CtRevisionId RevisionId;
100 	uint8_t FsType;
101 	uint8_t FsSubType;
102 	uint8_t Options;
103 	uint8_t Rsrvd1;
104 	union CtCommandResponse CommandResponse;
105 	uint8_t Rsrvd2;
106 	uint8_t ReasonCode;
107 	uint8_t Explanation;
108 	uint8_t VendorUnique;
109 
110 	union {
111 		uint32_t PortID;
112 		struct gid {
113 			uint8_t PortType;	/* for GID_PT requests */
114 			uint8_t DomainScope;
115 			uint8_t AreaScope;
116 			uint8_t Fc4Type;	/* for GID_FT requests */
117 		} gid;
118 		struct rft {
119 			uint32_t PortId;	/* For RFT_ID requests */
120 
121 #ifdef __BIG_ENDIAN_BITFIELD
122 			uint32_t rsvd0:16;
123 			uint32_t rsvd1:7;
124 			uint32_t fcpReg:1;	/* Type 8 */
125 			uint32_t rsvd2:2;
126 			uint32_t ipReg:1;	/* Type 5 */
127 			uint32_t rsvd3:5;
128 #else	/*  __LITTLE_ENDIAN_BITFIELD */
129 			uint32_t rsvd0:16;
130 			uint32_t fcpReg:1;	/* Type 8 */
131 			uint32_t rsvd1:7;
132 			uint32_t rsvd3:5;
133 			uint32_t ipReg:1;	/* Type 5 */
134 			uint32_t rsvd2:2;
135 #endif
136 
137 			uint32_t rsvd[7];
138 		} rft;
139 		struct rnn {
140 			uint32_t PortId;	/* For RNN_ID requests */
141 			uint8_t wwnn[8];
142 		} rnn;
143 		struct rsnn {	/* For RSNN_ID requests */
144 			uint8_t wwnn[8];
145 			uint8_t len;
146 			uint8_t symbname[255];
147 		} rsnn;
148 		struct da_id { /* For DA_ID requests */
149 			uint32_t port_id;
150 		} da_id;
151 		struct rspn {	/* For RSPN_ID requests */
152 			uint32_t PortId;
153 			uint8_t len;
154 			uint8_t symbname[255];
155 		} rspn;
156 		struct gff {
157 			uint32_t PortId;
158 		} gff;
159 		struct gff_acc {
160 			uint8_t fbits[128];
161 		} gff_acc;
162 #define FCP_TYPE_FEATURE_OFFSET 7
163 		struct rff {
164 			uint32_t PortId;
165 			uint8_t reserved[2];
166 			uint8_t fbits;
167 			uint8_t type_code;     /* type=8 for FCP */
168 		} rff;
169 	} un;
170 };
171 
172 #define  SLI_CT_REVISION        1
173 #define  GID_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
174 			   sizeof(struct gid))
175 #define  GFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
176 			   sizeof(struct gff))
177 #define  RFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
178 			   sizeof(struct rft))
179 #define  RFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
180 			   sizeof(struct rff))
181 #define  RNN_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
182 			   sizeof(struct rnn))
183 #define  RSNN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
184 			   sizeof(struct rsnn))
185 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
186 			  sizeof(struct da_id))
187 #define  RSPN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
188 			   sizeof(struct rspn))
189 
190 /*
191  * FsType Definitions
192  */
193 
194 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
195 #define  SLI_CT_TIME_SERVICE              0xFB
196 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
197 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
198 
199 /*
200  * Directory Service Subtypes
201  */
202 
203 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
204 
205 /*
206  * Response Codes
207  */
208 
209 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
210 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
211 
212 /*
213  * Reason Codes
214  */
215 
216 #define  SLI_CT_NO_ADDITIONAL_EXPL	  0x0
217 #define  SLI_CT_INVALID_COMMAND           0x01
218 #define  SLI_CT_INVALID_VERSION           0x02
219 #define  SLI_CT_LOGICAL_ERROR             0x03
220 #define  SLI_CT_INVALID_IU_SIZE           0x04
221 #define  SLI_CT_LOGICAL_BUSY              0x05
222 #define  SLI_CT_PROTOCOL_ERROR            0x07
223 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
224 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
225 #define  SLI_CT_HBA_INFO_NOT_REGISTERED	  0x10
226 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
227 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
228 #define  SLI_CT_HBA_ATTR_NOT_PRESENT	  0x13
229 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
230 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
231 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
232 #define  SLI_CT_VENDOR_UNIQUE             0xff
233 
234 /*
235  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
236  */
237 
238 #define  SLI_CT_NO_PORT_ID                0x01
239 #define  SLI_CT_NO_PORT_NAME              0x02
240 #define  SLI_CT_NO_NODE_NAME              0x03
241 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
242 #define  SLI_CT_NO_IP_ADDRESS             0x05
243 #define  SLI_CT_NO_IPA                    0x06
244 #define  SLI_CT_NO_FC4_TYPES              0x07
245 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
246 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
247 #define  SLI_CT_NO_PORT_TYPE              0x0A
248 #define  SLI_CT_ACCESS_DENIED             0x10
249 #define  SLI_CT_INVALID_PORT_ID           0x11
250 #define  SLI_CT_DATABASE_EMPTY            0x12
251 
252 /*
253  * Name Server Command Codes
254  */
255 
256 #define  SLI_CTNS_GA_NXT      0x0100
257 #define  SLI_CTNS_GPN_ID      0x0112
258 #define  SLI_CTNS_GNN_ID      0x0113
259 #define  SLI_CTNS_GCS_ID      0x0114
260 #define  SLI_CTNS_GFT_ID      0x0117
261 #define  SLI_CTNS_GSPN_ID     0x0118
262 #define  SLI_CTNS_GPT_ID      0x011A
263 #define  SLI_CTNS_GFF_ID      0x011F
264 #define  SLI_CTNS_GID_PN      0x0121
265 #define  SLI_CTNS_GID_NN      0x0131
266 #define  SLI_CTNS_GIP_NN      0x0135
267 #define  SLI_CTNS_GIPA_NN     0x0136
268 #define  SLI_CTNS_GSNN_NN     0x0139
269 #define  SLI_CTNS_GNN_IP      0x0153
270 #define  SLI_CTNS_GIPA_IP     0x0156
271 #define  SLI_CTNS_GID_FT      0x0171
272 #define  SLI_CTNS_GID_PT      0x01A1
273 #define  SLI_CTNS_RPN_ID      0x0212
274 #define  SLI_CTNS_RNN_ID      0x0213
275 #define  SLI_CTNS_RCS_ID      0x0214
276 #define  SLI_CTNS_RFT_ID      0x0217
277 #define  SLI_CTNS_RSPN_ID     0x0218
278 #define  SLI_CTNS_RPT_ID      0x021A
279 #define  SLI_CTNS_RFF_ID      0x021F
280 #define  SLI_CTNS_RIP_NN      0x0235
281 #define  SLI_CTNS_RIPA_NN     0x0236
282 #define  SLI_CTNS_RSNN_NN     0x0239
283 #define  SLI_CTNS_DA_ID       0x0300
284 
285 /*
286  * Port Types
287  */
288 
289 #define  SLI_CTPT_N_PORT      0x01
290 #define  SLI_CTPT_NL_PORT     0x02
291 #define  SLI_CTPT_FNL_PORT    0x03
292 #define  SLI_CTPT_IP          0x04
293 #define  SLI_CTPT_FCP         0x08
294 #define  SLI_CTPT_NX_PORT     0x7F
295 #define  SLI_CTPT_F_PORT      0x81
296 #define  SLI_CTPT_FL_PORT     0x82
297 #define  SLI_CTPT_E_PORT      0x84
298 
299 #define SLI_CT_LAST_ENTRY     0x80000000
300 
301 /* Fibre Channel Service Parameter definitions */
302 
303 #define FC_PH_4_0   6		/* FC-PH version 4.0 */
304 #define FC_PH_4_1   7		/* FC-PH version 4.1 */
305 #define FC_PH_4_2   8		/* FC-PH version 4.2 */
306 #define FC_PH_4_3   9		/* FC-PH version 4.3 */
307 
308 #define FC_PH_LOW   8		/* Lowest supported FC-PH version */
309 #define FC_PH_HIGH  9		/* Highest supported FC-PH version */
310 #define FC_PH3   0x20		/* FC-PH-3 version */
311 
312 #define FF_FRAME_SIZE     2048
313 
314 struct lpfc_name {
315 	union {
316 		struct {
317 #ifdef __BIG_ENDIAN_BITFIELD
318 			uint8_t nameType:4;	/* FC Word 0, bit 28:31 */
319 			uint8_t IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit
320 						   8:11 of IEEE ext */
321 #else	/*  __LITTLE_ENDIAN_BITFIELD */
322 			uint8_t IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit
323 						   8:11 of IEEE ext */
324 			uint8_t nameType:4;	/* FC Word 0, bit 28:31 */
325 #endif
326 
327 #define NAME_IEEE           0x1	/* IEEE name - nameType */
328 #define NAME_IEEE_EXT       0x2	/* IEEE extended name */
329 #define NAME_FC_TYPE        0x3	/* FC native name type */
330 #define NAME_IP_TYPE        0x4	/* IP address */
331 #define NAME_CCITT_TYPE     0xC
332 #define NAME_CCITT_GR_TYPE  0xE
333 			uint8_t IEEEextLsb;	/* FC Word 0, bit 16:23, IEEE
334 						   extended Lsb */
335 			uint8_t IEEE[6];	/* FC IEEE address */
336 		} s;
337 		uint8_t wwn[8];
338 	} u;
339 };
340 
341 struct csp {
342 	uint8_t fcphHigh;	/* FC Word 0, byte 0 */
343 	uint8_t fcphLow;
344 	uint8_t bbCreditMsb;
345 	uint8_t bbCreditlsb;	/* FC Word 0, byte 3 */
346 
347 /*
348  * Word 1 Bit 31 in common service parameter is overloaded.
349  * Word 1 Bit 31 in FLOGI request is multiple NPort request
350  * Word 1 Bit 31 in FLOGI response is clean address bit
351  */
352 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
353 /*
354  * Word 1 Bit 30 in common service parameter is overloaded.
355  * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
356  * Word 1 Bit 30 in PLOGI request is random offset
357  */
358 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
359 #ifdef __BIG_ENDIAN_BITFIELD
360 	uint16_t request_multiple_Nport:1;	/* FC Word 1, bit 31 */
361 	uint16_t randomOffset:1;	/* FC Word 1, bit 30 */
362 	uint16_t response_multiple_NPort:1;	/* FC Word 1, bit 29 */
363 	uint16_t fPort:1;	/* FC Word 1, bit 28 */
364 	uint16_t altBbCredit:1;	/* FC Word 1, bit 27 */
365 	uint16_t edtovResolution:1;	/* FC Word 1, bit 26 */
366 	uint16_t multicast:1;	/* FC Word 1, bit 25 */
367 	uint16_t broadcast:1;	/* FC Word 1, bit 24 */
368 
369 	uint16_t huntgroup:1;	/* FC Word 1, bit 23 */
370 	uint16_t simplex:1;	/* FC Word 1, bit 22 */
371 	uint16_t word1Reserved1:3;	/* FC Word 1, bit 21:19 */
372 	uint16_t dhd:1;		/* FC Word 1, bit 18 */
373 	uint16_t contIncSeqCnt:1;	/* FC Word 1, bit 17 */
374 	uint16_t payloadlength:1;	/* FC Word 1, bit 16 */
375 #else	/*  __LITTLE_ENDIAN_BITFIELD */
376 	uint16_t broadcast:1;	/* FC Word 1, bit 24 */
377 	uint16_t multicast:1;	/* FC Word 1, bit 25 */
378 	uint16_t edtovResolution:1;	/* FC Word 1, bit 26 */
379 	uint16_t altBbCredit:1;	/* FC Word 1, bit 27 */
380 	uint16_t fPort:1;	/* FC Word 1, bit 28 */
381 	uint16_t response_multiple_NPort:1;	/* FC Word 1, bit 29 */
382 	uint16_t randomOffset:1;	/* FC Word 1, bit 30 */
383 	uint16_t request_multiple_Nport:1;	/* FC Word 1, bit 31 */
384 
385 	uint16_t payloadlength:1;	/* FC Word 1, bit 16 */
386 	uint16_t contIncSeqCnt:1;	/* FC Word 1, bit 17 */
387 	uint16_t dhd:1;		/* FC Word 1, bit 18 */
388 	uint16_t word1Reserved1:3;	/* FC Word 1, bit 21:19 */
389 	uint16_t simplex:1;	/* FC Word 1, bit 22 */
390 	uint16_t huntgroup:1;	/* FC Word 1, bit 23 */
391 #endif
392 
393 	uint8_t bbRcvSizeMsb;	/* Upper nibble is reserved */
394 	uint8_t bbRcvSizeLsb;	/* FC Word 1, byte 3 */
395 	union {
396 		struct {
397 			uint8_t word2Reserved1;	/* FC Word 2 byte 0 */
398 
399 			uint8_t totalConcurrSeq;	/* FC Word 2 byte 1 */
400 			uint8_t roByCategoryMsb;	/* FC Word 2 byte 2 */
401 
402 			uint8_t roByCategoryLsb;	/* FC Word 2 byte 3 */
403 		} nPort;
404 		uint32_t r_a_tov;	/* R_A_TOV must be in B.E. format */
405 	} w2;
406 
407 	uint32_t e_d_tov;	/* E_D_TOV must be in B.E. format */
408 };
409 
410 struct class_parms {
411 #ifdef __BIG_ENDIAN_BITFIELD
412 	uint8_t classValid:1;	/* FC Word 0, bit 31 */
413 	uint8_t intermix:1;	/* FC Word 0, bit 30 */
414 	uint8_t stackedXparent:1;	/* FC Word 0, bit 29 */
415 	uint8_t stackedLockDown:1;	/* FC Word 0, bit 28 */
416 	uint8_t seqDelivery:1;	/* FC Word 0, bit 27 */
417 	uint8_t word0Reserved1:3;	/* FC Word 0, bit 24:26 */
418 #else	/*  __LITTLE_ENDIAN_BITFIELD */
419 	uint8_t word0Reserved1:3;	/* FC Word 0, bit 24:26 */
420 	uint8_t seqDelivery:1;	/* FC Word 0, bit 27 */
421 	uint8_t stackedLockDown:1;	/* FC Word 0, bit 28 */
422 	uint8_t stackedXparent:1;	/* FC Word 0, bit 29 */
423 	uint8_t intermix:1;	/* FC Word 0, bit 30 */
424 	uint8_t classValid:1;	/* FC Word 0, bit 31 */
425 
426 #endif
427 
428 	uint8_t word0Reserved2;	/* FC Word 0, bit 16:23 */
429 
430 #ifdef __BIG_ENDIAN_BITFIELD
431 	uint8_t iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
432 	uint8_t iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
433 	uint8_t iCtlAck0capable:1;	/* FC Word 0, bit 11 */
434 	uint8_t iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
435 	uint8_t word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
436 #else	/*  __LITTLE_ENDIAN_BITFIELD */
437 	uint8_t word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
438 	uint8_t iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
439 	uint8_t iCtlAck0capable:1;	/* FC Word 0, bit 11 */
440 	uint8_t iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
441 	uint8_t iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
442 #endif
443 
444 	uint8_t word0Reserved4;	/* FC Word 0, bit  0: 7 */
445 
446 #ifdef __BIG_ENDIAN_BITFIELD
447 	uint8_t rCtlAck0capable:1;	/* FC Word 1, bit 31 */
448 	uint8_t rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
449 	uint8_t rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
450 	uint8_t rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
451 	uint8_t word1Reserved1:1;	/* FC Word 1, bit 26 */
452 	uint8_t rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
453 #else	/*  __LITTLE_ENDIAN_BITFIELD */
454 	uint8_t rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
455 	uint8_t word1Reserved1:1;	/* FC Word 1, bit 26 */
456 	uint8_t rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
457 	uint8_t rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
458 	uint8_t rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
459 	uint8_t rCtlAck0capable:1;	/* FC Word 1, bit 31 */
460 #endif
461 
462 	uint8_t word1Reserved2;	/* FC Word 1, bit 16:23 */
463 	uint8_t rcvDataSizeMsb;	/* FC Word 1, bit  8:15 */
464 	uint8_t rcvDataSizeLsb;	/* FC Word 1, bit  0: 7 */
465 
466 	uint8_t concurrentSeqMsb;	/* FC Word 2, bit 24:31 */
467 	uint8_t concurrentSeqLsb;	/* FC Word 2, bit 16:23 */
468 	uint8_t EeCreditSeqMsb;	/* FC Word 2, bit  8:15 */
469 	uint8_t EeCreditSeqLsb;	/* FC Word 2, bit  0: 7 */
470 
471 	uint8_t openSeqPerXchgMsb;	/* FC Word 3, bit 24:31 */
472 	uint8_t openSeqPerXchgLsb;	/* FC Word 3, bit 16:23 */
473 	uint8_t word3Reserved1;	/* Fc Word 3, bit  8:15 */
474 	uint8_t word3Reserved2;	/* Fc Word 3, bit  0: 7 */
475 };
476 
477 struct serv_parm {	/* Structure is in Big Endian format */
478 	struct csp cmn;
479 	struct lpfc_name portName;
480 	struct lpfc_name nodeName;
481 	struct class_parms cls1;
482 	struct class_parms cls2;
483 	struct class_parms cls3;
484 	struct class_parms cls4;
485 	uint8_t vendorVersion[16];
486 };
487 
488 /*
489  * Virtual Fabric Tagging Header
490  */
491 struct fc_vft_header {
492 	 uint32_t word0;
493 #define fc_vft_hdr_r_ctl_SHIFT		24
494 #define fc_vft_hdr_r_ctl_MASK		0xFF
495 #define fc_vft_hdr_r_ctl_WORD		word0
496 #define fc_vft_hdr_ver_SHIFT		22
497 #define fc_vft_hdr_ver_MASK		0x3
498 #define fc_vft_hdr_ver_WORD		word0
499 #define fc_vft_hdr_type_SHIFT		18
500 #define fc_vft_hdr_type_MASK		0xF
501 #define fc_vft_hdr_type_WORD		word0
502 #define fc_vft_hdr_e_SHIFT		16
503 #define fc_vft_hdr_e_MASK		0x1
504 #define fc_vft_hdr_e_WORD		word0
505 #define fc_vft_hdr_priority_SHIFT	13
506 #define fc_vft_hdr_priority_MASK	0x7
507 #define fc_vft_hdr_priority_WORD	word0
508 #define fc_vft_hdr_vf_id_SHIFT		1
509 #define fc_vft_hdr_vf_id_MASK		0xFFF
510 #define fc_vft_hdr_vf_id_WORD		word0
511 	uint32_t word1;
512 #define fc_vft_hdr_hopct_SHIFT		24
513 #define fc_vft_hdr_hopct_MASK		0xFF
514 #define fc_vft_hdr_hopct_WORD		word1
515 };
516 
517 /*
518  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
519  */
520 #ifdef __BIG_ENDIAN_BITFIELD
521 #define ELS_CMD_MASK      0xffff0000
522 #define ELS_RSP_MASK      0xff000000
523 #define ELS_CMD_LS_RJT    0x01000000
524 #define ELS_CMD_ACC       0x02000000
525 #define ELS_CMD_PLOGI     0x03000000
526 #define ELS_CMD_FLOGI     0x04000000
527 #define ELS_CMD_LOGO      0x05000000
528 #define ELS_CMD_ABTX      0x06000000
529 #define ELS_CMD_RCS       0x07000000
530 #define ELS_CMD_RES       0x08000000
531 #define ELS_CMD_RSS       0x09000000
532 #define ELS_CMD_RSI       0x0A000000
533 #define ELS_CMD_ESTS      0x0B000000
534 #define ELS_CMD_ESTC      0x0C000000
535 #define ELS_CMD_ADVC      0x0D000000
536 #define ELS_CMD_RTV       0x0E000000
537 #define ELS_CMD_RLS       0x0F000000
538 #define ELS_CMD_ECHO      0x10000000
539 #define ELS_CMD_TEST      0x11000000
540 #define ELS_CMD_RRQ       0x12000000
541 #define ELS_CMD_PRLI      0x20100014
542 #define ELS_CMD_PRLO      0x21100014
543 #define ELS_CMD_PRLO_ACC  0x02100014
544 #define ELS_CMD_PDISC     0x50000000
545 #define ELS_CMD_FDISC     0x51000000
546 #define ELS_CMD_ADISC     0x52000000
547 #define ELS_CMD_FARP      0x54000000
548 #define ELS_CMD_FARPR     0x55000000
549 #define ELS_CMD_RPS       0x56000000
550 #define ELS_CMD_RPL       0x57000000
551 #define ELS_CMD_FAN       0x60000000
552 #define ELS_CMD_RSCN      0x61040000
553 #define ELS_CMD_SCR       0x62000000
554 #define ELS_CMD_RNID      0x78000000
555 #define ELS_CMD_LIRR      0x7A000000
556 #else	/*  __LITTLE_ENDIAN_BITFIELD */
557 #define ELS_CMD_MASK      0xffff
558 #define ELS_RSP_MASK      0xff
559 #define ELS_CMD_LS_RJT    0x01
560 #define ELS_CMD_ACC       0x02
561 #define ELS_CMD_PLOGI     0x03
562 #define ELS_CMD_FLOGI     0x04
563 #define ELS_CMD_LOGO      0x05
564 #define ELS_CMD_ABTX      0x06
565 #define ELS_CMD_RCS       0x07
566 #define ELS_CMD_RES       0x08
567 #define ELS_CMD_RSS       0x09
568 #define ELS_CMD_RSI       0x0A
569 #define ELS_CMD_ESTS      0x0B
570 #define ELS_CMD_ESTC      0x0C
571 #define ELS_CMD_ADVC      0x0D
572 #define ELS_CMD_RTV       0x0E
573 #define ELS_CMD_RLS       0x0F
574 #define ELS_CMD_ECHO      0x10
575 #define ELS_CMD_TEST      0x11
576 #define ELS_CMD_RRQ       0x12
577 #define ELS_CMD_PRLI      0x14001020
578 #define ELS_CMD_PRLO      0x14001021
579 #define ELS_CMD_PRLO_ACC  0x14001002
580 #define ELS_CMD_PDISC     0x50
581 #define ELS_CMD_FDISC     0x51
582 #define ELS_CMD_ADISC     0x52
583 #define ELS_CMD_FARP      0x54
584 #define ELS_CMD_FARPR     0x55
585 #define ELS_CMD_RPS       0x56
586 #define ELS_CMD_RPL       0x57
587 #define ELS_CMD_FAN       0x60
588 #define ELS_CMD_RSCN      0x0461
589 #define ELS_CMD_SCR       0x62
590 #define ELS_CMD_RNID      0x78
591 #define ELS_CMD_LIRR      0x7A
592 #endif
593 
594 /*
595  *  LS_RJT Payload Definition
596  */
597 
598 struct ls_rjt {	/* Structure is in Big Endian format */
599 	union {
600 		uint32_t lsRjtError;
601 		struct {
602 			uint8_t lsRjtRsvd0;	/* FC Word 0, bit 24:31 */
603 
604 			uint8_t lsRjtRsnCode;	/* FC Word 0, bit 16:23 */
605 			/* LS_RJT reason codes */
606 #define LSRJT_INVALID_CMD     0x01
607 #define LSRJT_LOGICAL_ERR     0x03
608 #define LSRJT_LOGICAL_BSY     0x05
609 #define LSRJT_PROTOCOL_ERR    0x07
610 #define LSRJT_UNABLE_TPC      0x09	/* Unable to perform command */
611 #define LSRJT_CMD_UNSUPPORTED 0x0B
612 #define LSRJT_VENDOR_UNIQUE   0xFF	/* See Byte 3 */
613 
614 			uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
615 			/* LS_RJT reason explanation */
616 #define LSEXP_NOTHING_MORE      0x00
617 #define LSEXP_SPARM_OPTIONS     0x01
618 #define LSEXP_SPARM_ICTL        0x03
619 #define LSEXP_SPARM_RCTL        0x05
620 #define LSEXP_SPARM_RCV_SIZE    0x07
621 #define LSEXP_SPARM_CONCUR_SEQ  0x09
622 #define LSEXP_SPARM_CREDIT      0x0B
623 #define LSEXP_INVALID_PNAME     0x0D
624 #define LSEXP_INVALID_NNAME     0x0E
625 #define LSEXP_INVALID_CSP       0x0F
626 #define LSEXP_INVALID_ASSOC_HDR 0x11
627 #define LSEXP_ASSOC_HDR_REQ     0x13
628 #define LSEXP_INVALID_O_SID     0x15
629 #define LSEXP_INVALID_OX_RX     0x17
630 #define LSEXP_CMD_IN_PROGRESS   0x19
631 #define LSEXP_PORT_LOGIN_REQ    0x1E
632 #define LSEXP_INVALID_NPORT_ID  0x1F
633 #define LSEXP_INVALID_SEQ_ID    0x21
634 #define LSEXP_INVALID_XCHG      0x23
635 #define LSEXP_INACTIVE_XCHG     0x25
636 #define LSEXP_RQ_REQUIRED       0x27
637 #define LSEXP_OUT_OF_RESOURCE   0x29
638 #define LSEXP_CANT_GIVE_DATA    0x2A
639 #define LSEXP_REQ_UNSUPPORTED   0x2C
640 			uint8_t vendorUnique;	/* FC Word 0, bit  0: 7 */
641 		} b;
642 	} un;
643 };
644 
645 /*
646  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
647  */
648 
649 typedef struct _LOGO {		/* Structure is in Big Endian format */
650 	union {
651 		uint32_t nPortId32;	/* Access nPortId as a word */
652 		struct {
653 			uint8_t word1Reserved1;	/* FC Word 1, bit 31:24 */
654 			uint8_t nPortIdByte0;	/* N_port  ID bit 16:23 */
655 			uint8_t nPortIdByte1;	/* N_port  ID bit  8:15 */
656 			uint8_t nPortIdByte2;	/* N_port  ID bit  0: 7 */
657 		} b;
658 	} un;
659 	struct lpfc_name portName;	/* N_port name field */
660 } LOGO;
661 
662 /*
663  *  FCP Login (PRLI Request / ACC) Payload Definition
664  */
665 
666 #define PRLX_PAGE_LEN   0x10
667 #define TPRLO_PAGE_LEN  0x14
668 
669 typedef struct _PRLI {		/* Structure is in Big Endian format */
670 	uint8_t prliType;	/* FC Parm Word 0, bit 24:31 */
671 
672 #define PRLI_FCP_TYPE 0x08
673 	uint8_t word0Reserved1;	/* FC Parm Word 0, bit 16:23 */
674 
675 #ifdef __BIG_ENDIAN_BITFIELD
676 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
677 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
678 	uint8_t estabImagePair:1;	/* FC Parm Word 0, bit 13 */
679 
680 	/*    ACC = imagePairEstablished */
681 	uint8_t word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
682 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
683 #else	/*  __LITTLE_ENDIAN_BITFIELD */
684 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
685 	uint8_t word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
686 	uint8_t estabImagePair:1;	/* FC Parm Word 0, bit 13 */
687 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
688 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
689 	/*    ACC = imagePairEstablished */
690 #endif
691 
692 #define PRLI_REQ_EXECUTED     0x1	/* acceptRspCode */
693 #define PRLI_NO_RESOURCES     0x2
694 #define PRLI_INIT_INCOMPLETE  0x3
695 #define PRLI_NO_SUCH_PA       0x4
696 #define PRLI_PREDEF_CONFIG    0x5
697 #define PRLI_PARTIAL_SUCCESS  0x6
698 #define PRLI_INVALID_PAGE_CNT 0x7
699 	uint8_t word0Reserved3;	/* FC Parm Word 0, bit 0:7 */
700 
701 	uint32_t origProcAssoc;	/* FC Parm Word 1, bit 0:31 */
702 
703 	uint32_t respProcAssoc;	/* FC Parm Word 2, bit 0:31 */
704 
705 	uint8_t word3Reserved1;	/* FC Parm Word 3, bit 24:31 */
706 	uint8_t word3Reserved2;	/* FC Parm Word 3, bit 16:23 */
707 
708 #ifdef __BIG_ENDIAN_BITFIELD
709 	uint16_t Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
710 	uint16_t Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
711 	uint16_t Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
712 	uint16_t Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
713 	uint16_t Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
714 	uint16_t Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
715 	uint16_t TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
716 	uint16_t Retry:1;	/* FC Parm Word 3, bit  8 */
717 	uint16_t ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
718 	uint16_t dataOverLay:1;	/* FC Parm Word 3, bit  6 */
719 	uint16_t initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
720 	uint16_t targetFunc:1;	/* FC Parm Word 3, bit  4 */
721 	uint16_t cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
722 	uint16_t dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
723 	uint16_t readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
724 	uint16_t writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
725 #else	/*  __LITTLE_ENDIAN_BITFIELD */
726 	uint16_t Retry:1;	/* FC Parm Word 3, bit  8 */
727 	uint16_t TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
728 	uint16_t Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
729 	uint16_t Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
730 	uint16_t Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
731 	uint16_t Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
732 	uint16_t Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
733 	uint16_t Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
734 	uint16_t writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
735 	uint16_t readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
736 	uint16_t dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
737 	uint16_t cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
738 	uint16_t targetFunc:1;	/* FC Parm Word 3, bit  4 */
739 	uint16_t initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
740 	uint16_t dataOverLay:1;	/* FC Parm Word 3, bit  6 */
741 	uint16_t ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
742 #endif
743 } PRLI;
744 
745 /*
746  *  FCP Logout (PRLO Request / ACC) Payload Definition
747  */
748 
749 typedef struct _PRLO {		/* Structure is in Big Endian format */
750 	uint8_t prloType;	/* FC Parm Word 0, bit 24:31 */
751 
752 #define PRLO_FCP_TYPE  0x08
753 	uint8_t word0Reserved1;	/* FC Parm Word 0, bit 16:23 */
754 
755 #ifdef __BIG_ENDIAN_BITFIELD
756 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
757 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
758 	uint8_t word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
759 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
760 #else	/*  __LITTLE_ENDIAN_BITFIELD */
761 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
762 	uint8_t word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
763 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
764 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
765 #endif
766 
767 #define PRLO_REQ_EXECUTED     0x1	/* acceptRspCode */
768 #define PRLO_NO_SUCH_IMAGE    0x4
769 #define PRLO_INVALID_PAGE_CNT 0x7
770 
771 	uint8_t word0Reserved3;	/* FC Parm Word 0, bit 0:7 */
772 
773 	uint32_t origProcAssoc;	/* FC Parm Word 1, bit 0:31 */
774 
775 	uint32_t respProcAssoc;	/* FC Parm Word 2, bit 0:31 */
776 
777 	uint32_t word3Reserved1;	/* FC Parm Word 3, bit 0:31 */
778 } PRLO;
779 
780 typedef struct _ADISC {		/* Structure is in Big Endian format */
781 	uint32_t hardAL_PA;
782 	struct lpfc_name portName;
783 	struct lpfc_name nodeName;
784 	uint32_t DID;
785 } ADISC;
786 
787 typedef struct _FARP {		/* Structure is in Big Endian format */
788 	uint32_t Mflags:8;
789 	uint32_t Odid:24;
790 #define FARP_NO_ACTION          0	/* FARP information enclosed, no
791 					   action */
792 #define FARP_MATCH_PORT         0x1	/* Match on Responder Port Name */
793 #define FARP_MATCH_NODE         0x2	/* Match on Responder Node Name */
794 #define FARP_MATCH_IP           0x4	/* Match on IP address, not supported */
795 #define FARP_MATCH_IPV4         0x5	/* Match on IPV4 address, not
796 					   supported */
797 #define FARP_MATCH_IPV6         0x6	/* Match on IPV6 address, not
798 					   supported */
799 	uint32_t Rflags:8;
800 	uint32_t Rdid:24;
801 #define FARP_REQUEST_PLOGI      0x1	/* Request for PLOGI */
802 #define FARP_REQUEST_FARPR      0x2	/* Request for FARP Response */
803 	struct lpfc_name OportName;
804 	struct lpfc_name OnodeName;
805 	struct lpfc_name RportName;
806 	struct lpfc_name RnodeName;
807 	uint8_t Oipaddr[16];
808 	uint8_t Ripaddr[16];
809 } FARP;
810 
811 typedef struct _FAN {		/* Structure is in Big Endian format */
812 	uint32_t Fdid;
813 	struct lpfc_name FportName;
814 	struct lpfc_name FnodeName;
815 } FAN;
816 
817 typedef struct _SCR {		/* Structure is in Big Endian format */
818 	uint8_t resvd1;
819 	uint8_t resvd2;
820 	uint8_t resvd3;
821 	uint8_t Function;
822 #define  SCR_FUNC_FABRIC     0x01
823 #define  SCR_FUNC_NPORT      0x02
824 #define  SCR_FUNC_FULL       0x03
825 #define  SCR_CLEAR           0xff
826 } SCR;
827 
828 typedef struct _RNID_TOP_DISC {
829 	struct lpfc_name portName;
830 	uint8_t resvd[8];
831 	uint32_t unitType;
832 #define RNID_HBA            0x7
833 #define RNID_HOST           0xa
834 #define RNID_DRIVER         0xd
835 	uint32_t physPort;
836 	uint32_t attachedNodes;
837 	uint16_t ipVersion;
838 #define RNID_IPV4           0x1
839 #define RNID_IPV6           0x2
840 	uint16_t UDPport;
841 	uint8_t ipAddr[16];
842 	uint16_t resvd1;
843 	uint16_t flags;
844 #define RNID_TD_SUPPORT     0x1
845 #define RNID_LP_VALID       0x2
846 } RNID_TOP_DISC;
847 
848 typedef struct _RNID {		/* Structure is in Big Endian format */
849 	uint8_t Format;
850 #define RNID_TOPOLOGY_DISC  0xdf
851 	uint8_t CommonLen;
852 	uint8_t resvd1;
853 	uint8_t SpecificLen;
854 	struct lpfc_name portName;
855 	struct lpfc_name nodeName;
856 	union {
857 		RNID_TOP_DISC topologyDisc;	/* topology disc (0xdf) */
858 	} un;
859 } RNID;
860 
861 typedef struct  _RPS {		/* Structure is in Big Endian format */
862 	union {
863 		uint32_t portNum;
864 		struct lpfc_name portName;
865 	} un;
866 } RPS;
867 
868 typedef struct  _RPS_RSP {	/* Structure is in Big Endian format */
869 	uint16_t rsvd1;
870 	uint16_t portStatus;
871 	uint32_t linkFailureCnt;
872 	uint32_t lossSyncCnt;
873 	uint32_t lossSignalCnt;
874 	uint32_t primSeqErrCnt;
875 	uint32_t invalidXmitWord;
876 	uint32_t crcCnt;
877 } RPS_RSP;
878 
879 struct RLS {			/* Structure is in Big Endian format */
880 	uint32_t rls;
881 #define rls_rsvd_SHIFT		24
882 #define rls_rsvd_MASK		0x000000ff
883 #define rls_rsvd_WORD		rls
884 #define rls_did_SHIFT		0
885 #define rls_did_MASK		0x00ffffff
886 #define rls_did_WORD		rls
887 };
888 
889 struct  RLS_RSP {		/* Structure is in Big Endian format */
890 	uint32_t linkFailureCnt;
891 	uint32_t lossSyncCnt;
892 	uint32_t lossSignalCnt;
893 	uint32_t primSeqErrCnt;
894 	uint32_t invalidXmitWord;
895 	uint32_t crcCnt;
896 };
897 
898 struct RRQ {			/* Structure is in Big Endian format */
899 	uint32_t rrq;
900 #define rrq_rsvd_SHIFT		24
901 #define rrq_rsvd_MASK		0x000000ff
902 #define rrq_rsvd_WORD		rrq
903 #define rrq_did_SHIFT		0
904 #define rrq_did_MASK		0x00ffffff
905 #define rrq_did_WORD		rrq
906 	uint32_t rrq_exchg;
907 #define rrq_oxid_SHIFT		16
908 #define rrq_oxid_MASK		0xffff
909 #define rrq_oxid_WORD		rrq_exchg
910 #define rrq_rxid_SHIFT		0
911 #define rrq_rxid_MASK		0xffff
912 #define rrq_rxid_WORD		rrq_exchg
913 };
914 
915 #define LPFC_MAX_VFN_PER_PFN	255 /* Maximum VFs allowed per ARI */
916 #define LPFC_DEF_VFN_PER_PFN	0   /* Default VFs due to platform limitation*/
917 
918 struct RTV_RSP {		/* Structure is in Big Endian format */
919 	uint32_t ratov;
920 	uint32_t edtov;
921 	uint32_t qtov;
922 #define qtov_rsvd0_SHIFT	28
923 #define qtov_rsvd0_MASK		0x0000000f
924 #define qtov_rsvd0_WORD		qtov		/* reserved */
925 #define qtov_edtovres_SHIFT	27
926 #define qtov_edtovres_MASK	0x00000001
927 #define qtov_edtovres_WORD	qtov		/* E_D_TOV Resolution */
928 #define qtov__rsvd1_SHIFT	19
929 #define qtov_rsvd1_MASK		0x0000003f
930 #define qtov_rsvd1_WORD		qtov		/* reserved */
931 #define qtov_rttov_SHIFT	18
932 #define qtov_rttov_MASK		0x00000001
933 #define qtov_rttov_WORD		qtov		/* R_T_TOV value */
934 #define qtov_rsvd2_SHIFT	0
935 #define qtov_rsvd2_MASK		0x0003ffff
936 #define qtov_rsvd2_WORD		qtov		/* reserved */
937 };
938 
939 
940 typedef struct  _RPL {		/* Structure is in Big Endian format */
941 	uint32_t maxsize;
942 	uint32_t index;
943 } RPL;
944 
945 typedef struct  _PORT_NUM_BLK {
946 	uint32_t portNum;
947 	uint32_t portID;
948 	struct lpfc_name portName;
949 } PORT_NUM_BLK;
950 
951 typedef struct  _RPL_RSP {	/* Structure is in Big Endian format */
952 	uint32_t listLen;
953 	uint32_t index;
954 	PORT_NUM_BLK port_num_blk;
955 } RPL_RSP;
956 
957 /* This is used for RSCN command */
958 typedef struct _D_ID {		/* Structure is in Big Endian format */
959 	union {
960 		uint32_t word;
961 		struct {
962 #ifdef __BIG_ENDIAN_BITFIELD
963 			uint8_t resv;
964 			uint8_t domain;
965 			uint8_t area;
966 			uint8_t id;
967 #else	/*  __LITTLE_ENDIAN_BITFIELD */
968 			uint8_t id;
969 			uint8_t area;
970 			uint8_t domain;
971 			uint8_t resv;
972 #endif
973 		} b;
974 	} un;
975 } D_ID;
976 
977 #define RSCN_ADDRESS_FORMAT_PORT	0x0
978 #define RSCN_ADDRESS_FORMAT_AREA	0x1
979 #define RSCN_ADDRESS_FORMAT_DOMAIN	0x2
980 #define RSCN_ADDRESS_FORMAT_FABRIC	0x3
981 #define RSCN_ADDRESS_FORMAT_MASK	0x3
982 
983 /*
984  *  Structure to define all ELS Payload types
985  */
986 
987 typedef struct _ELS_PKT {	/* Structure is in Big Endian format */
988 	uint8_t elsCode;	/* FC Word 0, bit 24:31 */
989 	uint8_t elsByte1;
990 	uint8_t elsByte2;
991 	uint8_t elsByte3;
992 	union {
993 		struct ls_rjt lsRjt;	/* Payload for LS_RJT ELS response */
994 		struct serv_parm logi;	/* Payload for PLOGI/FLOGI/PDISC/ACC */
995 		LOGO logo;	/* Payload for PLOGO/FLOGO/ACC */
996 		PRLI prli;	/* Payload for PRLI/ACC */
997 		PRLO prlo;	/* Payload for PRLO/ACC */
998 		ADISC adisc;	/* Payload for ADISC/ACC */
999 		FARP farp;	/* Payload for FARP/ACC */
1000 		FAN fan;	/* Payload for FAN */
1001 		SCR scr;	/* Payload for SCR/ACC */
1002 		RNID rnid;	/* Payload for RNID */
1003 		uint8_t pad[128 - 4];	/* Pad out to payload of 128 bytes */
1004 	} un;
1005 } ELS_PKT;
1006 
1007 /*
1008  * FDMI
1009  * HBA MAnagement Operations Command Codes
1010  */
1011 #define  SLI_MGMT_GRHL     0x100	/* Get registered HBA list */
1012 #define  SLI_MGMT_GHAT     0x101	/* Get HBA attributes */
1013 #define  SLI_MGMT_GRPL     0x102	/* Get registered Port list */
1014 #define  SLI_MGMT_GPAT     0x110	/* Get Port attributes */
1015 #define  SLI_MGMT_RHBA     0x200	/* Register HBA */
1016 #define  SLI_MGMT_RHAT     0x201	/* Register HBA attributes */
1017 #define  SLI_MGMT_RPRT     0x210	/* Register Port */
1018 #define  SLI_MGMT_RPA      0x211	/* Register Port attributes */
1019 #define  SLI_MGMT_DHBA     0x300	/* De-register HBA */
1020 #define  SLI_MGMT_DPRT     0x310	/* De-register Port */
1021 
1022 /*
1023  * Management Service Subtypes
1024  */
1025 #define  SLI_CT_FDMI_Subtypes     0x10
1026 
1027 /*
1028  * HBA Management Service Reject Code
1029  */
1030 #define  REJECT_CODE             0x9	/* Unable to perform command request */
1031 
1032 /*
1033  * HBA Management Service Reject Reason Code
1034  * Please refer to the Reason Codes above
1035  */
1036 
1037 /*
1038  * HBA Attribute Types
1039  */
1040 #define  NODE_NAME               0x1
1041 #define  MANUFACTURER            0x2
1042 #define  SERIAL_NUMBER           0x3
1043 #define  MODEL                   0x4
1044 #define  MODEL_DESCRIPTION       0x5
1045 #define  HARDWARE_VERSION        0x6
1046 #define  DRIVER_VERSION          0x7
1047 #define  OPTION_ROM_VERSION      0x8
1048 #define  FIRMWARE_VERSION        0x9
1049 #define  OS_NAME_VERSION	 0xa
1050 #define  MAX_CT_PAYLOAD_LEN	 0xb
1051 
1052 /*
1053  * Port Attrubute Types
1054  */
1055 #define  SUPPORTED_FC4_TYPES     0x1
1056 #define  SUPPORTED_SPEED         0x2
1057 #define  PORT_SPEED              0x3
1058 #define  MAX_FRAME_SIZE          0x4
1059 #define  OS_DEVICE_NAME          0x5
1060 #define  HOST_NAME               0x6
1061 
1062 union AttributesDef {
1063 	/* Structure is in Big Endian format */
1064 	struct {
1065 		uint32_t AttrType:16;
1066 		uint32_t AttrLen:16;
1067 	} bits;
1068 	uint32_t word;
1069 };
1070 
1071 
1072 /*
1073  * HBA Attribute Entry (8 - 260 bytes)
1074  */
1075 typedef struct {
1076 	union AttributesDef ad;
1077 	union {
1078 		uint32_t VendorSpecific;
1079 		uint8_t Manufacturer[64];
1080 		uint8_t SerialNumber[64];
1081 		uint8_t Model[256];
1082 		uint8_t ModelDescription[256];
1083 		uint8_t HardwareVersion[256];
1084 		uint8_t DriverVersion[256];
1085 		uint8_t OptionROMVersion[256];
1086 		uint8_t FirmwareVersion[256];
1087 		struct lpfc_name NodeName;
1088 		uint8_t SupportFC4Types[32];
1089 		uint32_t SupportSpeed;
1090 		uint32_t PortSpeed;
1091 		uint32_t MaxFrameSize;
1092 		uint8_t OsDeviceName[256];
1093 		uint8_t OsNameVersion[256];
1094 		uint32_t MaxCTPayloadLen;
1095 		uint8_t HostName[256];
1096 	} un;
1097 } ATTRIBUTE_ENTRY;
1098 
1099 /*
1100  * HBA Attribute Block
1101  */
1102 typedef struct {
1103 	uint32_t EntryCnt;	/* Number of HBA attribute entries */
1104 	ATTRIBUTE_ENTRY Entry;	/* Variable-length array */
1105 } ATTRIBUTE_BLOCK;
1106 
1107 /*
1108  * Port Entry
1109  */
1110 typedef struct {
1111 	struct lpfc_name PortName;
1112 } PORT_ENTRY;
1113 
1114 /*
1115  * HBA Identifier
1116  */
1117 typedef struct {
1118 	struct lpfc_name PortName;
1119 } HBA_IDENTIFIER;
1120 
1121 /*
1122  * Registered Port List Format
1123  */
1124 typedef struct {
1125 	uint32_t EntryCnt;
1126 	PORT_ENTRY pe;		/* Variable-length array */
1127 } REG_PORT_LIST;
1128 
1129 /*
1130  * Register HBA(RHBA)
1131  */
1132 typedef struct {
1133 	HBA_IDENTIFIER hi;
1134 	REG_PORT_LIST rpl;	/* variable-length array */
1135 /* ATTRIBUTE_BLOCK   ab; */
1136 } REG_HBA;
1137 
1138 /*
1139  * Register HBA Attributes (RHAT)
1140  */
1141 typedef struct {
1142 	struct lpfc_name HBA_PortName;
1143 	ATTRIBUTE_BLOCK ab;
1144 } REG_HBA_ATTRIBUTE;
1145 
1146 /*
1147  * Register Port Attributes (RPA)
1148  */
1149 typedef struct {
1150 	struct lpfc_name PortName;
1151 	ATTRIBUTE_BLOCK ab;
1152 } REG_PORT_ATTRIBUTE;
1153 
1154 /*
1155  * Get Registered HBA List (GRHL) Accept Payload Format
1156  */
1157 typedef struct {
1158 	uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1159 	struct lpfc_name HBA_PortName;	/* Variable-length array */
1160 } GRHL_ACC_PAYLOAD;
1161 
1162 /*
1163  * Get Registered Port List (GRPL) Accept Payload Format
1164  */
1165 typedef struct {
1166 	uint32_t RPL_Entry_Cnt;	/* Number of Registered Port Entries */
1167 	PORT_ENTRY Reg_Port_Entry[1];	/* Variable-length array */
1168 } GRPL_ACC_PAYLOAD;
1169 
1170 /*
1171  * Get Port Attributes (GPAT) Accept Payload Format
1172  */
1173 
1174 typedef struct {
1175 	ATTRIBUTE_BLOCK pab;
1176 } GPAT_ACC_PAYLOAD;
1177 
1178 
1179 /*
1180  *  Begin HBA configuration parameters.
1181  *  The PCI configuration register BAR assignments are:
1182  *  BAR0, offset 0x10 - SLIM base memory address
1183  *  BAR1, offset 0x14 - SLIM base memory high address
1184  *  BAR2, offset 0x18 - REGISTER base memory address
1185  *  BAR3, offset 0x1c - REGISTER base memory high address
1186  *  BAR4, offset 0x20 - BIU I/O registers
1187  *  BAR5, offset 0x24 - REGISTER base io high address
1188  */
1189 
1190 /* Number of rings currently used and available. */
1191 #define MAX_CONFIGURED_RINGS     3
1192 #define MAX_RINGS                4
1193 
1194 /* IOCB / Mailbox is owned by FireFly */
1195 #define OWN_CHIP        1
1196 
1197 /* IOCB / Mailbox is owned by Host */
1198 #define OWN_HOST        0
1199 
1200 /* Number of 4-byte words in an IOCB. */
1201 #define IOCB_WORD_SZ    8
1202 
1203 /* network headers for Dfctl field */
1204 #define FC_NET_HDR      0x20
1205 
1206 /* Start FireFly Register definitions */
1207 #define PCI_VENDOR_ID_EMULEX        0x10df
1208 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1209 #define PCI_DEVICE_ID_PROTEUS_VF    0xe100
1210 #define PCI_DEVICE_ID_BALIUS        0xe131
1211 #define PCI_DEVICE_ID_PROTEUS_PF    0xe180
1212 #define PCI_DEVICE_ID_LANCER_FC     0xe200
1213 #define PCI_DEVICE_ID_LANCER_FC_VF  0xe208
1214 #define PCI_DEVICE_ID_LANCER_FCOE   0xe260
1215 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1216 #define PCI_DEVICE_ID_SAT_SMB       0xf011
1217 #define PCI_DEVICE_ID_SAT_MID       0xf015
1218 #define PCI_DEVICE_ID_RFLY          0xf095
1219 #define PCI_DEVICE_ID_PFLY          0xf098
1220 #define PCI_DEVICE_ID_LP101         0xf0a1
1221 #define PCI_DEVICE_ID_TFLY          0xf0a5
1222 #define PCI_DEVICE_ID_BSMB          0xf0d1
1223 #define PCI_DEVICE_ID_BMID          0xf0d5
1224 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1225 #define PCI_DEVICE_ID_ZMID          0xf0e5
1226 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1227 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1228 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1229 #define PCI_DEVICE_ID_SAT           0xf100
1230 #define PCI_DEVICE_ID_SAT_SCSP      0xf111
1231 #define PCI_DEVICE_ID_SAT_DCSP      0xf112
1232 #define PCI_DEVICE_ID_FALCON        0xf180
1233 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1234 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1235 #define PCI_DEVICE_ID_CENTAUR       0xf900
1236 #define PCI_DEVICE_ID_PEGASUS       0xf980
1237 #define PCI_DEVICE_ID_THOR          0xfa00
1238 #define PCI_DEVICE_ID_VIPER         0xfb00
1239 #define PCI_DEVICE_ID_LP10000S      0xfc00
1240 #define PCI_DEVICE_ID_LP11000S      0xfc10
1241 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1242 #define PCI_DEVICE_ID_SAT_S         0xfc40
1243 #define PCI_DEVICE_ID_PROTEUS_S     0xfc50
1244 #define PCI_DEVICE_ID_HELIOS        0xfd00
1245 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1246 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1247 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1248 #define PCI_DEVICE_ID_HORNET        0xfe05
1249 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1250 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1251 #define PCI_VENDOR_ID_SERVERENGINE  0x19a2
1252 #define PCI_DEVICE_ID_TIGERSHARK    0x0704
1253 #define PCI_DEVICE_ID_TOMCAT        0x0714
1254 
1255 #define JEDEC_ID_ADDRESS            0x0080001c
1256 #define FIREFLY_JEDEC_ID            0x1ACC
1257 #define SUPERFLY_JEDEC_ID           0x0020
1258 #define DRAGONFLY_JEDEC_ID          0x0021
1259 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1260 #define CENTAUR_2G_JEDEC_ID         0x0026
1261 #define CENTAUR_1G_JEDEC_ID         0x0028
1262 #define PEGASUS_ORION_JEDEC_ID      0x0036
1263 #define PEGASUS_JEDEC_ID            0x0038
1264 #define THOR_JEDEC_ID               0x0012
1265 #define HELIOS_JEDEC_ID             0x0364
1266 #define ZEPHYR_JEDEC_ID             0x0577
1267 #define VIPER_JEDEC_ID              0x4838
1268 #define SATURN_JEDEC_ID             0x1004
1269 #define HORNET_JDEC_ID              0x2057706D
1270 
1271 #define JEDEC_ID_MASK               0x0FFFF000
1272 #define JEDEC_ID_SHIFT              12
1273 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1274 
1275 typedef struct {		/* FireFly BIU registers */
1276 	uint32_t hostAtt;	/* See definitions for Host Attention
1277 				   register */
1278 	uint32_t chipAtt;	/* See definitions for Chip Attention
1279 				   register */
1280 	uint32_t hostStatus;	/* See definitions for Host Status register */
1281 	uint32_t hostControl;	/* See definitions for Host Control register */
1282 	uint32_t buiConfig;	/* See definitions for BIU configuration
1283 				   register */
1284 } FF_REGS;
1285 
1286 /* IO Register size in bytes */
1287 #define FF_REG_AREA_SIZE       256
1288 
1289 /* Host Attention Register */
1290 
1291 #define HA_REG_OFFSET  0	/* Byte offset from register base address */
1292 
1293 #define HA_R0RE_REQ    0x00000001	/* Bit  0 */
1294 #define HA_R0CE_RSP    0x00000002	/* Bit  1 */
1295 #define HA_R0ATT       0x00000008	/* Bit  3 */
1296 #define HA_R1RE_REQ    0x00000010	/* Bit  4 */
1297 #define HA_R1CE_RSP    0x00000020	/* Bit  5 */
1298 #define HA_R1ATT       0x00000080	/* Bit  7 */
1299 #define HA_R2RE_REQ    0x00000100	/* Bit  8 */
1300 #define HA_R2CE_RSP    0x00000200	/* Bit  9 */
1301 #define HA_R2ATT       0x00000800	/* Bit 11 */
1302 #define HA_R3RE_REQ    0x00001000	/* Bit 12 */
1303 #define HA_R3CE_RSP    0x00002000	/* Bit 13 */
1304 #define HA_R3ATT       0x00008000	/* Bit 15 */
1305 #define HA_LATT        0x20000000	/* Bit 29 */
1306 #define HA_MBATT       0x40000000	/* Bit 30 */
1307 #define HA_ERATT       0x80000000	/* Bit 31 */
1308 
1309 #define HA_RXRE_REQ    0x00000001	/* Bit  0 */
1310 #define HA_RXCE_RSP    0x00000002	/* Bit  1 */
1311 #define HA_RXATT       0x00000008	/* Bit  3 */
1312 #define HA_RXMASK      0x0000000f
1313 
1314 #define HA_R0_CLR_MSK	(HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1315 #define HA_R1_CLR_MSK	(HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1316 #define HA_R2_CLR_MSK	(HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1317 #define HA_R3_CLR_MSK	(HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1318 
1319 #define HA_R0_POS	3
1320 #define HA_R1_POS	7
1321 #define HA_R2_POS	11
1322 #define HA_R3_POS	15
1323 #define HA_LE_POS	29
1324 #define HA_MB_POS	30
1325 #define HA_ER_POS	31
1326 /* Chip Attention Register */
1327 
1328 #define CA_REG_OFFSET  4	/* Byte offset from register base address */
1329 
1330 #define CA_R0CE_REQ    0x00000001	/* Bit  0 */
1331 #define CA_R0RE_RSP    0x00000002	/* Bit  1 */
1332 #define CA_R0ATT       0x00000008	/* Bit  3 */
1333 #define CA_R1CE_REQ    0x00000010	/* Bit  4 */
1334 #define CA_R1RE_RSP    0x00000020	/* Bit  5 */
1335 #define CA_R1ATT       0x00000080	/* Bit  7 */
1336 #define CA_R2CE_REQ    0x00000100	/* Bit  8 */
1337 #define CA_R2RE_RSP    0x00000200	/* Bit  9 */
1338 #define CA_R2ATT       0x00000800	/* Bit 11 */
1339 #define CA_R3CE_REQ    0x00001000	/* Bit 12 */
1340 #define CA_R3RE_RSP    0x00002000	/* Bit 13 */
1341 #define CA_R3ATT       0x00008000	/* Bit 15 */
1342 #define CA_MBATT       0x40000000	/* Bit 30 */
1343 
1344 /* Host Status Register */
1345 
1346 #define HS_REG_OFFSET  8	/* Byte offset from register base address */
1347 
1348 #define HS_MBRDY       0x00400000	/* Bit 22 */
1349 #define HS_FFRDY       0x00800000	/* Bit 23 */
1350 #define HS_FFER8       0x01000000	/* Bit 24 */
1351 #define HS_FFER7       0x02000000	/* Bit 25 */
1352 #define HS_FFER6       0x04000000	/* Bit 26 */
1353 #define HS_FFER5       0x08000000	/* Bit 27 */
1354 #define HS_FFER4       0x10000000	/* Bit 28 */
1355 #define HS_FFER3       0x20000000	/* Bit 29 */
1356 #define HS_FFER2       0x40000000	/* Bit 30 */
1357 #define HS_FFER1       0x80000000	/* Bit 31 */
1358 #define HS_CRIT_TEMP   0x00000100	/* Bit 8  */
1359 #define HS_FFERM       0xFF000100	/* Mask for error bits 31:24 and 8 */
1360 #define UNPLUG_ERR     0x00000001	/* Indicate pci hot unplug */
1361 /* Host Control Register */
1362 
1363 #define HC_REG_OFFSET  12	/* Byte offset from register base address */
1364 
1365 #define HC_MBINT_ENA   0x00000001	/* Bit  0 */
1366 #define HC_R0INT_ENA   0x00000002	/* Bit  1 */
1367 #define HC_R1INT_ENA   0x00000004	/* Bit  2 */
1368 #define HC_R2INT_ENA   0x00000008	/* Bit  3 */
1369 #define HC_R3INT_ENA   0x00000010	/* Bit  4 */
1370 #define HC_INITHBI     0x02000000	/* Bit 25 */
1371 #define HC_INITMB      0x04000000	/* Bit 26 */
1372 #define HC_INITFF      0x08000000	/* Bit 27 */
1373 #define HC_LAINT_ENA   0x20000000	/* Bit 29 */
1374 #define HC_ERINT_ENA   0x80000000	/* Bit 31 */
1375 
1376 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1377 #define MSIX_DFLT_ID	0
1378 #define MSIX_RNG0_ID	0
1379 #define MSIX_RNG1_ID	1
1380 #define MSIX_RNG2_ID	2
1381 #define MSIX_RNG3_ID	3
1382 
1383 #define MSIX_LINK_ID	4
1384 #define MSIX_MBOX_ID	5
1385 
1386 #define MSIX_SPARE0_ID	6
1387 #define MSIX_SPARE1_ID	7
1388 
1389 /* Mailbox Commands */
1390 #define MBX_SHUTDOWN        0x00	/* terminate testing */
1391 #define MBX_LOAD_SM         0x01
1392 #define MBX_READ_NV         0x02
1393 #define MBX_WRITE_NV        0x03
1394 #define MBX_RUN_BIU_DIAG    0x04
1395 #define MBX_INIT_LINK       0x05
1396 #define MBX_DOWN_LINK       0x06
1397 #define MBX_CONFIG_LINK     0x07
1398 #define MBX_CONFIG_RING     0x09
1399 #define MBX_RESET_RING      0x0A
1400 #define MBX_READ_CONFIG     0x0B
1401 #define MBX_READ_RCONFIG    0x0C
1402 #define MBX_READ_SPARM      0x0D
1403 #define MBX_READ_STATUS     0x0E
1404 #define MBX_READ_RPI        0x0F
1405 #define MBX_READ_XRI        0x10
1406 #define MBX_READ_REV        0x11
1407 #define MBX_READ_LNK_STAT   0x12
1408 #define MBX_REG_LOGIN       0x13
1409 #define MBX_UNREG_LOGIN     0x14
1410 #define MBX_CLEAR_LA        0x16
1411 #define MBX_DUMP_MEMORY     0x17
1412 #define MBX_DUMP_CONTEXT    0x18
1413 #define MBX_RUN_DIAGS       0x19
1414 #define MBX_RESTART         0x1A
1415 #define MBX_UPDATE_CFG      0x1B
1416 #define MBX_DOWN_LOAD       0x1C
1417 #define MBX_DEL_LD_ENTRY    0x1D
1418 #define MBX_RUN_PROGRAM     0x1E
1419 #define MBX_SET_MASK        0x20
1420 #define MBX_SET_VARIABLE    0x21
1421 #define MBX_UNREG_D_ID      0x23
1422 #define MBX_KILL_BOARD      0x24
1423 #define MBX_CONFIG_FARP     0x25
1424 #define MBX_BEACON          0x2A
1425 #define MBX_CONFIG_MSI      0x30
1426 #define MBX_HEARTBEAT       0x31
1427 #define MBX_WRITE_VPARMS    0x32
1428 #define MBX_ASYNCEVT_ENABLE 0x33
1429 #define MBX_READ_EVENT_LOG_STATUS 0x37
1430 #define MBX_READ_EVENT_LOG  0x38
1431 #define MBX_WRITE_EVENT_LOG 0x39
1432 
1433 #define MBX_PORT_CAPABILITIES 0x3B
1434 #define MBX_PORT_IOV_CONTROL 0x3C
1435 
1436 #define MBX_CONFIG_HBQ	    0x7C
1437 #define MBX_LOAD_AREA       0x81
1438 #define MBX_RUN_BIU_DIAG64  0x84
1439 #define MBX_CONFIG_PORT     0x88
1440 #define MBX_READ_SPARM64    0x8D
1441 #define MBX_READ_RPI64      0x8F
1442 #define MBX_REG_LOGIN64     0x93
1443 #define MBX_READ_TOPOLOGY   0x95
1444 #define MBX_REG_VPI	    0x96
1445 #define MBX_UNREG_VPI	    0x97
1446 
1447 #define MBX_WRITE_WWN       0x98
1448 #define MBX_SET_DEBUG       0x99
1449 #define MBX_LOAD_EXP_ROM    0x9C
1450 #define MBX_SLI4_CONFIG	    0x9B
1451 #define MBX_SLI4_REQ_FTRS   0x9D
1452 #define MBX_MAX_CMDS        0x9E
1453 #define MBX_RESUME_RPI      0x9E
1454 #define MBX_SLI2_CMD_MASK   0x80
1455 #define MBX_REG_VFI         0x9F
1456 #define MBX_REG_FCFI        0xA0
1457 #define MBX_UNREG_VFI       0xA1
1458 #define MBX_UNREG_FCFI	    0xA2
1459 #define MBX_INIT_VFI        0xA3
1460 #define MBX_INIT_VPI        0xA4
1461 
1462 #define MBX_AUTH_PORT       0xF8
1463 #define MBX_SECURITY_MGMT   0xF9
1464 
1465 /* IOCB Commands */
1466 
1467 #define CMD_RCV_SEQUENCE_CX     0x01
1468 #define CMD_XMIT_SEQUENCE_CR    0x02
1469 #define CMD_XMIT_SEQUENCE_CX    0x03
1470 #define CMD_XMIT_BCAST_CN       0x04
1471 #define CMD_XMIT_BCAST_CX       0x05
1472 #define CMD_QUE_RING_BUF_CN     0x06
1473 #define CMD_QUE_XRI_BUF_CX      0x07
1474 #define CMD_IOCB_CONTINUE_CN    0x08
1475 #define CMD_RET_XRI_BUF_CX      0x09
1476 #define CMD_ELS_REQUEST_CR      0x0A
1477 #define CMD_ELS_REQUEST_CX      0x0B
1478 #define CMD_RCV_ELS_REQ_CX      0x0D
1479 #define CMD_ABORT_XRI_CN        0x0E
1480 #define CMD_ABORT_XRI_CX        0x0F
1481 #define CMD_CLOSE_XRI_CN        0x10
1482 #define CMD_CLOSE_XRI_CX        0x11
1483 #define CMD_CREATE_XRI_CR       0x12
1484 #define CMD_CREATE_XRI_CX       0x13
1485 #define CMD_GET_RPI_CN          0x14
1486 #define CMD_XMIT_ELS_RSP_CX     0x15
1487 #define CMD_GET_RPI_CR          0x16
1488 #define CMD_XRI_ABORTED_CX      0x17
1489 #define CMD_FCP_IWRITE_CR       0x18
1490 #define CMD_FCP_IWRITE_CX       0x19
1491 #define CMD_FCP_IREAD_CR        0x1A
1492 #define CMD_FCP_IREAD_CX        0x1B
1493 #define CMD_FCP_ICMND_CR        0x1C
1494 #define CMD_FCP_ICMND_CX        0x1D
1495 #define CMD_FCP_TSEND_CX        0x1F
1496 #define CMD_FCP_TRECEIVE_CX     0x21
1497 #define CMD_FCP_TRSP_CX	        0x23
1498 #define CMD_FCP_AUTO_TRSP_CX    0x29
1499 
1500 #define CMD_ADAPTER_MSG         0x20
1501 #define CMD_ADAPTER_DUMP        0x22
1502 
1503 /*  SLI_2 IOCB Command Set */
1504 
1505 #define CMD_ASYNC_STATUS        0x7C
1506 #define CMD_RCV_SEQUENCE64_CX   0x81
1507 #define CMD_XMIT_SEQUENCE64_CR  0x82
1508 #define CMD_XMIT_SEQUENCE64_CX  0x83
1509 #define CMD_XMIT_BCAST64_CN     0x84
1510 #define CMD_XMIT_BCAST64_CX     0x85
1511 #define CMD_QUE_RING_BUF64_CN   0x86
1512 #define CMD_QUE_XRI_BUF64_CX    0x87
1513 #define CMD_IOCB_CONTINUE64_CN  0x88
1514 #define CMD_RET_XRI_BUF64_CX    0x89
1515 #define CMD_ELS_REQUEST64_CR    0x8A
1516 #define CMD_ELS_REQUEST64_CX    0x8B
1517 #define CMD_ABORT_MXRI64_CN     0x8C
1518 #define CMD_RCV_ELS_REQ64_CX    0x8D
1519 #define CMD_XMIT_ELS_RSP64_CX   0x95
1520 #define CMD_XMIT_BLS_RSP64_CX   0x97
1521 #define CMD_FCP_IWRITE64_CR     0x98
1522 #define CMD_FCP_IWRITE64_CX     0x99
1523 #define CMD_FCP_IREAD64_CR      0x9A
1524 #define CMD_FCP_IREAD64_CX      0x9B
1525 #define CMD_FCP_ICMND64_CR      0x9C
1526 #define CMD_FCP_ICMND64_CX      0x9D
1527 #define CMD_FCP_TSEND64_CX      0x9F
1528 #define CMD_FCP_TRECEIVE64_CX   0xA1
1529 #define CMD_FCP_TRSP64_CX       0xA3
1530 
1531 #define CMD_QUE_XRI64_CX	0xB3
1532 #define CMD_IOCB_RCV_SEQ64_CX	0xB5
1533 #define CMD_IOCB_RCV_ELS64_CX	0xB7
1534 #define CMD_IOCB_RET_XRI64_CX	0xB9
1535 #define CMD_IOCB_RCV_CONT64_CX	0xBB
1536 
1537 #define CMD_GEN_REQUEST64_CR    0xC2
1538 #define CMD_GEN_REQUEST64_CX    0xC3
1539 
1540 /* Unhandled SLI-3 Commands */
1541 #define CMD_IOCB_XMIT_MSEQ64_CR		0xB0
1542 #define CMD_IOCB_XMIT_MSEQ64_CX		0xB1
1543 #define CMD_IOCB_RCV_SEQ_LIST64_CX	0xC1
1544 #define CMD_IOCB_RCV_ELS_LIST64_CX	0xCD
1545 #define CMD_IOCB_CLOSE_EXTENDED_CN	0xB6
1546 #define CMD_IOCB_ABORT_EXTENDED_CN	0xBA
1547 #define CMD_IOCB_RET_HBQE64_CN		0xCA
1548 #define CMD_IOCB_FCP_IBIDIR64_CR	0xAC
1549 #define CMD_IOCB_FCP_IBIDIR64_CX	0xAD
1550 #define CMD_IOCB_FCP_ITASKMGT64_CX	0xAF
1551 #define CMD_IOCB_LOGENTRY_CN		0x94
1552 #define CMD_IOCB_LOGENTRY_ASYNC_CN	0x96
1553 
1554 /* Data Security SLI Commands */
1555 #define DSSCMD_IWRITE64_CR		0xF8
1556 #define DSSCMD_IWRITE64_CX		0xF9
1557 #define DSSCMD_IREAD64_CR		0xFA
1558 #define DSSCMD_IREAD64_CX		0xFB
1559 
1560 #define CMD_MAX_IOCB_CMD        0xFB
1561 #define CMD_IOCB_MASK           0xff
1562 
1563 #define MAX_MSG_DATA            28	/* max msg data in CMD_ADAPTER_MSG
1564 					   iocb */
1565 #define LPFC_MAX_ADPTMSG         32	/* max msg data */
1566 /*
1567  *  Define Status
1568  */
1569 #define MBX_SUCCESS                 0
1570 #define MBXERR_NUM_RINGS            1
1571 #define MBXERR_NUM_IOCBS            2
1572 #define MBXERR_IOCBS_EXCEEDED       3
1573 #define MBXERR_BAD_RING_NUMBER      4
1574 #define MBXERR_MASK_ENTRIES_RANGE   5
1575 #define MBXERR_MASKS_EXCEEDED       6
1576 #define MBXERR_BAD_PROFILE          7
1577 #define MBXERR_BAD_DEF_CLASS        8
1578 #define MBXERR_BAD_MAX_RESPONDER    9
1579 #define MBXERR_BAD_MAX_ORIGINATOR   10
1580 #define MBXERR_RPI_REGISTERED       11
1581 #define MBXERR_RPI_FULL             12
1582 #define MBXERR_NO_RESOURCES         13
1583 #define MBXERR_BAD_RCV_LENGTH       14
1584 #define MBXERR_DMA_ERROR            15
1585 #define MBXERR_ERROR                16
1586 #define MBXERR_LINK_DOWN            0x33
1587 #define MBXERR_SEC_NO_PERMISSION    0xF02
1588 #define MBX_NOT_FINISHED            255
1589 
1590 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
1591 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
1592 
1593 #define TEMPERATURE_OFFSET 0xB0	/* Slim offset for critical temperature event */
1594 
1595 /*
1596  *    Begin Structure Definitions for Mailbox Commands
1597  */
1598 
1599 typedef struct {
1600 #ifdef __BIG_ENDIAN_BITFIELD
1601 	uint8_t tval;
1602 	uint8_t tmask;
1603 	uint8_t rval;
1604 	uint8_t rmask;
1605 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1606 	uint8_t rmask;
1607 	uint8_t rval;
1608 	uint8_t tmask;
1609 	uint8_t tval;
1610 #endif
1611 } RR_REG;
1612 
1613 struct ulp_bde {
1614 	uint32_t bdeAddress;
1615 #ifdef __BIG_ENDIAN_BITFIELD
1616 	uint32_t bdeReserved:4;
1617 	uint32_t bdeAddrHigh:4;
1618 	uint32_t bdeSize:24;
1619 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1620 	uint32_t bdeSize:24;
1621 	uint32_t bdeAddrHigh:4;
1622 	uint32_t bdeReserved:4;
1623 #endif
1624 };
1625 
1626 typedef struct ULP_BDL {	/* SLI-2 */
1627 #ifdef __BIG_ENDIAN_BITFIELD
1628 	uint32_t bdeFlags:8;	/* BDL Flags */
1629 	uint32_t bdeSize:24;	/* Size of BDL array in host memory (bytes) */
1630 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1631 	uint32_t bdeSize:24;	/* Size of BDL array in host memory (bytes) */
1632 	uint32_t bdeFlags:8;	/* BDL Flags */
1633 #endif
1634 
1635 	uint32_t addrLow;	/* Address 0:31 */
1636 	uint32_t addrHigh;	/* Address 32:63 */
1637 	uint32_t ulpIoTag32;	/* Can be used for 32 bit I/O Tag */
1638 } ULP_BDL;
1639 
1640 /*
1641  * BlockGuard Definitions
1642  */
1643 
1644 enum lpfc_protgrp_type {
1645 	LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors                  */
1646 	LPFC_PG_TYPE_NO_DIF,	  /* no DIF data pointed to by prot grp       */
1647 	LPFC_PG_TYPE_EMBD_DIF,	  /* DIF is embedded (inline) with data       */
1648 	LPFC_PG_TYPE_DIF_BUF	  /* DIF has its own scatter/gather list      */
1649 };
1650 
1651 /* PDE Descriptors */
1652 #define LPFC_PDE5_DESCRIPTOR		0x85
1653 #define LPFC_PDE6_DESCRIPTOR		0x86
1654 #define LPFC_PDE7_DESCRIPTOR		0x87
1655 
1656 /* BlockGuard Opcodes */
1657 #define BG_OP_IN_NODIF_OUT_CRC		0x0
1658 #define	BG_OP_IN_CRC_OUT_NODIF		0x1
1659 #define	BG_OP_IN_NODIF_OUT_CSUM		0x2
1660 #define	BG_OP_IN_CSUM_OUT_NODIF		0x3
1661 #define	BG_OP_IN_CRC_OUT_CRC		0x4
1662 #define	BG_OP_IN_CSUM_OUT_CSUM		0x5
1663 #define	BG_OP_IN_CRC_OUT_CSUM		0x6
1664 #define	BG_OP_IN_CSUM_OUT_CRC		0x7
1665 
1666 struct lpfc_pde5 {
1667 	uint32_t word0;
1668 #define pde5_type_SHIFT		24
1669 #define pde5_type_MASK		0x000000ff
1670 #define pde5_type_WORD		word0
1671 #define pde5_rsvd0_SHIFT	0
1672 #define pde5_rsvd0_MASK		0x00ffffff
1673 #define pde5_rsvd0_WORD		word0
1674 	uint32_t reftag;	/* Reference Tag Value			*/
1675 	uint32_t reftagtr;	/* Reference Tag Translation Value 	*/
1676 };
1677 
1678 struct lpfc_pde6 {
1679 	uint32_t word0;
1680 #define pde6_type_SHIFT		24
1681 #define pde6_type_MASK		0x000000ff
1682 #define pde6_type_WORD		word0
1683 #define pde6_rsvd0_SHIFT	0
1684 #define pde6_rsvd0_MASK		0x00ffffff
1685 #define pde6_rsvd0_WORD		word0
1686 	uint32_t word1;
1687 #define pde6_rsvd1_SHIFT	26
1688 #define pde6_rsvd1_MASK		0x0000003f
1689 #define pde6_rsvd1_WORD		word1
1690 #define pde6_na_SHIFT		25
1691 #define pde6_na_MASK		0x00000001
1692 #define pde6_na_WORD		word1
1693 #define pde6_rsvd2_SHIFT	16
1694 #define pde6_rsvd2_MASK		0x000001FF
1695 #define pde6_rsvd2_WORD		word1
1696 #define pde6_apptagtr_SHIFT	0
1697 #define pde6_apptagtr_MASK	0x0000ffff
1698 #define pde6_apptagtr_WORD	word1
1699 	uint32_t word2;
1700 #define pde6_optx_SHIFT		28
1701 #define pde6_optx_MASK		0x0000000f
1702 #define pde6_optx_WORD		word2
1703 #define pde6_oprx_SHIFT		24
1704 #define pde6_oprx_MASK		0x0000000f
1705 #define pde6_oprx_WORD		word2
1706 #define pde6_nr_SHIFT		23
1707 #define pde6_nr_MASK		0x00000001
1708 #define pde6_nr_WORD		word2
1709 #define pde6_ce_SHIFT		22
1710 #define pde6_ce_MASK		0x00000001
1711 #define pde6_ce_WORD		word2
1712 #define pde6_re_SHIFT		21
1713 #define pde6_re_MASK		0x00000001
1714 #define pde6_re_WORD		word2
1715 #define pde6_ae_SHIFT		20
1716 #define pde6_ae_MASK		0x00000001
1717 #define pde6_ae_WORD		word2
1718 #define pde6_ai_SHIFT		19
1719 #define pde6_ai_MASK		0x00000001
1720 #define pde6_ai_WORD		word2
1721 #define pde6_bs_SHIFT		16
1722 #define pde6_bs_MASK		0x00000007
1723 #define pde6_bs_WORD		word2
1724 #define pde6_apptagval_SHIFT	0
1725 #define pde6_apptagval_MASK	0x0000ffff
1726 #define pde6_apptagval_WORD	word2
1727 };
1728 
1729 struct lpfc_pde7 {
1730 	uint32_t word0;
1731 #define pde7_type_SHIFT		24
1732 #define pde7_type_MASK		0x000000ff
1733 #define pde7_type_WORD		word0
1734 #define pde7_rsvd0_SHIFT	0
1735 #define pde7_rsvd0_MASK		0x00ffffff
1736 #define pde7_rsvd0_WORD		word0
1737 	uint32_t addrHigh;
1738 	uint32_t addrLow;
1739 };
1740 
1741 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1742 
1743 typedef struct {
1744 #ifdef __BIG_ENDIAN_BITFIELD
1745 	uint32_t rsvd2:25;
1746 	uint32_t acknowledgment:1;
1747 	uint32_t version:1;
1748 	uint32_t erase_or_prog:1;
1749 	uint32_t update_flash:1;
1750 	uint32_t update_ram:1;
1751 	uint32_t method:1;
1752 	uint32_t load_cmplt:1;
1753 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1754 	uint32_t load_cmplt:1;
1755 	uint32_t method:1;
1756 	uint32_t update_ram:1;
1757 	uint32_t update_flash:1;
1758 	uint32_t erase_or_prog:1;
1759 	uint32_t version:1;
1760 	uint32_t acknowledgment:1;
1761 	uint32_t rsvd2:25;
1762 #endif
1763 
1764 	uint32_t dl_to_adr_low;
1765 	uint32_t dl_to_adr_high;
1766 	uint32_t dl_len;
1767 	union {
1768 		uint32_t dl_from_mbx_offset;
1769 		struct ulp_bde dl_from_bde;
1770 		struct ulp_bde64 dl_from_bde64;
1771 	} un;
1772 
1773 } LOAD_SM_VAR;
1774 
1775 /* Structure for MB Command READ_NVPARM (02) */
1776 
1777 typedef struct {
1778 	uint32_t rsvd1[3];	/* Read as all one's */
1779 	uint32_t rsvd2;		/* Read as all zero's */
1780 	uint32_t portname[2];	/* N_PORT name */
1781 	uint32_t nodename[2];	/* NODE name */
1782 
1783 #ifdef __BIG_ENDIAN_BITFIELD
1784 	uint32_t pref_DID:24;
1785 	uint32_t hardAL_PA:8;
1786 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1787 	uint32_t hardAL_PA:8;
1788 	uint32_t pref_DID:24;
1789 #endif
1790 
1791 	uint32_t rsvd3[21];	/* Read as all one's */
1792 } READ_NV_VAR;
1793 
1794 /* Structure for MB Command WRITE_NVPARMS (03) */
1795 
1796 typedef struct {
1797 	uint32_t rsvd1[3];	/* Must be all one's */
1798 	uint32_t rsvd2;		/* Must be all zero's */
1799 	uint32_t portname[2];	/* N_PORT name */
1800 	uint32_t nodename[2];	/* NODE name */
1801 
1802 #ifdef __BIG_ENDIAN_BITFIELD
1803 	uint32_t pref_DID:24;
1804 	uint32_t hardAL_PA:8;
1805 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1806 	uint32_t hardAL_PA:8;
1807 	uint32_t pref_DID:24;
1808 #endif
1809 
1810 	uint32_t rsvd3[21];	/* Must be all one's */
1811 } WRITE_NV_VAR;
1812 
1813 /* Structure for MB Command RUN_BIU_DIAG (04) */
1814 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1815 
1816 typedef struct {
1817 	uint32_t rsvd1;
1818 	union {
1819 		struct {
1820 			struct ulp_bde xmit_bde;
1821 			struct ulp_bde rcv_bde;
1822 		} s1;
1823 		struct {
1824 			struct ulp_bde64 xmit_bde64;
1825 			struct ulp_bde64 rcv_bde64;
1826 		} s2;
1827 	} un;
1828 } BIU_DIAG_VAR;
1829 
1830 /* Structure for MB command READ_EVENT_LOG (0x38) */
1831 struct READ_EVENT_LOG_VAR {
1832 	uint32_t word1;
1833 #define lpfc_event_log_SHIFT	29
1834 #define lpfc_event_log_MASK	0x00000001
1835 #define lpfc_event_log_WORD	word1
1836 #define USE_MAILBOX_RESPONSE	1
1837 	uint32_t offset;
1838 	struct ulp_bde64 rcv_bde64;
1839 };
1840 
1841 /* Structure for MB Command INIT_LINK (05) */
1842 
1843 typedef struct {
1844 #ifdef __BIG_ENDIAN_BITFIELD
1845 	uint32_t rsvd1:24;
1846 	uint32_t lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective Reset to */
1847 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1848 	uint32_t lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective Reset to */
1849 	uint32_t rsvd1:24;
1850 #endif
1851 
1852 #ifdef __BIG_ENDIAN_BITFIELD
1853 	uint8_t fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
1854 	uint8_t rsvd2;
1855 	uint16_t link_flags;
1856 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1857 	uint16_t link_flags;
1858 	uint8_t rsvd2;
1859 	uint8_t fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
1860 #endif
1861 
1862 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
1863 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
1864 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
1865 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
1866 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
1867 #define	FLAGS_UNREG_LOGIN_ALL	     0x08 /* UNREG_LOGIN all on link down */
1868 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
1869 
1870 #define FLAGS_TOPOLOGY_FAILOVER      0x0400	/* Bit 10 */
1871 #define FLAGS_LINK_SPEED             0x0800	/* Bit 11 */
1872 #define FLAGS_IMED_ABORT             0x04000	/* Bit 14 */
1873 
1874 	uint32_t link_speed;
1875 #define LINK_SPEED_AUTO 0x0     /* Auto selection */
1876 #define LINK_SPEED_1G   0x1     /* 1 Gigabaud */
1877 #define LINK_SPEED_2G   0x2     /* 2 Gigabaud */
1878 #define LINK_SPEED_4G   0x4     /* 4 Gigabaud */
1879 #define LINK_SPEED_8G   0x8     /* 8 Gigabaud */
1880 #define LINK_SPEED_10G  0x10    /* 10 Gigabaud */
1881 #define LINK_SPEED_16G  0x11    /* 16 Gigabaud */
1882 
1883 } INIT_LINK_VAR;
1884 
1885 /* Structure for MB Command DOWN_LINK (06) */
1886 
1887 typedef struct {
1888 	uint32_t rsvd1;
1889 } DOWN_LINK_VAR;
1890 
1891 /* Structure for MB Command CONFIG_LINK (07) */
1892 
1893 typedef struct {
1894 #ifdef __BIG_ENDIAN_BITFIELD
1895 	uint32_t cr:1;
1896 	uint32_t ci:1;
1897 	uint32_t cr_delay:6;
1898 	uint32_t cr_count:8;
1899 	uint32_t rsvd1:8;
1900 	uint32_t MaxBBC:8;
1901 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1902 	uint32_t MaxBBC:8;
1903 	uint32_t rsvd1:8;
1904 	uint32_t cr_count:8;
1905 	uint32_t cr_delay:6;
1906 	uint32_t ci:1;
1907 	uint32_t cr:1;
1908 #endif
1909 
1910 	uint32_t myId;
1911 	uint32_t rsvd2;
1912 	uint32_t edtov;
1913 	uint32_t arbtov;
1914 	uint32_t ratov;
1915 	uint32_t rttov;
1916 	uint32_t altov;
1917 	uint32_t crtov;
1918 	uint32_t citov;
1919 #ifdef __BIG_ENDIAN_BITFIELD
1920 	uint32_t rrq_enable:1;
1921 	uint32_t rrq_immed:1;
1922 	uint32_t rsvd4:29;
1923 	uint32_t ack0_enable:1;
1924 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1925 	uint32_t ack0_enable:1;
1926 	uint32_t rsvd4:29;
1927 	uint32_t rrq_immed:1;
1928 	uint32_t rrq_enable:1;
1929 #endif
1930 } CONFIG_LINK;
1931 
1932 /* Structure for MB Command PART_SLIM (08)
1933  * will be removed since SLI1 is no longer supported!
1934  */
1935 typedef struct {
1936 #ifdef __BIG_ENDIAN_BITFIELD
1937 	uint16_t offCiocb;
1938 	uint16_t numCiocb;
1939 	uint16_t offRiocb;
1940 	uint16_t numRiocb;
1941 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1942 	uint16_t numCiocb;
1943 	uint16_t offCiocb;
1944 	uint16_t numRiocb;
1945 	uint16_t offRiocb;
1946 #endif
1947 } RING_DEF;
1948 
1949 typedef struct {
1950 #ifdef __BIG_ENDIAN_BITFIELD
1951 	uint32_t unused1:24;
1952 	uint32_t numRing:8;
1953 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1954 	uint32_t numRing:8;
1955 	uint32_t unused1:24;
1956 #endif
1957 
1958 	RING_DEF ringdef[4];
1959 	uint32_t hbainit;
1960 } PART_SLIM_VAR;
1961 
1962 /* Structure for MB Command CONFIG_RING (09) */
1963 
1964 typedef struct {
1965 #ifdef __BIG_ENDIAN_BITFIELD
1966 	uint32_t unused2:6;
1967 	uint32_t recvSeq:1;
1968 	uint32_t recvNotify:1;
1969 	uint32_t numMask:8;
1970 	uint32_t profile:8;
1971 	uint32_t unused1:4;
1972 	uint32_t ring:4;
1973 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1974 	uint32_t ring:4;
1975 	uint32_t unused1:4;
1976 	uint32_t profile:8;
1977 	uint32_t numMask:8;
1978 	uint32_t recvNotify:1;
1979 	uint32_t recvSeq:1;
1980 	uint32_t unused2:6;
1981 #endif
1982 
1983 #ifdef __BIG_ENDIAN_BITFIELD
1984 	uint16_t maxRespXchg;
1985 	uint16_t maxOrigXchg;
1986 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1987 	uint16_t maxOrigXchg;
1988 	uint16_t maxRespXchg;
1989 #endif
1990 
1991 	RR_REG rrRegs[6];
1992 } CONFIG_RING_VAR;
1993 
1994 /* Structure for MB Command RESET_RING (10) */
1995 
1996 typedef struct {
1997 	uint32_t ring_no;
1998 } RESET_RING_VAR;
1999 
2000 /* Structure for MB Command READ_CONFIG (11) */
2001 
2002 typedef struct {
2003 #ifdef __BIG_ENDIAN_BITFIELD
2004 	uint32_t cr:1;
2005 	uint32_t ci:1;
2006 	uint32_t cr_delay:6;
2007 	uint32_t cr_count:8;
2008 	uint32_t InitBBC:8;
2009 	uint32_t MaxBBC:8;
2010 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2011 	uint32_t MaxBBC:8;
2012 	uint32_t InitBBC:8;
2013 	uint32_t cr_count:8;
2014 	uint32_t cr_delay:6;
2015 	uint32_t ci:1;
2016 	uint32_t cr:1;
2017 #endif
2018 
2019 #ifdef __BIG_ENDIAN_BITFIELD
2020 	uint32_t topology:8;
2021 	uint32_t myDid:24;
2022 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2023 	uint32_t myDid:24;
2024 	uint32_t topology:8;
2025 #endif
2026 
2027 	/* Defines for topology (defined previously) */
2028 #ifdef __BIG_ENDIAN_BITFIELD
2029 	uint32_t AR:1;
2030 	uint32_t IR:1;
2031 	uint32_t rsvd1:29;
2032 	uint32_t ack0:1;
2033 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2034 	uint32_t ack0:1;
2035 	uint32_t rsvd1:29;
2036 	uint32_t IR:1;
2037 	uint32_t AR:1;
2038 #endif
2039 
2040 	uint32_t edtov;
2041 	uint32_t arbtov;
2042 	uint32_t ratov;
2043 	uint32_t rttov;
2044 	uint32_t altov;
2045 	uint32_t lmt;
2046 #define LMT_RESERVED  0x000    /* Not used */
2047 #define LMT_1Gb       0x004
2048 #define LMT_2Gb       0x008
2049 #define LMT_4Gb       0x040
2050 #define LMT_8Gb       0x080
2051 #define LMT_10Gb      0x100
2052 #define LMT_16Gb      0x200
2053 	uint32_t rsvd2;
2054 	uint32_t rsvd3;
2055 	uint32_t max_xri;
2056 	uint32_t max_iocb;
2057 	uint32_t max_rpi;
2058 	uint32_t avail_xri;
2059 	uint32_t avail_iocb;
2060 	uint32_t avail_rpi;
2061 	uint32_t max_vpi;
2062 	uint32_t rsvd4;
2063 	uint32_t rsvd5;
2064 	uint32_t avail_vpi;
2065 } READ_CONFIG_VAR;
2066 
2067 /* Structure for MB Command READ_RCONFIG (12) */
2068 
2069 typedef struct {
2070 #ifdef __BIG_ENDIAN_BITFIELD
2071 	uint32_t rsvd2:7;
2072 	uint32_t recvNotify:1;
2073 	uint32_t numMask:8;
2074 	uint32_t profile:8;
2075 	uint32_t rsvd1:4;
2076 	uint32_t ring:4;
2077 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2078 	uint32_t ring:4;
2079 	uint32_t rsvd1:4;
2080 	uint32_t profile:8;
2081 	uint32_t numMask:8;
2082 	uint32_t recvNotify:1;
2083 	uint32_t rsvd2:7;
2084 #endif
2085 
2086 #ifdef __BIG_ENDIAN_BITFIELD
2087 	uint16_t maxResp;
2088 	uint16_t maxOrig;
2089 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2090 	uint16_t maxOrig;
2091 	uint16_t maxResp;
2092 #endif
2093 
2094 	RR_REG rrRegs[6];
2095 
2096 #ifdef __BIG_ENDIAN_BITFIELD
2097 	uint16_t cmdRingOffset;
2098 	uint16_t cmdEntryCnt;
2099 	uint16_t rspRingOffset;
2100 	uint16_t rspEntryCnt;
2101 	uint16_t nextCmdOffset;
2102 	uint16_t rsvd3;
2103 	uint16_t nextRspOffset;
2104 	uint16_t rsvd4;
2105 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2106 	uint16_t cmdEntryCnt;
2107 	uint16_t cmdRingOffset;
2108 	uint16_t rspEntryCnt;
2109 	uint16_t rspRingOffset;
2110 	uint16_t rsvd3;
2111 	uint16_t nextCmdOffset;
2112 	uint16_t rsvd4;
2113 	uint16_t nextRspOffset;
2114 #endif
2115 } READ_RCONF_VAR;
2116 
2117 /* Structure for MB Command READ_SPARM (13) */
2118 /* Structure for MB Command READ_SPARM64 (0x8D) */
2119 
2120 typedef struct {
2121 	uint32_t rsvd1;
2122 	uint32_t rsvd2;
2123 	union {
2124 		struct ulp_bde sp; /* This BDE points to struct serv_parm
2125 				      structure */
2126 		struct ulp_bde64 sp64;
2127 	} un;
2128 #ifdef __BIG_ENDIAN_BITFIELD
2129 	uint16_t rsvd3;
2130 	uint16_t vpi;
2131 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2132 	uint16_t vpi;
2133 	uint16_t rsvd3;
2134 #endif
2135 } READ_SPARM_VAR;
2136 
2137 /* Structure for MB Command READ_STATUS (14) */
2138 
2139 typedef struct {
2140 #ifdef __BIG_ENDIAN_BITFIELD
2141 	uint32_t rsvd1:31;
2142 	uint32_t clrCounters:1;
2143 	uint16_t activeXriCnt;
2144 	uint16_t activeRpiCnt;
2145 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2146 	uint32_t clrCounters:1;
2147 	uint32_t rsvd1:31;
2148 	uint16_t activeRpiCnt;
2149 	uint16_t activeXriCnt;
2150 #endif
2151 
2152 	uint32_t xmitByteCnt;
2153 	uint32_t rcvByteCnt;
2154 	uint32_t xmitFrameCnt;
2155 	uint32_t rcvFrameCnt;
2156 	uint32_t xmitSeqCnt;
2157 	uint32_t rcvSeqCnt;
2158 	uint32_t totalOrigExchanges;
2159 	uint32_t totalRespExchanges;
2160 	uint32_t rcvPbsyCnt;
2161 	uint32_t rcvFbsyCnt;
2162 } READ_STATUS_VAR;
2163 
2164 /* Structure for MB Command READ_RPI (15) */
2165 /* Structure for MB Command READ_RPI64 (0x8F) */
2166 
2167 typedef struct {
2168 #ifdef __BIG_ENDIAN_BITFIELD
2169 	uint16_t nextRpi;
2170 	uint16_t reqRpi;
2171 	uint32_t rsvd2:8;
2172 	uint32_t DID:24;
2173 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2174 	uint16_t reqRpi;
2175 	uint16_t nextRpi;
2176 	uint32_t DID:24;
2177 	uint32_t rsvd2:8;
2178 #endif
2179 
2180 	union {
2181 		struct ulp_bde sp;
2182 		struct ulp_bde64 sp64;
2183 	} un;
2184 
2185 } READ_RPI_VAR;
2186 
2187 /* Structure for MB Command READ_XRI (16) */
2188 
2189 typedef struct {
2190 #ifdef __BIG_ENDIAN_BITFIELD
2191 	uint16_t nextXri;
2192 	uint16_t reqXri;
2193 	uint16_t rsvd1;
2194 	uint16_t rpi;
2195 	uint32_t rsvd2:8;
2196 	uint32_t DID:24;
2197 	uint32_t rsvd3:8;
2198 	uint32_t SID:24;
2199 	uint32_t rsvd4;
2200 	uint8_t seqId;
2201 	uint8_t rsvd5;
2202 	uint16_t seqCount;
2203 	uint16_t oxId;
2204 	uint16_t rxId;
2205 	uint32_t rsvd6:30;
2206 	uint32_t si:1;
2207 	uint32_t exchOrig:1;
2208 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2209 	uint16_t reqXri;
2210 	uint16_t nextXri;
2211 	uint16_t rpi;
2212 	uint16_t rsvd1;
2213 	uint32_t DID:24;
2214 	uint32_t rsvd2:8;
2215 	uint32_t SID:24;
2216 	uint32_t rsvd3:8;
2217 	uint32_t rsvd4;
2218 	uint16_t seqCount;
2219 	uint8_t rsvd5;
2220 	uint8_t seqId;
2221 	uint16_t rxId;
2222 	uint16_t oxId;
2223 	uint32_t exchOrig:1;
2224 	uint32_t si:1;
2225 	uint32_t rsvd6:30;
2226 #endif
2227 } READ_XRI_VAR;
2228 
2229 /* Structure for MB Command READ_REV (17) */
2230 
2231 typedef struct {
2232 #ifdef __BIG_ENDIAN_BITFIELD
2233 	uint32_t cv:1;
2234 	uint32_t rr:1;
2235 	uint32_t rsvd2:2;
2236 	uint32_t v3req:1;
2237 	uint32_t v3rsp:1;
2238 	uint32_t rsvd1:25;
2239 	uint32_t rv:1;
2240 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2241 	uint32_t rv:1;
2242 	uint32_t rsvd1:25;
2243 	uint32_t v3rsp:1;
2244 	uint32_t v3req:1;
2245 	uint32_t rsvd2:2;
2246 	uint32_t rr:1;
2247 	uint32_t cv:1;
2248 #endif
2249 
2250 	uint32_t biuRev;
2251 	uint32_t smRev;
2252 	union {
2253 		uint32_t smFwRev;
2254 		struct {
2255 #ifdef __BIG_ENDIAN_BITFIELD
2256 			uint8_t ProgType;
2257 			uint8_t ProgId;
2258 			uint16_t ProgVer:4;
2259 			uint16_t ProgRev:4;
2260 			uint16_t ProgFixLvl:2;
2261 			uint16_t ProgDistType:2;
2262 			uint16_t DistCnt:4;
2263 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2264 			uint16_t DistCnt:4;
2265 			uint16_t ProgDistType:2;
2266 			uint16_t ProgFixLvl:2;
2267 			uint16_t ProgRev:4;
2268 			uint16_t ProgVer:4;
2269 			uint8_t ProgId;
2270 			uint8_t ProgType;
2271 #endif
2272 
2273 		} b;
2274 	} un;
2275 	uint32_t endecRev;
2276 #ifdef __BIG_ENDIAN_BITFIELD
2277 	uint8_t feaLevelHigh;
2278 	uint8_t feaLevelLow;
2279 	uint8_t fcphHigh;
2280 	uint8_t fcphLow;
2281 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2282 	uint8_t fcphLow;
2283 	uint8_t fcphHigh;
2284 	uint8_t feaLevelLow;
2285 	uint8_t feaLevelHigh;
2286 #endif
2287 
2288 	uint32_t postKernRev;
2289 	uint32_t opFwRev;
2290 	uint8_t opFwName[16];
2291 	uint32_t sli1FwRev;
2292 	uint8_t sli1FwName[16];
2293 	uint32_t sli2FwRev;
2294 	uint8_t sli2FwName[16];
2295 	uint32_t sli3Feat;
2296 	uint32_t RandomData[6];
2297 } READ_REV_VAR;
2298 
2299 /* Structure for MB Command READ_LINK_STAT (18) */
2300 
2301 typedef struct {
2302 	uint32_t rsvd1;
2303 	uint32_t linkFailureCnt;
2304 	uint32_t lossSyncCnt;
2305 
2306 	uint32_t lossSignalCnt;
2307 	uint32_t primSeqErrCnt;
2308 	uint32_t invalidXmitWord;
2309 	uint32_t crcCnt;
2310 	uint32_t primSeqTimeout;
2311 	uint32_t elasticOverrun;
2312 	uint32_t arbTimeout;
2313 } READ_LNK_VAR;
2314 
2315 /* Structure for MB Command REG_LOGIN (19) */
2316 /* Structure for MB Command REG_LOGIN64 (0x93) */
2317 
2318 typedef struct {
2319 #ifdef __BIG_ENDIAN_BITFIELD
2320 	uint16_t rsvd1;
2321 	uint16_t rpi;
2322 	uint32_t rsvd2:8;
2323 	uint32_t did:24;
2324 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2325 	uint16_t rpi;
2326 	uint16_t rsvd1;
2327 	uint32_t did:24;
2328 	uint32_t rsvd2:8;
2329 #endif
2330 
2331 	union {
2332 		struct ulp_bde sp;
2333 		struct ulp_bde64 sp64;
2334 	} un;
2335 
2336 #ifdef __BIG_ENDIAN_BITFIELD
2337 	uint16_t rsvd6;
2338 	uint16_t vpi;
2339 #else /* __LITTLE_ENDIAN_BITFIELD */
2340 	uint16_t vpi;
2341 	uint16_t rsvd6;
2342 #endif
2343 
2344 } REG_LOGIN_VAR;
2345 
2346 /* Word 30 contents for REG_LOGIN */
2347 typedef union {
2348 	struct {
2349 #ifdef __BIG_ENDIAN_BITFIELD
2350 		uint16_t rsvd1:12;
2351 		uint16_t wd30_class:4;
2352 		uint16_t xri;
2353 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2354 		uint16_t xri;
2355 		uint16_t wd30_class:4;
2356 		uint16_t rsvd1:12;
2357 #endif
2358 	} f;
2359 	uint32_t word;
2360 } REG_WD30;
2361 
2362 /* Structure for MB Command UNREG_LOGIN (20) */
2363 
2364 typedef struct {
2365 #ifdef __BIG_ENDIAN_BITFIELD
2366 	uint16_t rsvd1;
2367 	uint16_t rpi;
2368 	uint32_t rsvd2;
2369 	uint32_t rsvd3;
2370 	uint32_t rsvd4;
2371 	uint32_t rsvd5;
2372 	uint16_t rsvd6;
2373 	uint16_t vpi;
2374 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2375 	uint16_t rpi;
2376 	uint16_t rsvd1;
2377 	uint32_t rsvd2;
2378 	uint32_t rsvd3;
2379 	uint32_t rsvd4;
2380 	uint32_t rsvd5;
2381 	uint16_t vpi;
2382 	uint16_t rsvd6;
2383 #endif
2384 } UNREG_LOGIN_VAR;
2385 
2386 /* Structure for MB Command REG_VPI (0x96) */
2387 typedef struct {
2388 #ifdef __BIG_ENDIAN_BITFIELD
2389 	uint32_t rsvd1;
2390 	uint32_t rsvd2:7;
2391 	uint32_t upd:1;
2392 	uint32_t sid:24;
2393 	uint32_t wwn[2];
2394 	uint32_t rsvd5;
2395 	uint16_t vfi;
2396 	uint16_t vpi;
2397 #else	/*  __LITTLE_ENDIAN */
2398 	uint32_t rsvd1;
2399 	uint32_t sid:24;
2400 	uint32_t upd:1;
2401 	uint32_t rsvd2:7;
2402 	uint32_t wwn[2];
2403 	uint32_t rsvd5;
2404 	uint16_t vpi;
2405 	uint16_t vfi;
2406 #endif
2407 } REG_VPI_VAR;
2408 
2409 /* Structure for MB Command UNREG_VPI (0x97) */
2410 typedef struct {
2411 	uint32_t rsvd1;
2412 #ifdef __BIG_ENDIAN_BITFIELD
2413 	uint16_t rsvd2;
2414 	uint16_t sli4_vpi;
2415 #else	/*  __LITTLE_ENDIAN */
2416 	uint16_t sli4_vpi;
2417 	uint16_t rsvd2;
2418 #endif
2419 	uint32_t rsvd3;
2420 	uint32_t rsvd4;
2421 	uint32_t rsvd5;
2422 #ifdef __BIG_ENDIAN_BITFIELD
2423 	uint16_t rsvd6;
2424 	uint16_t vpi;
2425 #else	/*  __LITTLE_ENDIAN */
2426 	uint16_t vpi;
2427 	uint16_t rsvd6;
2428 #endif
2429 } UNREG_VPI_VAR;
2430 
2431 /* Structure for MB Command UNREG_D_ID (0x23) */
2432 
2433 typedef struct {
2434 	uint32_t did;
2435 	uint32_t rsvd2;
2436 	uint32_t rsvd3;
2437 	uint32_t rsvd4;
2438 	uint32_t rsvd5;
2439 #ifdef __BIG_ENDIAN_BITFIELD
2440 	uint16_t rsvd6;
2441 	uint16_t vpi;
2442 #else
2443 	uint16_t vpi;
2444 	uint16_t rsvd6;
2445 #endif
2446 } UNREG_D_ID_VAR;
2447 
2448 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2449 struct lpfc_mbx_read_top {
2450 	uint32_t eventTag;	/* Event tag */
2451 	uint32_t word2;
2452 #define lpfc_mbx_read_top_fa_SHIFT		12
2453 #define lpfc_mbx_read_top_fa_MASK		0x00000001
2454 #define lpfc_mbx_read_top_fa_WORD		word2
2455 #define lpfc_mbx_read_top_mm_SHIFT		11
2456 #define lpfc_mbx_read_top_mm_MASK		0x00000001
2457 #define lpfc_mbx_read_top_mm_WORD		word2
2458 #define lpfc_mbx_read_top_pb_SHIFT		9
2459 #define lpfc_mbx_read_top_pb_MASK		0X00000001
2460 #define lpfc_mbx_read_top_pb_WORD		word2
2461 #define lpfc_mbx_read_top_il_SHIFT		8
2462 #define lpfc_mbx_read_top_il_MASK		0x00000001
2463 #define lpfc_mbx_read_top_il_WORD		word2
2464 #define lpfc_mbx_read_top_att_type_SHIFT	0
2465 #define lpfc_mbx_read_top_att_type_MASK		0x000000FF
2466 #define lpfc_mbx_read_top_att_type_WORD		word2
2467 #define LPFC_ATT_RESERVED    0x00	/* Reserved - attType */
2468 #define LPFC_ATT_LINK_UP     0x01	/* Link is up */
2469 #define LPFC_ATT_LINK_DOWN   0x02	/* Link is down */
2470 	uint32_t word3;
2471 #define lpfc_mbx_read_top_alpa_granted_SHIFT	24
2472 #define lpfc_mbx_read_top_alpa_granted_MASK	0x000000FF
2473 #define lpfc_mbx_read_top_alpa_granted_WORD	word3
2474 #define lpfc_mbx_read_top_lip_alps_SHIFT	16
2475 #define lpfc_mbx_read_top_lip_alps_MASK		0x000000FF
2476 #define lpfc_mbx_read_top_lip_alps_WORD		word3
2477 #define lpfc_mbx_read_top_lip_type_SHIFT	8
2478 #define lpfc_mbx_read_top_lip_type_MASK		0x000000FF
2479 #define lpfc_mbx_read_top_lip_type_WORD		word3
2480 #define lpfc_mbx_read_top_topology_SHIFT	0
2481 #define lpfc_mbx_read_top_topology_MASK		0x000000FF
2482 #define lpfc_mbx_read_top_topology_WORD		word3
2483 #define LPFC_TOPOLOGY_PT_PT 0x01	/* Topology is pt-pt / pt-fabric */
2484 #define LPFC_TOPOLOGY_LOOP  0x02	/* Topology is FC-AL */
2485 #define LPFC_TOPOLOGY_MM    0x05	/* maint mode zephtr to menlo */
2486 	/* store the LILP AL_PA position map into */
2487 	struct ulp_bde64 lilpBde64;
2488 #define LPFC_ALPA_MAP_SIZE	128
2489 	uint32_t word7;
2490 #define lpfc_mbx_read_top_ld_lu_SHIFT		31
2491 #define lpfc_mbx_read_top_ld_lu_MASK		0x00000001
2492 #define lpfc_mbx_read_top_ld_lu_WORD		word7
2493 #define lpfc_mbx_read_top_ld_tf_SHIFT		30
2494 #define lpfc_mbx_read_top_ld_tf_MASK		0x00000001
2495 #define lpfc_mbx_read_top_ld_tf_WORD		word7
2496 #define lpfc_mbx_read_top_ld_link_spd_SHIFT	8
2497 #define lpfc_mbx_read_top_ld_link_spd_MASK	0x000000FF
2498 #define lpfc_mbx_read_top_ld_link_spd_WORD	word7
2499 #define lpfc_mbx_read_top_ld_nl_port_SHIFT	4
2500 #define lpfc_mbx_read_top_ld_nl_port_MASK	0x0000000F
2501 #define lpfc_mbx_read_top_ld_nl_port_WORD	word7
2502 #define lpfc_mbx_read_top_ld_tx_SHIFT		2
2503 #define lpfc_mbx_read_top_ld_tx_MASK		0x00000003
2504 #define lpfc_mbx_read_top_ld_tx_WORD		word7
2505 #define lpfc_mbx_read_top_ld_rx_SHIFT		0
2506 #define lpfc_mbx_read_top_ld_rx_MASK		0x00000003
2507 #define lpfc_mbx_read_top_ld_rx_WORD		word7
2508 	uint32_t word8;
2509 #define lpfc_mbx_read_top_lu_SHIFT		31
2510 #define lpfc_mbx_read_top_lu_MASK		0x00000001
2511 #define lpfc_mbx_read_top_lu_WORD		word8
2512 #define lpfc_mbx_read_top_tf_SHIFT		30
2513 #define lpfc_mbx_read_top_tf_MASK		0x00000001
2514 #define lpfc_mbx_read_top_tf_WORD		word8
2515 #define lpfc_mbx_read_top_link_spd_SHIFT	8
2516 #define lpfc_mbx_read_top_link_spd_MASK		0x000000FF
2517 #define lpfc_mbx_read_top_link_spd_WORD		word8
2518 #define lpfc_mbx_read_top_nl_port_SHIFT		4
2519 #define lpfc_mbx_read_top_nl_port_MASK		0x0000000F
2520 #define lpfc_mbx_read_top_nl_port_WORD		word8
2521 #define lpfc_mbx_read_top_tx_SHIFT		2
2522 #define lpfc_mbx_read_top_tx_MASK		0x00000003
2523 #define lpfc_mbx_read_top_tx_WORD		word8
2524 #define lpfc_mbx_read_top_rx_SHIFT		0
2525 #define lpfc_mbx_read_top_rx_MASK		0x00000003
2526 #define lpfc_mbx_read_top_rx_WORD		word8
2527 #define LPFC_LINK_SPEED_UNKNOWN	0x0
2528 #define LPFC_LINK_SPEED_1GHZ	0x04
2529 #define LPFC_LINK_SPEED_2GHZ	0x08
2530 #define LPFC_LINK_SPEED_4GHZ	0x10
2531 #define LPFC_LINK_SPEED_8GHZ	0x20
2532 #define LPFC_LINK_SPEED_10GHZ	0x40
2533 #define LPFC_LINK_SPEED_16GHZ	0x80
2534 };
2535 
2536 /* Structure for MB Command CLEAR_LA (22) */
2537 
2538 typedef struct {
2539 	uint32_t eventTag;	/* Event tag */
2540 	uint32_t rsvd1;
2541 } CLEAR_LA_VAR;
2542 
2543 /* Structure for MB Command DUMP */
2544 
2545 typedef struct {
2546 #ifdef __BIG_ENDIAN_BITFIELD
2547 	uint32_t rsvd:25;
2548 	uint32_t ra:1;
2549 	uint32_t co:1;
2550 	uint32_t cv:1;
2551 	uint32_t type:4;
2552 	uint32_t entry_index:16;
2553 	uint32_t region_id:16;
2554 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2555 	uint32_t type:4;
2556 	uint32_t cv:1;
2557 	uint32_t co:1;
2558 	uint32_t ra:1;
2559 	uint32_t rsvd:25;
2560 	uint32_t region_id:16;
2561 	uint32_t entry_index:16;
2562 #endif
2563 
2564 	uint32_t sli4_length;
2565 	uint32_t word_cnt;
2566 	uint32_t resp_offset;
2567 } DUMP_VAR;
2568 
2569 #define  DMP_MEM_REG             0x1
2570 #define  DMP_NV_PARAMS           0x2
2571 #define  DMP_LMSD                0x3 /* Link Module Serial Data */
2572 #define  DMP_WELL_KNOWN          0x4
2573 
2574 #define  DMP_REGION_VPD          0xe
2575 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
2576 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
2577 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
2578 
2579 #define  DMP_REGION_VPORT	 0x16   /* VPort info region */
2580 #define  DMP_VPORT_REGION_SIZE	 0x200
2581 #define  DMP_MBOX_OFFSET_WORD	 0x5
2582 
2583 #define  DMP_REGION_23		 0x17   /* fcoe param  and port state region */
2584 #define  DMP_RGN23_SIZE		 0x400
2585 
2586 #define  WAKE_UP_PARMS_REGION_ID    4
2587 #define  WAKE_UP_PARMS_WORD_SIZE   15
2588 
2589 struct vport_rec {
2590 	uint8_t wwpn[8];
2591 	uint8_t wwnn[8];
2592 };
2593 
2594 #define VPORT_INFO_SIG 0x32324752
2595 #define VPORT_INFO_REV_MASK 0xff
2596 #define VPORT_INFO_REV 0x1
2597 #define MAX_STATIC_VPORT_COUNT 16
2598 struct static_vport_info {
2599 	uint32_t		signature;
2600 	uint32_t		rev;
2601 	struct vport_rec	vport_list[MAX_STATIC_VPORT_COUNT];
2602 	uint32_t		resvd[66];
2603 };
2604 
2605 /* Option rom version structure */
2606 struct prog_id {
2607 #ifdef __BIG_ENDIAN_BITFIELD
2608 	uint8_t  type;
2609 	uint8_t  id;
2610 	uint32_t ver:4;  /* Major Version */
2611 	uint32_t rev:4;  /* Revision */
2612 	uint32_t lev:2;  /* Level */
2613 	uint32_t dist:2; /* Dist Type */
2614 	uint32_t num:4;  /* number after dist type */
2615 #else /*  __LITTLE_ENDIAN_BITFIELD */
2616 	uint32_t num:4;  /* number after dist type */
2617 	uint32_t dist:2; /* Dist Type */
2618 	uint32_t lev:2;  /* Level */
2619 	uint32_t rev:4;  /* Revision */
2620 	uint32_t ver:4;  /* Major Version */
2621 	uint8_t  id;
2622 	uint8_t  type;
2623 #endif
2624 };
2625 
2626 /* Structure for MB Command UPDATE_CFG (0x1B) */
2627 
2628 struct update_cfg_var {
2629 #ifdef __BIG_ENDIAN_BITFIELD
2630 	uint32_t rsvd2:16;
2631 	uint32_t type:8;
2632 	uint32_t rsvd:1;
2633 	uint32_t ra:1;
2634 	uint32_t co:1;
2635 	uint32_t cv:1;
2636 	uint32_t req:4;
2637 	uint32_t entry_length:16;
2638 	uint32_t region_id:16;
2639 #else  /*  __LITTLE_ENDIAN_BITFIELD */
2640 	uint32_t req:4;
2641 	uint32_t cv:1;
2642 	uint32_t co:1;
2643 	uint32_t ra:1;
2644 	uint32_t rsvd:1;
2645 	uint32_t type:8;
2646 	uint32_t rsvd2:16;
2647 	uint32_t region_id:16;
2648 	uint32_t entry_length:16;
2649 #endif
2650 
2651 	uint32_t resp_info;
2652 	uint32_t byte_cnt;
2653 	uint32_t data_offset;
2654 };
2655 
2656 struct hbq_mask {
2657 #ifdef __BIG_ENDIAN_BITFIELD
2658 	uint8_t tmatch;
2659 	uint8_t tmask;
2660 	uint8_t rctlmatch;
2661 	uint8_t rctlmask;
2662 #else	/*  __LITTLE_ENDIAN */
2663 	uint8_t rctlmask;
2664 	uint8_t rctlmatch;
2665 	uint8_t tmask;
2666 	uint8_t tmatch;
2667 #endif
2668 };
2669 
2670 
2671 /* Structure for MB Command CONFIG_HBQ (7c) */
2672 
2673 struct config_hbq_var {
2674 #ifdef __BIG_ENDIAN_BITFIELD
2675 	uint32_t rsvd1      :7;
2676 	uint32_t recvNotify :1;     /* Receive Notification */
2677 	uint32_t numMask    :8;     /* # Mask Entries       */
2678 	uint32_t profile    :8;     /* Selection Profile    */
2679 	uint32_t rsvd2      :8;
2680 #else	/*  __LITTLE_ENDIAN */
2681 	uint32_t rsvd2      :8;
2682 	uint32_t profile    :8;     /* Selection Profile    */
2683 	uint32_t numMask    :8;     /* # Mask Entries       */
2684 	uint32_t recvNotify :1;     /* Receive Notification */
2685 	uint32_t rsvd1      :7;
2686 #endif
2687 
2688 #ifdef __BIG_ENDIAN_BITFIELD
2689 	uint32_t hbqId      :16;
2690 	uint32_t rsvd3      :12;
2691 	uint32_t ringMask   :4;
2692 #else	/*  __LITTLE_ENDIAN */
2693 	uint32_t ringMask   :4;
2694 	uint32_t rsvd3      :12;
2695 	uint32_t hbqId      :16;
2696 #endif
2697 
2698 #ifdef __BIG_ENDIAN_BITFIELD
2699 	uint32_t entry_count :16;
2700 	uint32_t rsvd4        :8;
2701 	uint32_t headerLen    :8;
2702 #else	/*  __LITTLE_ENDIAN */
2703 	uint32_t headerLen    :8;
2704 	uint32_t rsvd4        :8;
2705 	uint32_t entry_count :16;
2706 #endif
2707 
2708 	uint32_t hbqaddrLow;
2709 	uint32_t hbqaddrHigh;
2710 
2711 #ifdef __BIG_ENDIAN_BITFIELD
2712 	uint32_t rsvd5      :31;
2713 	uint32_t logEntry   :1;
2714 #else	/*  __LITTLE_ENDIAN */
2715 	uint32_t logEntry   :1;
2716 	uint32_t rsvd5      :31;
2717 #endif
2718 
2719 	uint32_t rsvd6;    /* w7 */
2720 	uint32_t rsvd7;    /* w8 */
2721 	uint32_t rsvd8;    /* w9 */
2722 
2723 	struct hbq_mask hbqMasks[6];
2724 
2725 
2726 	union {
2727 		uint32_t allprofiles[12];
2728 
2729 		struct {
2730 			#ifdef __BIG_ENDIAN_BITFIELD
2731 				uint32_t	seqlenoff	:16;
2732 				uint32_t	maxlen		:16;
2733 			#else	/*  __LITTLE_ENDIAN */
2734 				uint32_t	maxlen		:16;
2735 				uint32_t	seqlenoff	:16;
2736 			#endif
2737 			#ifdef __BIG_ENDIAN_BITFIELD
2738 				uint32_t	rsvd1		:28;
2739 				uint32_t	seqlenbcnt	:4;
2740 			#else	/*  __LITTLE_ENDIAN */
2741 				uint32_t	seqlenbcnt	:4;
2742 				uint32_t	rsvd1		:28;
2743 			#endif
2744 			uint32_t rsvd[10];
2745 		} profile2;
2746 
2747 		struct {
2748 			#ifdef __BIG_ENDIAN_BITFIELD
2749 				uint32_t	seqlenoff	:16;
2750 				uint32_t	maxlen		:16;
2751 			#else	/*  __LITTLE_ENDIAN */
2752 				uint32_t	maxlen		:16;
2753 				uint32_t	seqlenoff	:16;
2754 			#endif
2755 			#ifdef __BIG_ENDIAN_BITFIELD
2756 				uint32_t	cmdcodeoff	:28;
2757 				uint32_t	rsvd1		:12;
2758 				uint32_t	seqlenbcnt	:4;
2759 			#else	/*  __LITTLE_ENDIAN */
2760 				uint32_t	seqlenbcnt	:4;
2761 				uint32_t	rsvd1		:12;
2762 				uint32_t	cmdcodeoff	:28;
2763 			#endif
2764 			uint32_t cmdmatch[8];
2765 
2766 			uint32_t rsvd[2];
2767 		} profile3;
2768 
2769 		struct {
2770 			#ifdef __BIG_ENDIAN_BITFIELD
2771 				uint32_t	seqlenoff	:16;
2772 				uint32_t	maxlen		:16;
2773 			#else	/*  __LITTLE_ENDIAN */
2774 				uint32_t	maxlen		:16;
2775 				uint32_t	seqlenoff	:16;
2776 			#endif
2777 			#ifdef __BIG_ENDIAN_BITFIELD
2778 				uint32_t	cmdcodeoff	:28;
2779 				uint32_t	rsvd1		:12;
2780 				uint32_t	seqlenbcnt	:4;
2781 			#else	/*  __LITTLE_ENDIAN */
2782 				uint32_t	seqlenbcnt	:4;
2783 				uint32_t	rsvd1		:12;
2784 				uint32_t	cmdcodeoff	:28;
2785 			#endif
2786 			uint32_t cmdmatch[8];
2787 
2788 			uint32_t rsvd[2];
2789 		} profile5;
2790 
2791 	} profiles;
2792 
2793 };
2794 
2795 
2796 
2797 /* Structure for MB Command CONFIG_PORT (0x88) */
2798 typedef struct {
2799 #ifdef __BIG_ENDIAN_BITFIELD
2800 	uint32_t cBE       :  1;
2801 	uint32_t cET       :  1;
2802 	uint32_t cHpcb     :  1;
2803 	uint32_t cMA       :  1;
2804 	uint32_t sli_mode  :  4;
2805 	uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
2806 					* config block */
2807 #else	/*  __LITTLE_ENDIAN */
2808 	uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
2809 					* config block */
2810 	uint32_t sli_mode  :  4;
2811 	uint32_t cMA       :  1;
2812 	uint32_t cHpcb     :  1;
2813 	uint32_t cET       :  1;
2814 	uint32_t cBE       :  1;
2815 #endif
2816 
2817 	uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
2818 	uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
2819 	uint32_t hbainit[5];
2820 #ifdef __BIG_ENDIAN_BITFIELD
2821 	uint32_t hps	   :  1; /* bit 31 word9 Host Pointer in slim */
2822 	uint32_t rsvd	   : 31; /* least significant 31 bits of word 9 */
2823 #else   /*  __LITTLE_ENDIAN */
2824 	uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
2825 	uint32_t hps	   :  1; /* bit 31 word9 Host Pointer in slim */
2826 #endif
2827 
2828 #ifdef __BIG_ENDIAN_BITFIELD
2829 	uint32_t rsvd1     : 19;  /* Reserved                             */
2830 	uint32_t cdss      :  1;  /* Configure Data Security SLI          */
2831 	uint32_t casabt    :  1;  /* Configure async abts status notice   */
2832 	uint32_t rsvd2     :  2;  /* Reserved                             */
2833 	uint32_t cbg       :  1;  /* Configure BlockGuard                 */
2834 	uint32_t cmv       :  1;  /* Configure Max VPIs                   */
2835 	uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
2836 	uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
2837 	uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
2838 	uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
2839 	uint32_t cerbm	   :  1;  /* Configure Enhanced Receive Buf Mgmt  */
2840 	uint32_t cmx	   :  1;  /* Configure Max XRIs                   */
2841 	uint32_t cmr	   :  1;  /* Configure Max RPIs                   */
2842 #else	/*  __LITTLE_ENDIAN */
2843 	uint32_t cmr	   :  1;  /* Configure Max RPIs                   */
2844 	uint32_t cmx	   :  1;  /* Configure Max XRIs                   */
2845 	uint32_t cerbm	   :  1;  /* Configure Enhanced Receive Buf Mgmt  */
2846 	uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
2847 	uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
2848 	uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
2849 	uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
2850 	uint32_t cmv	   :  1;  /* Configure Max VPIs                   */
2851 	uint32_t cbg       :  1;  /* Configure BlockGuard                 */
2852 	uint32_t rsvd2     :  2;  /* Reserved                             */
2853 	uint32_t casabt    :  1;  /* Configure async abts status notice   */
2854 	uint32_t cdss      :  1;  /* Configure Data Security SLI          */
2855 	uint32_t rsvd1     : 19;  /* Reserved                             */
2856 #endif
2857 #ifdef __BIG_ENDIAN_BITFIELD
2858 	uint32_t rsvd3     : 19;  /* Reserved                             */
2859 	uint32_t gdss      :  1;  /* Configure Data Security SLI          */
2860 	uint32_t gasabt    :  1;  /* Grant async abts status notice       */
2861 	uint32_t rsvd4     :  2;  /* Reserved                             */
2862 	uint32_t gbg       :  1;  /* Grant BlockGuard                     */
2863 	uint32_t gmv	   :  1;  /* Grant Max VPIs                       */
2864 	uint32_t gcrp	   :  1;  /* Grant Command Ring Polling           */
2865 	uint32_t gsah	   :  1;  /* Grant Synchronous Abort Handling     */
2866 	uint32_t ghbs	   :  1;  /* Grant Host Backing Store             */
2867 	uint32_t ginb	   :  1;  /* Grant Interrupt Notification Block   */
2868 	uint32_t gerbm	   :  1;  /* Grant ERBM Request                   */
2869 	uint32_t gmx	   :  1;  /* Grant Max XRIs                       */
2870 	uint32_t gmr	   :  1;  /* Grant Max RPIs                       */
2871 #else	/*  __LITTLE_ENDIAN */
2872 	uint32_t gmr	   :  1;  /* Grant Max RPIs                       */
2873 	uint32_t gmx	   :  1;  /* Grant Max XRIs                       */
2874 	uint32_t gerbm	   :  1;  /* Grant ERBM Request                   */
2875 	uint32_t ginb	   :  1;  /* Grant Interrupt Notification Block   */
2876 	uint32_t ghbs	   :  1;  /* Grant Host Backing Store             */
2877 	uint32_t gsah	   :  1;  /* Grant Synchronous Abort Handling     */
2878 	uint32_t gcrp	   :  1;  /* Grant Command Ring Polling           */
2879 	uint32_t gmv	   :  1;  /* Grant Max VPIs                       */
2880 	uint32_t gbg       :  1;  /* Grant BlockGuard                     */
2881 	uint32_t rsvd4     :  2;  /* Reserved                             */
2882 	uint32_t gasabt    :  1;  /* Grant async abts status notice       */
2883 	uint32_t gdss      :  1;  /* Configure Data Security SLI          */
2884 	uint32_t rsvd3     : 19;  /* Reserved                             */
2885 #endif
2886 
2887 #ifdef __BIG_ENDIAN_BITFIELD
2888 	uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
2889 	uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
2890 #else	/*  __LITTLE_ENDIAN */
2891 	uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
2892 	uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
2893 #endif
2894 
2895 #ifdef __BIG_ENDIAN_BITFIELD
2896 	uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
2897 	uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
2898 #else	/*  __LITTLE_ENDIAN */
2899 	uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
2900 	uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
2901 #endif
2902 
2903 	uint32_t rsvd6;           /* Reserved                             */
2904 
2905 #ifdef __BIG_ENDIAN_BITFIELD
2906 	uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
2907 	uint32_t fips_level : 4;   /* FIPS Level                           */
2908 	uint32_t sec_err    : 9;   /* security crypto error                */
2909 	uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
2910 #else	/*  __LITTLE_ENDIAN */
2911 	uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
2912 	uint32_t sec_err    : 9;   /* security crypto error                */
2913 	uint32_t fips_level : 4;   /* FIPS Level                           */
2914 	uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
2915 #endif
2916 
2917 } CONFIG_PORT_VAR;
2918 
2919 /* Structure for MB Command CONFIG_MSI (0x30) */
2920 struct config_msi_var {
2921 #ifdef __BIG_ENDIAN_BITFIELD
2922 	uint32_t dfltMsgNum:8;	/* Default message number            */
2923 	uint32_t rsvd1:11;	/* Reserved                          */
2924 	uint32_t NID:5;		/* Number of secondary attention IDs */
2925 	uint32_t rsvd2:5;	/* Reserved                          */
2926 	uint32_t dfltPresent:1;	/* Default message number present    */
2927 	uint32_t addFlag:1;	/* Add association flag              */
2928 	uint32_t reportFlag:1;	/* Report association flag           */
2929 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2930 	uint32_t reportFlag:1;	/* Report association flag           */
2931 	uint32_t addFlag:1;	/* Add association flag              */
2932 	uint32_t dfltPresent:1;	/* Default message number present    */
2933 	uint32_t rsvd2:5;	/* Reserved                          */
2934 	uint32_t NID:5;		/* Number of secondary attention IDs */
2935 	uint32_t rsvd1:11;	/* Reserved                          */
2936 	uint32_t dfltMsgNum:8;	/* Default message number            */
2937 #endif
2938 	uint32_t attentionConditions[2];
2939 	uint8_t  attentionId[16];
2940 	uint8_t  messageNumberByHA[64];
2941 	uint8_t  messageNumberByID[16];
2942 	uint32_t autoClearHA[2];
2943 #ifdef __BIG_ENDIAN_BITFIELD
2944 	uint32_t rsvd3:16;
2945 	uint32_t autoClearID:16;
2946 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2947 	uint32_t autoClearID:16;
2948 	uint32_t rsvd3:16;
2949 #endif
2950 	uint32_t rsvd4;
2951 };
2952 
2953 /* SLI-2 Port Control Block */
2954 
2955 /* SLIM POINTER */
2956 #define SLIMOFF 0x30		/* WORD */
2957 
2958 typedef struct _SLI2_RDSC {
2959 	uint32_t cmdEntries;
2960 	uint32_t cmdAddrLow;
2961 	uint32_t cmdAddrHigh;
2962 
2963 	uint32_t rspEntries;
2964 	uint32_t rspAddrLow;
2965 	uint32_t rspAddrHigh;
2966 } SLI2_RDSC;
2967 
2968 typedef struct _PCB {
2969 #ifdef __BIG_ENDIAN_BITFIELD
2970 	uint32_t type:8;
2971 #define TYPE_NATIVE_SLI2       0x01
2972 	uint32_t feature:8;
2973 #define FEATURE_INITIAL_SLI2   0x01
2974 	uint32_t rsvd:12;
2975 	uint32_t maxRing:4;
2976 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2977 	uint32_t maxRing:4;
2978 	uint32_t rsvd:12;
2979 	uint32_t feature:8;
2980 #define FEATURE_INITIAL_SLI2   0x01
2981 	uint32_t type:8;
2982 #define TYPE_NATIVE_SLI2       0x01
2983 #endif
2984 
2985 	uint32_t mailBoxSize;
2986 	uint32_t mbAddrLow;
2987 	uint32_t mbAddrHigh;
2988 
2989 	uint32_t hgpAddrLow;
2990 	uint32_t hgpAddrHigh;
2991 
2992 	uint32_t pgpAddrLow;
2993 	uint32_t pgpAddrHigh;
2994 	SLI2_RDSC rdsc[MAX_RINGS];
2995 } PCB_t;
2996 
2997 /* NEW_FEATURE */
2998 typedef struct {
2999 #ifdef __BIG_ENDIAN_BITFIELD
3000 	uint32_t rsvd0:27;
3001 	uint32_t discardFarp:1;
3002 	uint32_t IPEnable:1;
3003 	uint32_t nodeName:1;
3004 	uint32_t portName:1;
3005 	uint32_t filterEnable:1;
3006 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3007 	uint32_t filterEnable:1;
3008 	uint32_t portName:1;
3009 	uint32_t nodeName:1;
3010 	uint32_t IPEnable:1;
3011 	uint32_t discardFarp:1;
3012 	uint32_t rsvd:27;
3013 #endif
3014 
3015 	uint8_t portname[8];	/* Used to be struct lpfc_name */
3016 	uint8_t nodename[8];
3017 	uint32_t rsvd1;
3018 	uint32_t rsvd2;
3019 	uint32_t rsvd3;
3020 	uint32_t IPAddress;
3021 } CONFIG_FARP_VAR;
3022 
3023 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3024 
3025 typedef struct {
3026 #ifdef __BIG_ENDIAN_BITFIELD
3027 	uint32_t rsvd:30;
3028 	uint32_t ring:2;	/* Ring for ASYNC_EVENT iocb Bits 0-1*/
3029 #else /*  __LITTLE_ENDIAN */
3030 	uint32_t ring:2;	/* Ring for ASYNC_EVENT iocb Bits 0-1*/
3031 	uint32_t rsvd:30;
3032 #endif
3033 } ASYNCEVT_ENABLE_VAR;
3034 
3035 /* Union of all Mailbox Command types */
3036 #define MAILBOX_CMD_WSIZE	32
3037 #define MAILBOX_CMD_SIZE	(MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3038 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3039 #define MAILBOX_EXT_WSIZE	512
3040 #define MAILBOX_EXT_SIZE	(MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3041 #define MAILBOX_HBA_EXT_OFFSET  0x100
3042 /* max mbox xmit size is a page size for sysfs IO operations */
3043 #define MAILBOX_SYSFS_MAX	4096
3044 
3045 typedef union {
3046 	uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3047 						    * feature/max ring number
3048 						    */
3049 	LOAD_SM_VAR varLdSM;		/* cmd =  1 (LOAD_SM)        */
3050 	READ_NV_VAR varRDnvp;		/* cmd =  2 (READ_NVPARMS)   */
3051 	WRITE_NV_VAR varWTnvp;		/* cmd =  3 (WRITE_NVPARMS)  */
3052 	BIU_DIAG_VAR varBIUdiag;	/* cmd =  4 (RUN_BIU_DIAG)   */
3053 	INIT_LINK_VAR varInitLnk;	/* cmd =  5 (INIT_LINK)      */
3054 	DOWN_LINK_VAR varDwnLnk;	/* cmd =  6 (DOWN_LINK)      */
3055 	CONFIG_LINK varCfgLnk;		/* cmd =  7 (CONFIG_LINK)    */
3056 	PART_SLIM_VAR varSlim;		/* cmd =  8 (PART_SLIM)      */
3057 	CONFIG_RING_VAR varCfgRing;	/* cmd =  9 (CONFIG_RING)    */
3058 	RESET_RING_VAR varRstRing;	/* cmd = 10 (RESET_RING)     */
3059 	READ_CONFIG_VAR varRdConfig;	/* cmd = 11 (READ_CONFIG)    */
3060 	READ_RCONF_VAR varRdRConfig;	/* cmd = 12 (READ_RCONFIG)   */
3061 	READ_SPARM_VAR varRdSparm;	/* cmd = 13 (READ_SPARM(64)) */
3062 	READ_STATUS_VAR varRdStatus;	/* cmd = 14 (READ_STATUS)    */
3063 	READ_RPI_VAR varRdRPI;		/* cmd = 15 (READ_RPI(64))   */
3064 	READ_XRI_VAR varRdXRI;		/* cmd = 16 (READ_XRI)       */
3065 	READ_REV_VAR varRdRev;		/* cmd = 17 (READ_REV)       */
3066 	READ_LNK_VAR varRdLnk;		/* cmd = 18 (READ_LNK_STAT)  */
3067 	REG_LOGIN_VAR varRegLogin;	/* cmd = 19 (REG_LOGIN(64))  */
3068 	UNREG_LOGIN_VAR varUnregLogin;	/* cmd = 20 (UNREG_LOGIN)    */
3069 	CLEAR_LA_VAR varClearLA;	/* cmd = 22 (CLEAR_LA)       */
3070 	DUMP_VAR varDmp;		/* Warm Start DUMP mbx cmd   */
3071 	UNREG_D_ID_VAR varUnregDID;	/* cmd = 0x23 (UNREG_D_ID)   */
3072 	CONFIG_FARP_VAR varCfgFarp;	/* cmd = 0x25 (CONFIG_FARP)
3073 					 * NEW_FEATURE
3074 					 */
3075 	struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
3076 	struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3077 	CONFIG_PORT_VAR varCfgPort;	/* cmd = 0x88 (CONFIG_PORT)  */
3078 	struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3079 	REG_VPI_VAR varRegVpi;		/* cmd = 0x96 (REG_VPI) */
3080 	UNREG_VPI_VAR varUnregVpi;	/* cmd = 0x97 (UNREG_VPI) */
3081 	ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3082 	struct READ_EVENT_LOG_VAR varRdEventLog;	/* cmd = 0x38
3083 							 * (READ_EVENT_LOG)
3084 							 */
3085 	struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI)     */
3086 } MAILVARIANTS;
3087 
3088 /*
3089  * SLI-2 specific structures
3090  */
3091 
3092 struct lpfc_hgp {
3093 	__le32 cmdPutInx;
3094 	__le32 rspGetInx;
3095 };
3096 
3097 struct lpfc_pgp {
3098 	__le32 cmdGetInx;
3099 	__le32 rspPutInx;
3100 };
3101 
3102 struct sli2_desc {
3103 	uint32_t unused1[16];
3104 	struct lpfc_hgp host[MAX_RINGS];
3105 	struct lpfc_pgp port[MAX_RINGS];
3106 };
3107 
3108 struct sli3_desc {
3109 	struct lpfc_hgp host[MAX_RINGS];
3110 	uint32_t reserved[8];
3111 	uint32_t hbq_put[16];
3112 };
3113 
3114 struct sli3_pgp {
3115 	struct lpfc_pgp port[MAX_RINGS];
3116 	uint32_t hbq_get[16];
3117 };
3118 
3119 union sli_var {
3120 	struct sli2_desc	s2;
3121 	struct sli3_desc	s3;
3122 	struct sli3_pgp		s3_pgp;
3123 };
3124 
3125 typedef struct {
3126 #ifdef __BIG_ENDIAN_BITFIELD
3127 	uint16_t mbxStatus;
3128 	uint8_t mbxCommand;
3129 	uint8_t mbxReserved:6;
3130 	uint8_t mbxHc:1;
3131 	uint8_t mbxOwner:1;	/* Low order bit first word */
3132 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3133 	uint8_t mbxOwner:1;	/* Low order bit first word */
3134 	uint8_t mbxHc:1;
3135 	uint8_t mbxReserved:6;
3136 	uint8_t mbxCommand;
3137 	uint16_t mbxStatus;
3138 #endif
3139 
3140 	MAILVARIANTS un;
3141 	union sli_var us;
3142 } MAILBOX_t;
3143 
3144 /*
3145  *    Begin Structure Definitions for IOCB Commands
3146  */
3147 
3148 typedef struct {
3149 #ifdef __BIG_ENDIAN_BITFIELD
3150 	uint8_t statAction;
3151 	uint8_t statRsn;
3152 	uint8_t statBaExp;
3153 	uint8_t statLocalError;
3154 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3155 	uint8_t statLocalError;
3156 	uint8_t statBaExp;
3157 	uint8_t statRsn;
3158 	uint8_t statAction;
3159 #endif
3160 	/* statRsn  P/F_RJT reason codes */
3161 #define RJT_BAD_D_ID       0x01	/* Invalid D_ID field */
3162 #define RJT_BAD_S_ID       0x02	/* Invalid S_ID field */
3163 #define RJT_UNAVAIL_TEMP   0x03	/* N_Port unavailable temp. */
3164 #define RJT_UNAVAIL_PERM   0x04	/* N_Port unavailable perm. */
3165 #define RJT_UNSUP_CLASS    0x05	/* Class not supported */
3166 #define RJT_DELIM_ERR      0x06	/* Delimiter usage error */
3167 #define RJT_UNSUP_TYPE     0x07	/* Type not supported */
3168 #define RJT_BAD_CONTROL    0x08	/* Invalid link conrtol */
3169 #define RJT_BAD_RCTL       0x09	/* R_CTL invalid */
3170 #define RJT_BAD_FCTL       0x0A	/* F_CTL invalid */
3171 #define RJT_BAD_OXID       0x0B	/* OX_ID invalid */
3172 #define RJT_BAD_RXID       0x0C	/* RX_ID invalid */
3173 #define RJT_BAD_SEQID      0x0D	/* SEQ_ID invalid */
3174 #define RJT_BAD_DFCTL      0x0E	/* DF_CTL invalid */
3175 #define RJT_BAD_SEQCNT     0x0F	/* SEQ_CNT invalid */
3176 #define RJT_BAD_PARM       0x10	/* Param. field invalid */
3177 #define RJT_XCHG_ERR       0x11	/* Exchange error */
3178 #define RJT_PROT_ERR       0x12	/* Protocol error */
3179 #define RJT_BAD_LENGTH     0x13	/* Invalid Length */
3180 #define RJT_UNEXPECTED_ACK 0x14	/* Unexpected ACK */
3181 #define RJT_LOGIN_REQUIRED 0x16	/* Login required */
3182 #define RJT_TOO_MANY_SEQ   0x17	/* Excessive sequences */
3183 #define RJT_XCHG_NOT_STRT  0x18	/* Exchange not started */
3184 #define RJT_UNSUP_SEC_HDR  0x19	/* Security hdr not supported */
3185 #define RJT_UNAVAIL_PATH   0x1A	/* Fabric Path not available */
3186 #define RJT_VENDOR_UNIQUE  0xFF	/* Vendor unique error */
3187 
3188 #define IOERR_SUCCESS                 0x00	/* statLocalError */
3189 #define IOERR_MISSING_CONTINUE        0x01
3190 #define IOERR_SEQUENCE_TIMEOUT        0x02
3191 #define IOERR_INTERNAL_ERROR          0x03
3192 #define IOERR_INVALID_RPI             0x04
3193 #define IOERR_NO_XRI                  0x05
3194 #define IOERR_ILLEGAL_COMMAND         0x06
3195 #define IOERR_XCHG_DROPPED            0x07
3196 #define IOERR_ILLEGAL_FIELD           0x08
3197 #define IOERR_BAD_CONTINUE            0x09
3198 #define IOERR_TOO_MANY_BUFFERS        0x0A
3199 #define IOERR_RCV_BUFFER_WAITING      0x0B
3200 #define IOERR_NO_CONNECTION           0x0C
3201 #define IOERR_TX_DMA_FAILED           0x0D
3202 #define IOERR_RX_DMA_FAILED           0x0E
3203 #define IOERR_ILLEGAL_FRAME           0x0F
3204 #define IOERR_EXTRA_DATA              0x10
3205 #define IOERR_NO_RESOURCES            0x11
3206 #define IOERR_RESERVED                0x12
3207 #define IOERR_ILLEGAL_LENGTH          0x13
3208 #define IOERR_UNSUPPORTED_FEATURE     0x14
3209 #define IOERR_ABORT_IN_PROGRESS       0x15
3210 #define IOERR_ABORT_REQUESTED         0x16
3211 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
3212 #define IOERR_LOOP_OPEN_FAILURE       0x18
3213 #define IOERR_RING_RESET              0x19
3214 #define IOERR_LINK_DOWN               0x1A
3215 #define IOERR_CORRUPTED_DATA          0x1B
3216 #define IOERR_CORRUPTED_RPI           0x1C
3217 #define IOERR_OUT_OF_ORDER_DATA       0x1D
3218 #define IOERR_OUT_OF_ORDER_ACK        0x1E
3219 #define IOERR_DUP_FRAME               0x1F
3220 #define IOERR_LINK_CONTROL_FRAME      0x20	/* ACK_N received */
3221 #define IOERR_BAD_HOST_ADDRESS        0x21
3222 #define IOERR_RCV_HDRBUF_WAITING      0x22
3223 #define IOERR_MISSING_HDR_BUFFER      0x23
3224 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
3225 #define IOERR_ABORTMULT_REQUESTED     0x25
3226 #define IOERR_BUFFER_SHORTAGE         0x28
3227 #define IOERR_DEFAULT                 0x29
3228 #define IOERR_CNT                     0x2A
3229 #define IOERR_SLER_FAILURE            0x46
3230 #define IOERR_SLER_CMD_RCV_FAILURE    0x47
3231 #define IOERR_SLER_REC_RJT_ERR        0x48
3232 #define IOERR_SLER_REC_SRR_RETRY_ERR  0x49
3233 #define IOERR_SLER_SRR_RJT_ERR        0x4A
3234 #define IOERR_SLER_RRQ_RJT_ERR        0x4C
3235 #define IOERR_SLER_RRQ_RETRY_ERR      0x4D
3236 #define IOERR_SLER_ABTS_ERR           0x4E
3237 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR		0xF0
3238 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR	0xF1
3239 #define IOERR_ELXSEC_CRYPTO_ERROR		0xF2
3240 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR	0xF3
3241 #define IOERR_DRVR_MASK               0x100
3242 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
3243 #define IOERR_SLI_BRESET              0x102
3244 #define IOERR_SLI_ABORTED             0x103
3245 } PARM_ERR;
3246 
3247 typedef union {
3248 	struct {
3249 #ifdef __BIG_ENDIAN_BITFIELD
3250 		uint8_t Rctl;	/* R_CTL field */
3251 		uint8_t Type;	/* TYPE field */
3252 		uint8_t Dfctl;	/* DF_CTL field */
3253 		uint8_t Fctl;	/* Bits 0-7 of IOCB word 5 */
3254 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3255 		uint8_t Fctl;	/* Bits 0-7 of IOCB word 5 */
3256 		uint8_t Dfctl;	/* DF_CTL field */
3257 		uint8_t Type;	/* TYPE field */
3258 		uint8_t Rctl;	/* R_CTL field */
3259 #endif
3260 
3261 #define BC      0x02		/* Broadcast Received  - Fctl */
3262 #define SI      0x04		/* Sequence Initiative */
3263 #define LA      0x08		/* Ignore Link Attention state */
3264 #define LS      0x80		/* Last Sequence */
3265 	} hcsw;
3266 	uint32_t reserved;
3267 } WORD5;
3268 
3269 /* IOCB Command template for a generic response */
3270 typedef struct {
3271 	uint32_t reserved[4];
3272 	PARM_ERR perr;
3273 } GENERIC_RSP;
3274 
3275 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3276 typedef struct {
3277 	struct ulp_bde xrsqbde[2];
3278 	uint32_t xrsqRo;	/* Starting Relative Offset */
3279 	WORD5 w5;		/* Header control/status word */
3280 } XR_SEQ_FIELDS;
3281 
3282 /* IOCB Command template for ELS_REQUEST */
3283 typedef struct {
3284 	struct ulp_bde elsReq;
3285 	struct ulp_bde elsRsp;
3286 
3287 #ifdef __BIG_ENDIAN_BITFIELD
3288 	uint32_t word4Rsvd:7;
3289 	uint32_t fl:1;
3290 	uint32_t myID:24;
3291 	uint32_t word5Rsvd:8;
3292 	uint32_t remoteID:24;
3293 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3294 	uint32_t myID:24;
3295 	uint32_t fl:1;
3296 	uint32_t word4Rsvd:7;
3297 	uint32_t remoteID:24;
3298 	uint32_t word5Rsvd:8;
3299 #endif
3300 } ELS_REQUEST;
3301 
3302 /* IOCB Command template for RCV_ELS_REQ */
3303 typedef struct {
3304 	struct ulp_bde elsReq[2];
3305 	uint32_t parmRo;
3306 
3307 #ifdef __BIG_ENDIAN_BITFIELD
3308 	uint32_t word5Rsvd:8;
3309 	uint32_t remoteID:24;
3310 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3311 	uint32_t remoteID:24;
3312 	uint32_t word5Rsvd:8;
3313 #endif
3314 } RCV_ELS_REQ;
3315 
3316 /* IOCB Command template for ABORT / CLOSE_XRI */
3317 typedef struct {
3318 	uint32_t rsvd[3];
3319 	uint32_t abortType;
3320 #define ABORT_TYPE_ABTX  0x00000000
3321 #define ABORT_TYPE_ABTS  0x00000001
3322 	uint32_t parm;
3323 #ifdef __BIG_ENDIAN_BITFIELD
3324 	uint16_t abortContextTag; /* ulpContext from command to abort/close */
3325 	uint16_t abortIoTag;	/* ulpIoTag from command to abort/close */
3326 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3327 	uint16_t abortIoTag;	/* ulpIoTag from command to abort/close */
3328 	uint16_t abortContextTag; /* ulpContext from command to abort/close */
3329 #endif
3330 } AC_XRI;
3331 
3332 /* IOCB Command template for ABORT_MXRI64 */
3333 typedef struct {
3334 	uint32_t rsvd[3];
3335 	uint32_t abortType;
3336 	uint32_t parm;
3337 	uint32_t iotag32;
3338 } A_MXRI64;
3339 
3340 /* IOCB Command template for GET_RPI */
3341 typedef struct {
3342 	uint32_t rsvd[4];
3343 	uint32_t parmRo;
3344 #ifdef __BIG_ENDIAN_BITFIELD
3345 	uint32_t word5Rsvd:8;
3346 	uint32_t remoteID:24;
3347 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3348 	uint32_t remoteID:24;
3349 	uint32_t word5Rsvd:8;
3350 #endif
3351 } GET_RPI;
3352 
3353 /* IOCB Command template for all FCP Initiator commands */
3354 typedef struct {
3355 	struct ulp_bde fcpi_cmnd;	/* FCP_CMND payload descriptor */
3356 	struct ulp_bde fcpi_rsp;	/* Rcv buffer */
3357 	uint32_t fcpi_parm;
3358 	uint32_t fcpi_XRdy;	/* transfer ready for IWRITE */
3359 } FCPI_FIELDS;
3360 
3361 /* IOCB Command template for all FCP Target commands */
3362 typedef struct {
3363 	struct ulp_bde fcpt_Buffer[2];	/* FCP_CMND payload descriptor */
3364 	uint32_t fcpt_Offset;
3365 	uint32_t fcpt_Length;	/* transfer ready for IWRITE */
3366 } FCPT_FIELDS;
3367 
3368 /* SLI-2 IOCB structure definitions */
3369 
3370 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3371 typedef struct {
3372 	ULP_BDL bdl;
3373 	uint32_t xrsqRo;	/* Starting Relative Offset */
3374 	WORD5 w5;		/* Header control/status word */
3375 } XMT_SEQ_FIELDS64;
3376 
3377 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3378 typedef struct {
3379 	struct ulp_bde64 rcvBde;
3380 	uint32_t rsvd1;
3381 	uint32_t xrsqRo;	/* Starting Relative Offset */
3382 	WORD5 w5;		/* Header control/status word */
3383 } RCV_SEQ_FIELDS64;
3384 
3385 /* IOCB Command template for ELS_REQUEST64 */
3386 typedef struct {
3387 	ULP_BDL bdl;
3388 #ifdef __BIG_ENDIAN_BITFIELD
3389 	uint32_t word4Rsvd:7;
3390 	uint32_t fl:1;
3391 	uint32_t myID:24;
3392 	uint32_t word5Rsvd:8;
3393 	uint32_t remoteID:24;
3394 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3395 	uint32_t myID:24;
3396 	uint32_t fl:1;
3397 	uint32_t word4Rsvd:7;
3398 	uint32_t remoteID:24;
3399 	uint32_t word5Rsvd:8;
3400 #endif
3401 } ELS_REQUEST64;
3402 
3403 /* IOCB Command template for GEN_REQUEST64 */
3404 typedef struct {
3405 	ULP_BDL bdl;
3406 	uint32_t xrsqRo;	/* Starting Relative Offset */
3407 	WORD5 w5;		/* Header control/status word */
3408 } GEN_REQUEST64;
3409 
3410 /* IOCB Command template for RCV_ELS_REQ64 */
3411 typedef struct {
3412 	struct ulp_bde64 elsReq;
3413 	uint32_t rcvd1;
3414 	uint32_t parmRo;
3415 
3416 #ifdef __BIG_ENDIAN_BITFIELD
3417 	uint32_t word5Rsvd:8;
3418 	uint32_t remoteID:24;
3419 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3420 	uint32_t remoteID:24;
3421 	uint32_t word5Rsvd:8;
3422 #endif
3423 } RCV_ELS_REQ64;
3424 
3425 /* IOCB Command template for RCV_SEQ64 */
3426 struct rcv_seq64 {
3427 	struct ulp_bde64 elsReq;
3428 	uint32_t hbq_1;
3429 	uint32_t parmRo;
3430 #ifdef __BIG_ENDIAN_BITFIELD
3431 	uint32_t rctl:8;
3432 	uint32_t type:8;
3433 	uint32_t dfctl:8;
3434 	uint32_t ls:1;
3435 	uint32_t fs:1;
3436 	uint32_t rsvd2:3;
3437 	uint32_t si:1;
3438 	uint32_t bc:1;
3439 	uint32_t rsvd3:1;
3440 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3441 	uint32_t rsvd3:1;
3442 	uint32_t bc:1;
3443 	uint32_t si:1;
3444 	uint32_t rsvd2:3;
3445 	uint32_t fs:1;
3446 	uint32_t ls:1;
3447 	uint32_t dfctl:8;
3448 	uint32_t type:8;
3449 	uint32_t rctl:8;
3450 #endif
3451 };
3452 
3453 /* IOCB Command template for all 64 bit FCP Initiator commands */
3454 typedef struct {
3455 	ULP_BDL bdl;
3456 	uint32_t fcpi_parm;
3457 	uint32_t fcpi_XRdy;	/* transfer ready for IWRITE */
3458 } FCPI_FIELDS64;
3459 
3460 /* IOCB Command template for all 64 bit FCP Target commands */
3461 typedef struct {
3462 	ULP_BDL bdl;
3463 	uint32_t fcpt_Offset;
3464 	uint32_t fcpt_Length;	/* transfer ready for IWRITE */
3465 } FCPT_FIELDS64;
3466 
3467 /* IOCB Command template for Async Status iocb commands */
3468 typedef struct {
3469 	uint32_t rsvd[4];
3470 	uint32_t param;
3471 #ifdef __BIG_ENDIAN_BITFIELD
3472 	uint16_t evt_code;		/* High order bits word 5 */
3473 	uint16_t sub_ctxt_tag;		/* Low  order bits word 5 */
3474 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3475 	uint16_t sub_ctxt_tag;		/* High order bits word 5 */
3476 	uint16_t evt_code;		/* Low  order bits word 5 */
3477 #endif
3478 } ASYNCSTAT_FIELDS;
3479 #define ASYNC_TEMP_WARN		0x100
3480 #define ASYNC_TEMP_SAFE		0x101
3481 #define ASYNC_STATUS_CN		0x102
3482 
3483 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3484    or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3485 
3486 struct rcv_sli3 {
3487 #ifdef __BIG_ENDIAN_BITFIELD
3488 	uint16_t ox_id;
3489 	uint16_t seq_cnt;
3490 
3491 	uint16_t vpi;
3492 	uint16_t word9Rsvd;
3493 #else  /*  __LITTLE_ENDIAN */
3494 	uint16_t seq_cnt;
3495 	uint16_t ox_id;
3496 
3497 	uint16_t word9Rsvd;
3498 	uint16_t vpi;
3499 #endif
3500 	uint32_t word10Rsvd;
3501 	uint32_t acc_len;      /* accumulated length */
3502 	struct ulp_bde64 bde2;
3503 };
3504 
3505 /* Structure used for a single HBQ entry */
3506 struct lpfc_hbq_entry {
3507 	struct ulp_bde64 bde;
3508 	uint32_t buffer_tag;
3509 };
3510 
3511 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3512 typedef struct {
3513 	struct lpfc_hbq_entry   buff;
3514 	uint32_t                rsvd;
3515 	uint32_t		rsvd1;
3516 } QUE_XRI64_CX_FIELDS;
3517 
3518 struct que_xri64cx_ext_fields {
3519 	uint32_t	iotag64_low;
3520 	uint32_t	iotag64_high;
3521 	uint32_t	ebde_count;
3522 	uint32_t	rsvd;
3523 	struct lpfc_hbq_entry	buff[5];
3524 };
3525 
3526 struct sli3_bg_fields {
3527 	uint32_t filler[6];	/* word 8-13 in IOCB */
3528 	uint32_t bghm;		/* word 14 - BlockGuard High Water Mark */
3529 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3530 #define BGS_BIDIR_BG_PROF_MASK		0xff000000
3531 #define BGS_BIDIR_BG_PROF_SHIFT		24
3532 #define BGS_BIDIR_ERR_COND_FLAGS_MASK	0x003f0000
3533 #define BGS_BIDIR_ERR_COND_SHIFT	16
3534 #define BGS_BG_PROFILE_MASK		0x0000ff00
3535 #define BGS_BG_PROFILE_SHIFT		8
3536 #define BGS_INVALID_PROF_MASK		0x00000020
3537 #define BGS_INVALID_PROF_SHIFT		5
3538 #define BGS_UNINIT_DIF_BLOCK_MASK	0x00000010
3539 #define BGS_UNINIT_DIF_BLOCK_SHIFT	4
3540 #define BGS_HI_WATER_MARK_PRESENT_MASK	0x00000008
3541 #define BGS_HI_WATER_MARK_PRESENT_SHIFT	3
3542 #define BGS_REFTAG_ERR_MASK		0x00000004
3543 #define BGS_REFTAG_ERR_SHIFT		2
3544 #define BGS_APPTAG_ERR_MASK		0x00000002
3545 #define BGS_APPTAG_ERR_SHIFT		1
3546 #define BGS_GUARD_ERR_MASK		0x00000001
3547 #define BGS_GUARD_ERR_SHIFT		0
3548 	uint32_t bgstat;	/* word 15 - BlockGuard Status */
3549 };
3550 
3551 static inline uint32_t
lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)3552 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3553 {
3554 	return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3555 				BGS_BIDIR_BG_PROF_SHIFT;
3556 }
3557 
3558 static inline uint32_t
lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)3559 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3560 {
3561 	return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3562 				BGS_BIDIR_ERR_COND_SHIFT;
3563 }
3564 
3565 static inline uint32_t
lpfc_bgs_get_bg_prof(uint32_t bgstat)3566 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3567 {
3568 	return (bgstat & BGS_BG_PROFILE_MASK) >>
3569 				BGS_BG_PROFILE_SHIFT;
3570 }
3571 
3572 static inline uint32_t
lpfc_bgs_get_invalid_prof(uint32_t bgstat)3573 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3574 {
3575 	return (bgstat & BGS_INVALID_PROF_MASK) >>
3576 				BGS_INVALID_PROF_SHIFT;
3577 }
3578 
3579 static inline uint32_t
lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)3580 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3581 {
3582 	return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3583 				BGS_UNINIT_DIF_BLOCK_SHIFT;
3584 }
3585 
3586 static inline uint32_t
lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)3587 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3588 {
3589 	return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3590 				BGS_HI_WATER_MARK_PRESENT_SHIFT;
3591 }
3592 
3593 static inline uint32_t
lpfc_bgs_get_reftag_err(uint32_t bgstat)3594 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3595 {
3596 	return (bgstat & BGS_REFTAG_ERR_MASK) >>
3597 				BGS_REFTAG_ERR_SHIFT;
3598 }
3599 
3600 static inline uint32_t
lpfc_bgs_get_apptag_err(uint32_t bgstat)3601 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3602 {
3603 	return (bgstat & BGS_APPTAG_ERR_MASK) >>
3604 				BGS_APPTAG_ERR_SHIFT;
3605 }
3606 
3607 static inline uint32_t
lpfc_bgs_get_guard_err(uint32_t bgstat)3608 lpfc_bgs_get_guard_err(uint32_t bgstat)
3609 {
3610 	return (bgstat & BGS_GUARD_ERR_MASK) >>
3611 				BGS_GUARD_ERR_SHIFT;
3612 }
3613 
3614 #define LPFC_EXT_DATA_BDE_COUNT 3
3615 struct fcp_irw_ext {
3616 	uint32_t	io_tag64_low;
3617 	uint32_t	io_tag64_high;
3618 #ifdef __BIG_ENDIAN_BITFIELD
3619 	uint8_t		reserved1;
3620 	uint8_t		reserved2;
3621 	uint8_t		reserved3;
3622 	uint8_t		ebde_count;
3623 #else  /* __LITTLE_ENDIAN */
3624 	uint8_t		ebde_count;
3625 	uint8_t		reserved3;
3626 	uint8_t		reserved2;
3627 	uint8_t		reserved1;
3628 #endif
3629 	uint32_t	reserved4;
3630 	struct ulp_bde64 rbde;		/* response bde */
3631 	struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT];	/* data BDE or BPL */
3632 	uint8_t icd[32];		/* immediate command data (32 bytes) */
3633 };
3634 
3635 typedef struct _IOCB {	/* IOCB structure */
3636 	union {
3637 		GENERIC_RSP grsp;	/* Generic response */
3638 		XR_SEQ_FIELDS xrseq;	/* XMIT / BCAST / RCV_SEQUENCE cmd */
3639 		struct ulp_bde cont[3];	/* up to 3 continuation bdes */
3640 		RCV_ELS_REQ rcvels;	/* RCV_ELS_REQ template */
3641 		AC_XRI acxri;	/* ABORT / CLOSE_XRI template */
3642 		A_MXRI64 amxri;	/* abort multiple xri command overlay */
3643 		GET_RPI getrpi;	/* GET_RPI template */
3644 		FCPI_FIELDS fcpi;	/* FCP Initiator template */
3645 		FCPT_FIELDS fcpt;	/* FCP target template */
3646 
3647 		/* SLI-2 structures */
3648 
3649 		struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
3650 					      * bde_64s */
3651 		ELS_REQUEST64 elsreq64;	/* ELS_REQUEST template */
3652 		GEN_REQUEST64 genreq64;	/* GEN_REQUEST template */
3653 		RCV_ELS_REQ64 rcvels64;	/* RCV_ELS_REQ template */
3654 		XMT_SEQ_FIELDS64 xseq64;	/* XMIT / BCAST cmd */
3655 		FCPI_FIELDS64 fcpi64;	/* FCP 64 bit Initiator template */
3656 		FCPT_FIELDS64 fcpt64;	/* FCP 64 bit target template */
3657 		ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3658 		QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3659 		struct rcv_seq64 rcvseq64;	/* RCV_SEQ64 and RCV_CONT64 */
3660 		struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
3661 		uint32_t ulpWord[IOCB_WORD_SZ - 2];	/* generic 6 'words' */
3662 	} un;
3663 	union {
3664 		struct {
3665 #ifdef __BIG_ENDIAN_BITFIELD
3666 			uint16_t ulpContext;	/* High order bits word 6 */
3667 			uint16_t ulpIoTag;	/* Low  order bits word 6 */
3668 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3669 			uint16_t ulpIoTag;	/* Low  order bits word 6 */
3670 			uint16_t ulpContext;	/* High order bits word 6 */
3671 #endif
3672 		} t1;
3673 		struct {
3674 #ifdef __BIG_ENDIAN_BITFIELD
3675 			uint16_t ulpContext;	/* High order bits word 6 */
3676 			uint16_t ulpIoTag1:2;	/* Low  order bits word 6 */
3677 			uint16_t ulpIoTag0:14;	/* Low  order bits word 6 */
3678 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3679 			uint16_t ulpIoTag0:14;	/* Low  order bits word 6 */
3680 			uint16_t ulpIoTag1:2;	/* Low  order bits word 6 */
3681 			uint16_t ulpContext;	/* High order bits word 6 */
3682 #endif
3683 		} t2;
3684 	} un1;
3685 #define ulpContext un1.t1.ulpContext
3686 #define ulpIoTag   un1.t1.ulpIoTag
3687 #define ulpIoTag0  un1.t2.ulpIoTag0
3688 
3689 #ifdef __BIG_ENDIAN_BITFIELD
3690 	uint32_t ulpTimeout:8;
3691 	uint32_t ulpXS:1;
3692 	uint32_t ulpFCP2Rcvy:1;
3693 	uint32_t ulpPU:2;
3694 	uint32_t ulpIr:1;
3695 	uint32_t ulpClass:3;
3696 	uint32_t ulpCommand:8;
3697 	uint32_t ulpStatus:4;
3698 	uint32_t ulpBdeCount:2;
3699 	uint32_t ulpLe:1;
3700 	uint32_t ulpOwner:1;	/* Low order bit word 7 */
3701 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3702 	uint32_t ulpOwner:1;	/* Low order bit word 7 */
3703 	uint32_t ulpLe:1;
3704 	uint32_t ulpBdeCount:2;
3705 	uint32_t ulpStatus:4;
3706 	uint32_t ulpCommand:8;
3707 	uint32_t ulpClass:3;
3708 	uint32_t ulpIr:1;
3709 	uint32_t ulpPU:2;
3710 	uint32_t ulpFCP2Rcvy:1;
3711 	uint32_t ulpXS:1;
3712 	uint32_t ulpTimeout:8;
3713 #endif
3714 
3715 	union {
3716 		struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3717 
3718 		/* words 8-31 used for que_xri_cx iocb */
3719 		struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3720 		struct fcp_irw_ext fcp_ext;
3721 		uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3722 
3723 		/* words 8-15 for BlockGuard */
3724 		struct sli3_bg_fields sli3_bg;
3725 	} unsli3;
3726 
3727 #define ulpCt_h ulpXS
3728 #define ulpCt_l ulpFCP2Rcvy
3729 
3730 #define IOCB_FCP	   1	/* IOCB is used for FCP ELS cmds-ulpRsvByte */
3731 #define IOCB_IP		   2	/* IOCB is used for IP ELS cmds */
3732 #define PARM_UNUSED        0	/* PU field (Word 4) not used */
3733 #define PARM_REL_OFF       1	/* PU field (Word 4) = R. O. */
3734 #define PARM_READ_CHECK    2	/* PU field (Word 4) = Data Transfer Length */
3735 #define PARM_NPIV_DID	   3
3736 #define CLASS1             0	/* Class 1 */
3737 #define CLASS2             1	/* Class 2 */
3738 #define CLASS3             2	/* Class 3 */
3739 #define CLASS_FCP_INTERMIX 7	/* FCP Data->Cls 1, all else->Cls 2 */
3740 
3741 #define IOSTAT_SUCCESS         0x0	/* ulpStatus  - HBA defined */
3742 #define IOSTAT_FCP_RSP_ERROR   0x1
3743 #define IOSTAT_REMOTE_STOP     0x2
3744 #define IOSTAT_LOCAL_REJECT    0x3
3745 #define IOSTAT_NPORT_RJT       0x4
3746 #define IOSTAT_FABRIC_RJT      0x5
3747 #define IOSTAT_NPORT_BSY       0x6
3748 #define IOSTAT_FABRIC_BSY      0x7
3749 #define IOSTAT_INTERMED_RSP    0x8
3750 #define IOSTAT_LS_RJT          0x9
3751 #define IOSTAT_BA_RJT          0xA
3752 #define IOSTAT_RSVD1           0xB
3753 #define IOSTAT_RSVD2           0xC
3754 #define IOSTAT_RSVD3           0xD
3755 #define IOSTAT_RSVD4           0xE
3756 #define IOSTAT_NEED_BUFFER     0xF
3757 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
3758 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
3759 #define IOSTAT_CNT             0x11
3760 
3761 } IOCB_t;
3762 
3763 
3764 #define SLI1_SLIM_SIZE   (4 * 1024)
3765 
3766 /* Up to 498 IOCBs will fit into 16k
3767  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3768  */
3769 #define SLI2_SLIM_SIZE   (64 * 1024)
3770 
3771 /* Maximum IOCBs that will fit in SLI2 slim */
3772 #define MAX_SLI2_IOCB    498
3773 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3774 			    (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3775 			    sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
3776 
3777 /* HBQ entries are 4 words each = 4k */
3778 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
3779 			     lpfc_sli_hbq_count())
3780 
3781 struct lpfc_sli2_slim {
3782 	MAILBOX_t mbx;
3783 	uint32_t  mbx_ext_words[MAILBOX_EXT_WSIZE];
3784 	PCB_t pcb;
3785 	IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3786 };
3787 
3788 /*
3789  * This function checks PCI device to allow special handling for LC HBAs.
3790  *
3791  * Parameters:
3792  * device : struct pci_dev 's device field
3793  *
3794  * return 1 => TRUE
3795  *        0 => FALSE
3796  */
3797 static inline int
lpfc_is_LC_HBA(unsigned short device)3798 lpfc_is_LC_HBA(unsigned short device)
3799 {
3800 	if ((device == PCI_DEVICE_ID_TFLY) ||
3801 	    (device == PCI_DEVICE_ID_PFLY) ||
3802 	    (device == PCI_DEVICE_ID_LP101) ||
3803 	    (device == PCI_DEVICE_ID_BMID) ||
3804 	    (device == PCI_DEVICE_ID_BSMB) ||
3805 	    (device == PCI_DEVICE_ID_ZMID) ||
3806 	    (device == PCI_DEVICE_ID_ZSMB) ||
3807 	    (device == PCI_DEVICE_ID_SAT_MID) ||
3808 	    (device == PCI_DEVICE_ID_SAT_SMB) ||
3809 	    (device == PCI_DEVICE_ID_RFLY))
3810 		return 1;
3811 	else
3812 		return 0;
3813 }
3814 
3815 /*
3816  * Determine if an IOCB failed because of a link event or firmware reset.
3817  */
3818 
3819 static inline int
lpfc_error_lost_link(IOCB_t * iocbp)3820 lpfc_error_lost_link(IOCB_t *iocbp)
3821 {
3822 	return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3823 		(iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3824 		 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3825 		 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3826 }
3827 
3828 #define MENLO_TRANSPORT_TYPE 0xfe
3829 #define MENLO_CONTEXT 0
3830 #define MENLO_PU 3
3831 #define MENLO_TIMEOUT 30
3832 #define SETVAR_MLOMNT 0x103107
3833 #define SETVAR_MLORST 0x103007
3834 
3835 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
3836