1 /* 2 * arch/arm/mach-pnx4008/include/mach/irqs.h 3 * 4 * PNX4008 IRQ controller driver - header file 5 * 6 * Author: Dmitry Chigirev <source@mvista.com> 7 * 8 * 2005 (c) MontaVista Software, Inc. This file is licensed under 9 * the terms of the GNU General Public License version 2. This program 10 * is licensed "as is" without any warranty of any kind, whether express 11 * or implied. 12 */ 13 #ifndef __PNX4008_IRQS_h__ 14 #define __PNX4008_IRQS_h__ 15 16 #define NR_IRQS 96 17 18 /*Manual: table 259, page 199*/ 19 20 /*SUB2 Interrupt Routing (SIC2)*/ 21 22 #define SIC2_BASE_INT 64 23 24 #define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */ 25 #define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */ 26 #define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */ 27 #define GPI_06_INT 92 28 #define GPI_05_INT 91 29 #define GPI_04_INT 90 30 #define GPI_03_INT 89 31 #define GPI_02_INT 88 32 #define GPI_01_INT 87 33 #define GPI_00_INT 86 34 #define BT_CLKREQ_INT 85 35 #define SPI1_DATIN_INT 84 36 #define U5_RX_INT 83 37 #define SDIO_INT_N 82 38 #define CAM_HS_INT 81 39 #define CAM_VS_INT 80 40 #define GPI_07_INT 79 41 #define DISP_SYNC_INT 78 42 #define DSP_INT8 77 43 #define U7_HCTS_INT 76 44 #define GPI_10_INT 75 45 #define GPI_09_INT 74 46 #define GPI_08_INT 73 47 #define DSP_INT7 72 48 #define U2_HCTS_INT 71 49 #define SPI2_DATIN_INT 70 50 #define GPIO_05_INT 69 51 #define GPIO_04_INT 68 52 #define GPIO_03_INT 67 53 #define GPIO_02_INT 66 54 #define GPIO_01_INT 65 55 #define GPIO_00_INT 64 56 57 /*Manual: table 258, page 198*/ 58 59 /*SUB1 Interrupt Routing (SIC1)*/ 60 61 #define SIC1_BASE_INT 32 62 63 #define USB_I2C_INT 63 64 #define USB_DEV_HP_INT 62 65 #define USB_DEV_LP_INT 61 66 #define USB_DEV_DMA_INT 60 67 #define USB_HOST_INT 59 68 #define USB_OTG_ATX_INT_N 58 69 #define USB_OTG_TIMER_INT 57 70 #define SW_INT 56 71 #define SPI1_INT 55 72 #define KEY_IRQ 54 73 #define DSP_M_INT 53 74 #define RTC_INT 52 75 #define I2C_1_INT 51 76 #define I2C_2_INT 50 77 #define PLL1_LOCK_INT 49 78 #define PLL2_LOCK_INT 48 79 #define PLL3_LOCK_INT 47 80 #define PLL4_LOCK_INT 46 81 #define PLL5_LOCK_INT 45 82 #define SPI2_INT 44 83 #define DSP_INT1 43 84 #define DSP_INT2 42 85 #define DSP_TDM_INT2 41 86 #define TS_AUX_INT 40 87 #define TS_IRQ 39 88 #define TS_P_INT 38 89 #define UOUT1_TO_PAD_INT 37 90 #define GPI_11_INT 36 91 #define DSP_INT4 35 92 #define JTAG_COMM_RX_INT 34 93 #define JTAG_COMM_TX_INT 33 94 #define DSP_INT3 32 95 96 /*Manual: table 257, page 197*/ 97 98 /*MAIN Interrupt Routing*/ 99 100 #define MAIN_BASE_INT 0 101 102 #define SUB2_FIQ_N 31 /*active low */ 103 #define SUB1_FIQ_N 30 /*active low */ 104 #define JPEG_INT 29 105 #define DMA_INT 28 106 #define MSTIMER_INT 27 107 #define IIR1_INT 26 108 #define IIR2_INT 25 109 #define IIR7_INT 24 110 #define DSP_TDM_INT0 23 111 #define DSP_TDM_INT1 22 112 #define DSP_P_INT 21 113 #define DSP_INT0 20 114 #define DUM_INT 19 115 #define UOUT0_TO_PAD_INT 18 116 #define MP4_ENC_INT 17 117 #define MP4_DEC_INT 16 118 #define SD0_INT 15 119 #define MBX_INT 14 120 #define SD1_INT 13 121 #define MS_INT_N 12 122 #define FLASH_INT 11 /*NAND*/ 123 #define IIR6_INT 10 124 #define IIR5_INT 9 125 #define IIR4_INT 8 126 #define IIR3_INT 7 127 #define WATCH_INT 6 128 #define HSTIMER_INT 5 129 #define ARCH_TIMER_IRQ HSTIMER_INT 130 #define CAM_INT 4 131 #define PRNG_INT 3 132 #define CRYPTO_INT 2 133 #define SUB2_IRQ_N 1 /*active low */ 134 #define SUB1_IRQ_N 0 /*active low */ 135 136 #define PNX4008_IRQ_TYPES \ 137 { /*IRQ #'s: */ \ 138 IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \ 139 IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \ 140 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \ 141 IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \ 142 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \ 143 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \ 144 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \ 145 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \ 146 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \ 147 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \ 148 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \ 149 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \ 150 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \ 151 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \ 152 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \ 153 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \ 154 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \ 155 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \ 156 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \ 157 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \ 158 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \ 159 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \ 160 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \ 161 IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \ 162 } 163 164 /* Start Enable Pin Interrupts - table 58 page 66 */ 165 166 #define SE_PIN_BASE_INT 32 167 168 #define SE_U7_RX_INT 63 169 #define SE_U7_HCTS_INT 62 170 #define SE_BT_CLKREQ_INT 61 171 #define SE_U6_IRRX_INT 60 172 /*59 unused*/ 173 #define SE_U5_RX_INT 58 174 #define SE_GPI_11_INT 57 175 #define SE_U3_RX_INT 56 176 #define SE_U2_HCTS_INT 55 177 #define SE_U2_RX_INT 54 178 #define SE_U1_RX_INT 53 179 #define SE_DISP_SYNC_INT 52 180 /*51 unused*/ 181 #define SE_SDIO_INT_N 50 182 #define SE_MSDIO_START_INT 49 183 #define SE_GPI_06_INT 48 184 #define SE_GPI_05_INT 47 185 #define SE_GPI_04_INT 46 186 #define SE_GPI_03_INT 45 187 #define SE_GPI_02_INT 44 188 #define SE_GPI_01_INT 43 189 #define SE_GPI_00_INT 42 190 #define SE_SYSCLKEN_PIN_INT 41 191 #define SE_SPI1_DATAIN_INT 40 192 #define SE_GPI_07_INT 39 193 #define SE_SPI2_DATAIN_INT 38 194 #define SE_GPI_10_INT 37 195 #define SE_GPI_09_INT 36 196 #define SE_GPI_08_INT 35 197 /*34-32 unused*/ 198 199 /* Start Enable Internal Interrupts - table 57 page 65 */ 200 201 #define SE_INT_BASE_INT 0 202 203 #define SE_TS_IRQ 31 204 #define SE_TS_P_INT 30 205 #define SE_TS_AUX_INT 29 206 /*27-28 unused*/ 207 #define SE_USB_AHB_NEED_CLK_INT 26 208 #define SE_MSTIMER_INT 25 209 #define SE_RTC_INT 24 210 #define SE_USB_NEED_CLK_INT 23 211 #define SE_USB_INT 22 212 #define SE_USB_I2C_INT 21 213 #define SE_USB_OTG_TIMER_INT 20 214 215 #endif /* __PNX4008_IRQS_h__ */ 216