1 #ifndef _ISP1760_HCD_H_ 2 #define _ISP1760_HCD_H_ 3 4 /* exports for if */ 5 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, 6 int irq, unsigned long irqflags, 7 int rst_gpio, 8 struct device *dev, const char *busname, 9 unsigned int devflags); 10 int init_kmem_once(void); 11 void deinit_kmem_cache(void); 12 13 /* EHCI capability registers */ 14 #define HC_CAPLENGTH 0x00 15 #define HC_HCSPARAMS 0x04 16 #define HC_HCCPARAMS 0x08 17 18 /* EHCI operational registers */ 19 #define HC_USBCMD 0x20 20 #define HC_USBSTS 0x24 21 #define HC_FRINDEX 0x2c 22 #define HC_CONFIGFLAG 0x60 23 #define HC_PORTSC1 0x64 24 #define HC_ISO_PTD_DONEMAP_REG 0x130 25 #define HC_ISO_PTD_SKIPMAP_REG 0x134 26 #define HC_ISO_PTD_LASTPTD_REG 0x138 27 #define HC_INT_PTD_DONEMAP_REG 0x140 28 #define HC_INT_PTD_SKIPMAP_REG 0x144 29 #define HC_INT_PTD_LASTPTD_REG 0x148 30 #define HC_ATL_PTD_DONEMAP_REG 0x150 31 #define HC_ATL_PTD_SKIPMAP_REG 0x154 32 #define HC_ATL_PTD_LASTPTD_REG 0x158 33 34 /* Configuration Register */ 35 #define HC_HW_MODE_CTRL 0x300 36 #define ALL_ATX_RESET (1 << 31) 37 #define HW_ANA_DIGI_OC (1 << 15) 38 #define HW_DATA_BUS_32BIT (1 << 8) 39 #define HW_DACK_POL_HIGH (1 << 6) 40 #define HW_DREQ_POL_HIGH (1 << 5) 41 #define HW_INTR_HIGH_ACT (1 << 2) 42 #define HW_INTR_EDGE_TRIG (1 << 1) 43 #define HW_GLOBAL_INTR_EN (1 << 0) 44 45 #define HC_CHIP_ID_REG 0x304 46 #define HC_SCRATCH_REG 0x308 47 48 #define HC_RESET_REG 0x30c 49 #define SW_RESET_RESET_HC (1 << 1) 50 #define SW_RESET_RESET_ALL (1 << 0) 51 52 #define HC_BUFFER_STATUS_REG 0x334 53 #define ISO_BUF_FILL (1 << 2) 54 #define INT_BUF_FILL (1 << 1) 55 #define ATL_BUF_FILL (1 << 0) 56 57 #define HC_MEMORY_REG 0x33c 58 #define ISP_BANK(x) ((x) << 16) 59 60 #define HC_PORT1_CTRL 0x374 61 #define PORT1_POWER (3 << 3) 62 #define PORT1_INIT1 (1 << 7) 63 #define PORT1_INIT2 (1 << 23) 64 #define HW_OTG_CTRL_SET 0x374 65 #define HW_OTG_CTRL_CLR 0x376 66 67 /* Interrupt Register */ 68 #define HC_INTERRUPT_REG 0x310 69 70 #define HC_INTERRUPT_ENABLE 0x314 71 #define HC_ISO_INT (1 << 9) 72 #define HC_ATL_INT (1 << 8) 73 #define HC_INTL_INT (1 << 7) 74 #define HC_EOT_INT (1 << 3) 75 #define HC_SOT_INT (1 << 1) 76 #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT) 77 78 #define HC_ISO_IRQ_MASK_OR_REG 0x318 79 #define HC_INT_IRQ_MASK_OR_REG 0x31C 80 #define HC_ATL_IRQ_MASK_OR_REG 0x320 81 #define HC_ISO_IRQ_MASK_AND_REG 0x324 82 #define HC_INT_IRQ_MASK_AND_REG 0x328 83 #define HC_ATL_IRQ_MASK_AND_REG 0x32C 84 85 /* urb state*/ 86 #define DELETE_URB (0x0008) 87 #define NO_TRANSFER_ACTIVE (0xffffffff) 88 89 /* Philips Proprietary Transfer Descriptor (PTD) */ 90 typedef __u32 __bitwise __dw; 91 struct ptd { 92 __dw dw0; 93 __dw dw1; 94 __dw dw2; 95 __dw dw3; 96 __dw dw4; 97 __dw dw5; 98 __dw dw6; 99 __dw dw7; 100 }; 101 #define PTD_OFFSET 0x0400 102 #define ISO_PTD_OFFSET 0x0400 103 #define INT_PTD_OFFSET 0x0800 104 #define ATL_PTD_OFFSET 0x0c00 105 #define PAYLOAD_OFFSET 0x1000 106 107 struct slotinfo { 108 struct isp1760_qh *qh; 109 struct isp1760_qtd *qtd; 110 unsigned long timestamp; 111 }; 112 113 114 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 115 struct isp1760_qtd *qtd); 116 117 /* 118 * Device flags that can vary from board to board. All of these 119 * indicate the most "atypical" case, so that a devflags of 0 is 120 * a sane default configuration. 121 */ 122 #define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */ 123 #define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */ 124 #define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */ 125 #define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */ 126 #define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */ 127 #define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */ 128 #define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */ 129 #define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */ 130 #define ISP1760_FLAG_RESET_ACTIVE_HIGH 0x80000000 /* RESET GPIO active high */ 131 132 /* chip memory management */ 133 struct memory_chunk { 134 unsigned int start; 135 unsigned int size; 136 unsigned int free; 137 }; 138 139 /* 140 * 60kb divided in: 141 * - 32 blocks @ 256 bytes 142 * - 20 blocks @ 1024 bytes 143 * - 4 blocks @ 8192 bytes 144 */ 145 146 #define BLOCK_1_NUM 32 147 #define BLOCK_2_NUM 20 148 #define BLOCK_3_NUM 4 149 150 #define BLOCK_1_SIZE 256 151 #define BLOCK_2_SIZE 1024 152 #define BLOCK_3_SIZE 8192 153 #define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) 154 #define MAX_PAYLOAD_SIZE BLOCK_3_SIZE 155 #define PAYLOAD_AREA_SIZE 0xf000 156 157 /* ATL */ 158 /* DW0 */ 159 #define DW0_VALID_BIT 1 160 #define FROM_DW0_VALID(x) ((x) & 0x01) 161 #define TO_DW0_LENGTH(x) (((u32) x) << 3) 162 #define TO_DW0_MAXPACKET(x) (((u32) x) << 18) 163 #define TO_DW0_MULTI(x) (((u32) x) << 29) 164 #define TO_DW0_ENDPOINT(x) (((u32) x) << 31) 165 /* DW1 */ 166 #define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3) 167 #define TO_DW1_PID_TOKEN(x) (((u32) x) << 10) 168 #define DW1_TRANS_BULK ((u32) 2 << 12) 169 #define DW1_TRANS_INT ((u32) 3 << 12) 170 #define DW1_TRANS_SPLIT ((u32) 1 << 14) 171 #define DW1_SE_USB_LOSPEED ((u32) 2 << 16) 172 #define TO_DW1_PORT_NUM(x) (((u32) x) << 18) 173 #define TO_DW1_HUB_NUM(x) (((u32) x) << 25) 174 /* DW2 */ 175 #define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8) 176 #define TO_DW2_RL(x) ((x) << 25) 177 #define FROM_DW2_RL(x) (((x) >> 25) & 0xf) 178 /* DW3 */ 179 #define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff) 180 #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff) 181 #define TO_DW3_NAKCOUNT(x) ((x) << 19) 182 #define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf) 183 #define TO_DW3_CERR(x) ((x) << 23) 184 #define FROM_DW3_CERR(x) (((x) >> 23) & 0x3) 185 #define TO_DW3_DATA_TOGGLE(x) ((x) << 25) 186 #define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1) 187 #define TO_DW3_PING(x) ((x) << 26) 188 #define FROM_DW3_PING(x) (((x) >> 26) & 0x1) 189 #define DW3_ERROR_BIT (1 << 28) 190 #define DW3_BABBLE_BIT (1 << 29) 191 #define DW3_HALT_BIT (1 << 30) 192 #define DW3_ACTIVE_BIT (1 << 31) 193 #define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01) 194 195 #define INT_UNDERRUN (1 << 2) 196 #define INT_BABBLE (1 << 1) 197 #define INT_EXACT (1 << 0) 198 199 #define SETUP_PID (2) 200 #define IN_PID (1) 201 #define OUT_PID (0) 202 203 /* Errata 1 */ 204 #define RL_COUNTER (0) 205 #define NAK_COUNTER (0) 206 #define ERR_COUNTER (2) 207 208 #endif /* _ISP1760_HCD_H_ */ 209