1 /* 2 * arch/arm/plat-omap/include/mach/hardware.h 3 * 4 * Hardware definitions for TI OMAP processors and boards 5 * 6 * NOTE: Please put device driver specific defines into a separate header 7 * file for each driver. 8 * 9 * Copyright (C) 2001 RidgeRun, Inc. 10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> 11 * 12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> 13 * and Dirk Behme <dirk.behme@de.bosch.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * You should have received a copy of the GNU General Public License along 32 * with this program; if not, write to the Free Software Foundation, Inc., 33 * 675 Mass Ave, Cambridge, MA 02139, USA. 34 */ 35 36 #ifndef __ASM_ARCH_OMAP_HARDWARE_H 37 #define __ASM_ARCH_OMAP_HARDWARE_H 38 39 #include <asm/sizes.h> 40 #ifndef __ASSEMBLER__ 41 #include <asm/types.h> 42 #include <plat/cpu.h> 43 #endif 44 #include <plat/serial.h> 45 46 /* 47 * --------------------------------------------------------------------------- 48 * Common definitions for all OMAP processors 49 * NOTE: Put all processor or board specific parts to the special header 50 * files. 51 * --------------------------------------------------------------------------- 52 */ 53 54 /* 55 * ---------------------------------------------------------------------------- 56 * Timers 57 * ---------------------------------------------------------------------------- 58 */ 59 #define OMAP_MPU_TIMER1_BASE (0xfffec500) 60 #define OMAP_MPU_TIMER2_BASE (0xfffec600) 61 #define OMAP_MPU_TIMER3_BASE (0xfffec700) 62 #define MPU_TIMER_FREE (1 << 6) 63 #define MPU_TIMER_CLOCK_ENABLE (1 << 5) 64 #define MPU_TIMER_AR (1 << 1) 65 #define MPU_TIMER_ST (1 << 0) 66 67 /* 68 * ---------------------------------------------------------------------------- 69 * Clocks 70 * ---------------------------------------------------------------------------- 71 */ 72 #define CLKGEN_REG_BASE (0xfffece00) 73 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) 74 #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) 75 #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) 76 #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) 77 #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) 78 #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) 79 #define ARM_SYSST (CLKGEN_REG_BASE + 0x18) 80 #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) 81 82 #define CK_RATEF 1 83 #define CK_IDLEF 2 84 #define CK_ENABLEF 4 85 #define CK_SELECTF 8 86 #define SETARM_IDLE_SHIFT 87 88 /* DPLL control registers */ 89 #define DPLL_CTL (0xfffecf00) 90 91 /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ 92 #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) 93 #define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) 94 #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) 95 #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) 96 #define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) 97 98 /* 99 * --------------------------------------------------------------------------- 100 * UPLD 101 * --------------------------------------------------------------------------- 102 */ 103 #define ULPD_REG_BASE (0xfffe0800) 104 #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) 105 #define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) 106 #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) 107 # define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ 108 # define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ 109 #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) 110 # define SOFT_UDC_REQ (1 << 4) 111 # define SOFT_USB_CLK_REQ (1 << 3) 112 # define SOFT_DPLL_REQ (1 << 0) 113 #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) 114 #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) 115 #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) 116 #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) 117 #define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) 118 # define DIS_MMC2_DPLL_REQ (1 << 11) 119 # define DIS_MMC1_DPLL_REQ (1 << 10) 120 # define DIS_UART3_DPLL_REQ (1 << 9) 121 # define DIS_UART2_DPLL_REQ (1 << 8) 122 # define DIS_UART1_DPLL_REQ (1 << 7) 123 # define DIS_USB_HOST_DPLL_REQ (1 << 6) 124 #define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) 125 #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) 126 127 /* 128 * --------------------------------------------------------------------------- 129 * Watchdog timer 130 * --------------------------------------------------------------------------- 131 */ 132 133 /* Watchdog timer within the OMAP3.2 gigacell */ 134 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800) 135 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) 136 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) 137 #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) 138 #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) 139 140 /* 141 * --------------------------------------------------------------------------- 142 * Interrupts 143 * --------------------------------------------------------------------------- 144 */ 145 #ifdef CONFIG_ARCH_OMAP1 146 147 /* 148 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c 149 * or something similar.. -- PFM. 150 */ 151 152 #define OMAP_IH1_BASE 0xfffecb00 153 #define OMAP_IH2_BASE 0xfffe0000 154 155 #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) 156 #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) 157 #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) 158 #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) 159 #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) 160 #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) 161 #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) 162 163 #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) 164 #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) 165 #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) 166 #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) 167 #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) 168 #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) 169 #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) 170 171 #define IRQ_ITR_REG_OFFSET 0x00 172 #define IRQ_MIR_REG_OFFSET 0x04 173 #define IRQ_SIR_IRQ_REG_OFFSET 0x10 174 #define IRQ_SIR_FIQ_REG_OFFSET 0x14 175 #define IRQ_CONTROL_REG_OFFSET 0x18 176 #define IRQ_ISR_REG_OFFSET 0x9c 177 #define IRQ_ILR0_REG_OFFSET 0x1c 178 #define IRQ_GMR_REG_OFFSET 0xa0 179 180 #endif 181 182 /* 183 * ---------------------------------------------------------------------------- 184 * System control registers 185 * ---------------------------------------------------------------------------- 186 */ 187 #define MOD_CONF_CTRL_0 0xfffe1080 188 #define MOD_CONF_CTRL_1 0xfffe1110 189 190 /* 191 * ---------------------------------------------------------------------------- 192 * Pin multiplexing registers 193 * ---------------------------------------------------------------------------- 194 */ 195 #define FUNC_MUX_CTRL_0 0xfffe1000 196 #define FUNC_MUX_CTRL_1 0xfffe1004 197 #define FUNC_MUX_CTRL_2 0xfffe1008 198 #define COMP_MODE_CTRL_0 0xfffe100c 199 #define FUNC_MUX_CTRL_3 0xfffe1010 200 #define FUNC_MUX_CTRL_4 0xfffe1014 201 #define FUNC_MUX_CTRL_5 0xfffe1018 202 #define FUNC_MUX_CTRL_6 0xfffe101C 203 #define FUNC_MUX_CTRL_7 0xfffe1020 204 #define FUNC_MUX_CTRL_8 0xfffe1024 205 #define FUNC_MUX_CTRL_9 0xfffe1028 206 #define FUNC_MUX_CTRL_A 0xfffe102C 207 #define FUNC_MUX_CTRL_B 0xfffe1030 208 #define FUNC_MUX_CTRL_C 0xfffe1034 209 #define FUNC_MUX_CTRL_D 0xfffe1038 210 #define PULL_DWN_CTRL_0 0xfffe1040 211 #define PULL_DWN_CTRL_1 0xfffe1044 212 #define PULL_DWN_CTRL_2 0xfffe1048 213 #define PULL_DWN_CTRL_3 0xfffe104c 214 #define PULL_DWN_CTRL_4 0xfffe10ac 215 216 /* OMAP-1610 specific multiplexing registers */ 217 #define FUNC_MUX_CTRL_E 0xfffe1090 218 #define FUNC_MUX_CTRL_F 0xfffe1094 219 #define FUNC_MUX_CTRL_10 0xfffe1098 220 #define FUNC_MUX_CTRL_11 0xfffe109c 221 #define FUNC_MUX_CTRL_12 0xfffe10a0 222 #define PU_PD_SEL_0 0xfffe10b4 223 #define PU_PD_SEL_1 0xfffe10b8 224 #define PU_PD_SEL_2 0xfffe10bc 225 #define PU_PD_SEL_3 0xfffe10c0 226 #define PU_PD_SEL_4 0xfffe10c4 227 228 /* Timer32K for 1610 and 1710*/ 229 #define OMAP_TIMER32K_BASE 0xFFFBC400 230 231 /* 232 * --------------------------------------------------------------------------- 233 * TIPB bus interface 234 * --------------------------------------------------------------------------- 235 */ 236 #define TIPB_PUBLIC_CNTL_BASE 0xfffed300 237 #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) 238 #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 239 #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) 240 241 /* 242 * ---------------------------------------------------------------------------- 243 * MPUI interface 244 * ---------------------------------------------------------------------------- 245 */ 246 #define MPUI_BASE (0xfffec900) 247 #define MPUI_CTRL (MPUI_BASE + 0x0) 248 #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) 249 #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) 250 #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) 251 #define MPUI_STATUS_REG (MPUI_BASE + 0x10) 252 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14) 253 #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) 254 #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) 255 256 /* 257 * ---------------------------------------------------------------------------- 258 * LED Pulse Generator 259 * ---------------------------------------------------------------------------- 260 */ 261 #define OMAP_LPG1_BASE 0xfffbd000 262 #define OMAP_LPG2_BASE 0xfffbd800 263 #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) 264 #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) 265 #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) 266 #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) 267 268 /* 269 * ---------------------------------------------------------------------------- 270 * Pulse-Width Light 271 * ---------------------------------------------------------------------------- 272 */ 273 #define OMAP_PWL_BASE 0xfffb5800 274 #define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) 275 #define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) 276 277 /* 278 * --------------------------------------------------------------------------- 279 * Processor specific defines 280 * --------------------------------------------------------------------------- 281 */ 282 283 #include <plat/omap7xx.h> 284 #include <plat/omap1510.h> 285 #include <plat/omap16xx.h> 286 #include <plat/omap24xx.h> 287 #include <plat/omap34xx.h> 288 #include <plat/omap44xx.h> 289 #include <plat/ti81xx.h> 290 #include <plat/am33xx.h> 291 292 #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ 293