1 /*
2 * VPIF header file
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #ifndef VPIF_H
17 #define VPIF_H
18
19 #include <linux/io.h>
20 #include <linux/videodev2.h>
21 #include <media/davinci/vpif_types.h>
22
23 /* Maximum channel allowed */
24 #define VPIF_NUM_CHANNELS (4)
25 #define VPIF_CAPTURE_NUM_CHANNELS (2)
26 #define VPIF_DISPLAY_NUM_CHANNELS (2)
27
28 /* Macros to read/write registers */
29 extern void __iomem *vpif_base;
30 extern spinlock_t vpif_lock;
31
32 #define regr(reg) readl((reg) + vpif_base)
33 #define regw(value, reg) writel(value, (reg + vpif_base))
34
35 /* Register Address Offsets */
36 #define VPIF_PID (0x0000)
37 #define VPIF_CH0_CTRL (0x0004)
38 #define VPIF_CH1_CTRL (0x0008)
39 #define VPIF_CH2_CTRL (0x000C)
40 #define VPIF_CH3_CTRL (0x0010)
41
42 #define VPIF_INTEN (0x0020)
43 #define VPIF_INTEN_SET (0x0024)
44 #define VPIF_INTEN_CLR (0x0028)
45 #define VPIF_STATUS (0x002C)
46 #define VPIF_STATUS_CLR (0x0030)
47 #define VPIF_EMULATION_CTRL (0x0034)
48 #define VPIF_REQ_SIZE (0x0038)
49
50 #define VPIF_CH0_TOP_STRT_ADD_LUMA (0x0040)
51 #define VPIF_CH0_BTM_STRT_ADD_LUMA (0x0044)
52 #define VPIF_CH0_TOP_STRT_ADD_CHROMA (0x0048)
53 #define VPIF_CH0_BTM_STRT_ADD_CHROMA (0x004c)
54 #define VPIF_CH0_TOP_STRT_ADD_HANC (0x0050)
55 #define VPIF_CH0_BTM_STRT_ADD_HANC (0x0054)
56 #define VPIF_CH0_TOP_STRT_ADD_VANC (0x0058)
57 #define VPIF_CH0_BTM_STRT_ADD_VANC (0x005c)
58 #define VPIF_CH0_SP_CFG (0x0060)
59 #define VPIF_CH0_IMG_ADD_OFST (0x0064)
60 #define VPIF_CH0_HANC_ADD_OFST (0x0068)
61 #define VPIF_CH0_H_CFG (0x006c)
62 #define VPIF_CH0_V_CFG_00 (0x0070)
63 #define VPIF_CH0_V_CFG_01 (0x0074)
64 #define VPIF_CH0_V_CFG_02 (0x0078)
65 #define VPIF_CH0_V_CFG_03 (0x007c)
66
67 #define VPIF_CH1_TOP_STRT_ADD_LUMA (0x0080)
68 #define VPIF_CH1_BTM_STRT_ADD_LUMA (0x0084)
69 #define VPIF_CH1_TOP_STRT_ADD_CHROMA (0x0088)
70 #define VPIF_CH1_BTM_STRT_ADD_CHROMA (0x008c)
71 #define VPIF_CH1_TOP_STRT_ADD_HANC (0x0090)
72 #define VPIF_CH1_BTM_STRT_ADD_HANC (0x0094)
73 #define VPIF_CH1_TOP_STRT_ADD_VANC (0x0098)
74 #define VPIF_CH1_BTM_STRT_ADD_VANC (0x009c)
75 #define VPIF_CH1_SP_CFG (0x00a0)
76 #define VPIF_CH1_IMG_ADD_OFST (0x00a4)
77 #define VPIF_CH1_HANC_ADD_OFST (0x00a8)
78 #define VPIF_CH1_H_CFG (0x00ac)
79 #define VPIF_CH1_V_CFG_00 (0x00b0)
80 #define VPIF_CH1_V_CFG_01 (0x00b4)
81 #define VPIF_CH1_V_CFG_02 (0x00b8)
82 #define VPIF_CH1_V_CFG_03 (0x00bc)
83
84 #define VPIF_CH2_TOP_STRT_ADD_LUMA (0x00c0)
85 #define VPIF_CH2_BTM_STRT_ADD_LUMA (0x00c4)
86 #define VPIF_CH2_TOP_STRT_ADD_CHROMA (0x00c8)
87 #define VPIF_CH2_BTM_STRT_ADD_CHROMA (0x00cc)
88 #define VPIF_CH2_TOP_STRT_ADD_HANC (0x00d0)
89 #define VPIF_CH2_BTM_STRT_ADD_HANC (0x00d4)
90 #define VPIF_CH2_TOP_STRT_ADD_VANC (0x00d8)
91 #define VPIF_CH2_BTM_STRT_ADD_VANC (0x00dc)
92 #define VPIF_CH2_SP_CFG (0x00e0)
93 #define VPIF_CH2_IMG_ADD_OFST (0x00e4)
94 #define VPIF_CH2_HANC_ADD_OFST (0x00e8)
95 #define VPIF_CH2_H_CFG (0x00ec)
96 #define VPIF_CH2_V_CFG_00 (0x00f0)
97 #define VPIF_CH2_V_CFG_01 (0x00f4)
98 #define VPIF_CH2_V_CFG_02 (0x00f8)
99 #define VPIF_CH2_V_CFG_03 (0x00fc)
100 #define VPIF_CH2_HANC0_STRT (0x0100)
101 #define VPIF_CH2_HANC0_SIZE (0x0104)
102 #define VPIF_CH2_HANC1_STRT (0x0108)
103 #define VPIF_CH2_HANC1_SIZE (0x010c)
104 #define VPIF_CH2_VANC0_STRT (0x0110)
105 #define VPIF_CH2_VANC0_SIZE (0x0114)
106 #define VPIF_CH2_VANC1_STRT (0x0118)
107 #define VPIF_CH2_VANC1_SIZE (0x011c)
108
109 #define VPIF_CH3_TOP_STRT_ADD_LUMA (0x0140)
110 #define VPIF_CH3_BTM_STRT_ADD_LUMA (0x0144)
111 #define VPIF_CH3_TOP_STRT_ADD_CHROMA (0x0148)
112 #define VPIF_CH3_BTM_STRT_ADD_CHROMA (0x014c)
113 #define VPIF_CH3_TOP_STRT_ADD_HANC (0x0150)
114 #define VPIF_CH3_BTM_STRT_ADD_HANC (0x0154)
115 #define VPIF_CH3_TOP_STRT_ADD_VANC (0x0158)
116 #define VPIF_CH3_BTM_STRT_ADD_VANC (0x015c)
117 #define VPIF_CH3_SP_CFG (0x0160)
118 #define VPIF_CH3_IMG_ADD_OFST (0x0164)
119 #define VPIF_CH3_HANC_ADD_OFST (0x0168)
120 #define VPIF_CH3_H_CFG (0x016c)
121 #define VPIF_CH3_V_CFG_00 (0x0170)
122 #define VPIF_CH3_V_CFG_01 (0x0174)
123 #define VPIF_CH3_V_CFG_02 (0x0178)
124 #define VPIF_CH3_V_CFG_03 (0x017c)
125 #define VPIF_CH3_HANC0_STRT (0x0180)
126 #define VPIF_CH3_HANC0_SIZE (0x0184)
127 #define VPIF_CH3_HANC1_STRT (0x0188)
128 #define VPIF_CH3_HANC1_SIZE (0x018c)
129 #define VPIF_CH3_VANC0_STRT (0x0190)
130 #define VPIF_CH3_VANC0_SIZE (0x0194)
131 #define VPIF_CH3_VANC1_STRT (0x0198)
132 #define VPIF_CH3_VANC1_SIZE (0x019c)
133
134 #define VPIF_IODFT_CTRL (0x01c0)
135
136 /* Functions for bit Manipulation */
vpif_set_bit(u32 reg,u32 bit)137 static inline void vpif_set_bit(u32 reg, u32 bit)
138 {
139 regw((regr(reg)) | (0x01 << bit), reg);
140 }
141
vpif_clr_bit(u32 reg,u32 bit)142 static inline void vpif_clr_bit(u32 reg, u32 bit)
143 {
144 regw(((regr(reg)) & ~(0x01 << bit)), reg);
145 }
146
147 /* Macro for Generating mask */
148 #ifdef GENERATE_MASK
149 #undef GENERATE_MASK
150 #endif
151
152 #define GENERATE_MASK(bits, pos) \
153 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
154
155 /* Bit positions in the channel control registers */
156 #define VPIF_CH_DATA_MODE_BIT (2)
157 #define VPIF_CH_YC_MUX_BIT (3)
158 #define VPIF_CH_SDR_FMT_BIT (4)
159 #define VPIF_CH_HANC_EN_BIT (8)
160 #define VPIF_CH_VANC_EN_BIT (9)
161
162 #define VPIF_CAPTURE_CH_NIP (10)
163 #define VPIF_DISPLAY_CH_NIP (11)
164
165 #define VPIF_DISPLAY_PIX_EN_BIT (10)
166
167 #define VPIF_CH_INPUT_FIELD_FRAME_BIT (12)
168
169 #define VPIF_CH_FID_POLARITY_BIT (15)
170 #define VPIF_CH_V_VALID_POLARITY_BIT (14)
171 #define VPIF_CH_H_VALID_POLARITY_BIT (13)
172 #define VPIF_CH_DATA_WIDTH_BIT (28)
173
174 #define VPIF_CH_CLK_EDGE_CTRL_BIT (31)
175
176 /* Mask various length */
177 #define VPIF_CH_EAVSAV_MASK GENERATE_MASK(13, 0)
178 #define VPIF_CH_LEN_MASK GENERATE_MASK(12, 0)
179 #define VPIF_CH_WIDTH_MASK GENERATE_MASK(13, 0)
180 #define VPIF_CH_LEN_SHIFT (16)
181
182 /* VPIF masks for registers */
183 #define VPIF_REQ_SIZE_MASK (0x1ff)
184
185 /* bit posotion of interrupt vpif_ch_intr register */
186 #define VPIF_INTEN_FRAME_CH0 (0x00000001)
187 #define VPIF_INTEN_FRAME_CH1 (0x00000002)
188 #define VPIF_INTEN_FRAME_CH2 (0x00000004)
189 #define VPIF_INTEN_FRAME_CH3 (0x00000008)
190
191 /* bit position of clock and channel enable in vpif_chn_ctrl register */
192
193 #define VPIF_CH0_CLK_EN (0x00000002)
194 #define VPIF_CH0_EN (0x00000001)
195 #define VPIF_CH1_CLK_EN (0x00000002)
196 #define VPIF_CH1_EN (0x00000001)
197 #define VPIF_CH2_CLK_EN (0x00000002)
198 #define VPIF_CH2_EN (0x00000001)
199 #define VPIF_CH3_CLK_EN (0x00000002)
200 #define VPIF_CH3_EN (0x00000001)
201 #define VPIF_CH_CLK_EN (0x00000002)
202 #define VPIF_CH_EN (0x00000001)
203
204 #define VPIF_INT_TOP (0x00)
205 #define VPIF_INT_BOTTOM (0x01)
206 #define VPIF_INT_BOTH (0x02)
207
208 #define VPIF_CH0_INT_CTRL_SHIFT (6)
209 #define VPIF_CH1_INT_CTRL_SHIFT (6)
210 #define VPIF_CH2_INT_CTRL_SHIFT (6)
211 #define VPIF_CH3_INT_CTRL_SHIFT (6)
212 #define VPIF_CH_INT_CTRL_SHIFT (6)
213
214 /* enabled interrupt on both the fields on vpid_ch0_ctrl register */
215 #define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\
216 (VPIF_INT_BOTH << VPIF_CH0_INT_CTRL_SHIFT)), VPIF_CH0_CTRL))
217
218 /* enabled interrupt on both the fields on vpid_ch1_ctrl register */
219 #define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\
220 (VPIF_INT_BOTH << VPIF_CH1_INT_CTRL_SHIFT)), VPIF_CH1_CTRL))
221
222 /* enabled interrupt on both the fields on vpid_ch0_ctrl register */
223 #define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\
224 (VPIF_INT_BOTH << VPIF_CH2_INT_CTRL_SHIFT)), VPIF_CH2_CTRL))
225
226 /* enabled interrupt on both the fields on vpid_ch1_ctrl register */
227 #define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\
228 (VPIF_INT_BOTH << VPIF_CH3_INT_CTRL_SHIFT)), VPIF_CH3_CTRL))
229
230 #define VPIF_CH_FID_MASK (0x20)
231 #define VPIF_CH_FID_SHIFT (5)
232
233 #define VPIF_NTSC_VBI_START_FIELD0 (1)
234 #define VPIF_NTSC_VBI_START_FIELD1 (263)
235 #define VPIF_PAL_VBI_START_FIELD0 (624)
236 #define VPIF_PAL_VBI_START_FIELD1 (311)
237
238 #define VPIF_NTSC_HBI_START_FIELD0 (1)
239 #define VPIF_NTSC_HBI_START_FIELD1 (263)
240 #define VPIF_PAL_HBI_START_FIELD0 (624)
241 #define VPIF_PAL_HBI_START_FIELD1 (311)
242
243 #define VPIF_NTSC_VBI_COUNT_FIELD0 (20)
244 #define VPIF_NTSC_VBI_COUNT_FIELD1 (19)
245 #define VPIF_PAL_VBI_COUNT_FIELD0 (24)
246 #define VPIF_PAL_VBI_COUNT_FIELD1 (25)
247
248 #define VPIF_NTSC_HBI_COUNT_FIELD0 (263)
249 #define VPIF_NTSC_HBI_COUNT_FIELD1 (262)
250 #define VPIF_PAL_HBI_COUNT_FIELD0 (312)
251 #define VPIF_PAL_HBI_COUNT_FIELD1 (313)
252
253 #define VPIF_NTSC_VBI_SAMPLES_PER_LINE (720)
254 #define VPIF_PAL_VBI_SAMPLES_PER_LINE (720)
255 #define VPIF_NTSC_HBI_SAMPLES_PER_LINE (268)
256 #define VPIF_PAL_HBI_SAMPLES_PER_LINE (280)
257
258 #define VPIF_CH_VANC_EN (0x20)
259 #define VPIF_DMA_REQ_SIZE (0x080)
260 #define VPIF_EMULATION_DISABLE (0x01)
261
262 extern u8 irq_vpif_capture_channel[VPIF_NUM_CHANNELS];
263
264 /* inline function to enable/disable channel0 */
enable_channel0(int enable)265 static inline void enable_channel0(int enable)
266 {
267 if (enable)
268 regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL);
269 else
270 regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL);
271 }
272
273 /* inline function to enable/disable channel1 */
enable_channel1(int enable)274 static inline void enable_channel1(int enable)
275 {
276 if (enable)
277 regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL);
278 else
279 regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL);
280 }
281
282 /* inline function to enable interrupt for channel0 */
channel0_intr_enable(int enable)283 static inline void channel0_intr_enable(int enable)
284 {
285 unsigned long flags;
286
287 spin_lock_irqsave(&vpif_lock, flags);
288
289 if (enable) {
290 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
291 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
292
293 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN);
294 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
295 VPIF_INTEN_SET);
296 } else {
297 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN);
298 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
299 VPIF_INTEN_SET);
300 }
301 spin_unlock_irqrestore(&vpif_lock, flags);
302 }
303
304 /* inline function to enable interrupt for channel1 */
channel1_intr_enable(int enable)305 static inline void channel1_intr_enable(int enable)
306 {
307 unsigned long flags;
308
309 spin_lock_irqsave(&vpif_lock, flags);
310
311 if (enable) {
312 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
313 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
314
315 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN);
316 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
317 VPIF_INTEN_SET);
318 } else {
319 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN);
320 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
321 VPIF_INTEN_SET);
322 }
323 spin_unlock_irqrestore(&vpif_lock, flags);
324 }
325
326 /* inline function to set buffer addresses in case of Y/C non mux mode */
ch0_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)327 static inline void ch0_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,
328 unsigned long btm_strt_luma,
329 unsigned long top_strt_chroma,
330 unsigned long btm_strt_chroma)
331 {
332 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
333 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
334 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
335 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
336 }
337
338 /* inline function to set buffer addresses in VPIF registers for video data */
ch0_set_videobuf_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)339 static inline void ch0_set_videobuf_addr(unsigned long top_strt_luma,
340 unsigned long btm_strt_luma,
341 unsigned long top_strt_chroma,
342 unsigned long btm_strt_chroma)
343 {
344 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
345 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
346 regw(top_strt_chroma, VPIF_CH0_TOP_STRT_ADD_CHROMA);
347 regw(btm_strt_chroma, VPIF_CH0_BTM_STRT_ADD_CHROMA);
348 }
349
ch1_set_videobuf_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)350 static inline void ch1_set_videobuf_addr(unsigned long top_strt_luma,
351 unsigned long btm_strt_luma,
352 unsigned long top_strt_chroma,
353 unsigned long btm_strt_chroma)
354 {
355
356 regw(top_strt_luma, VPIF_CH1_TOP_STRT_ADD_LUMA);
357 regw(btm_strt_luma, VPIF_CH1_BTM_STRT_ADD_LUMA);
358 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
359 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
360 }
361
ch0_set_vbi_addr(unsigned long top_vbi,unsigned long btm_vbi,unsigned long a,unsigned long b)362 static inline void ch0_set_vbi_addr(unsigned long top_vbi,
363 unsigned long btm_vbi, unsigned long a, unsigned long b)
364 {
365 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_VANC);
366 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_VANC);
367 }
368
ch0_set_hbi_addr(unsigned long top_vbi,unsigned long btm_vbi,unsigned long a,unsigned long b)369 static inline void ch0_set_hbi_addr(unsigned long top_vbi,
370 unsigned long btm_vbi, unsigned long a, unsigned long b)
371 {
372 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_HANC);
373 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_HANC);
374 }
375
ch1_set_vbi_addr(unsigned long top_vbi,unsigned long btm_vbi,unsigned long a,unsigned long b)376 static inline void ch1_set_vbi_addr(unsigned long top_vbi,
377 unsigned long btm_vbi, unsigned long a, unsigned long b)
378 {
379 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_VANC);
380 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_VANC);
381 }
382
ch1_set_hbi_addr(unsigned long top_vbi,unsigned long btm_vbi,unsigned long a,unsigned long b)383 static inline void ch1_set_hbi_addr(unsigned long top_vbi,
384 unsigned long btm_vbi, unsigned long a, unsigned long b)
385 {
386 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_HANC);
387 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_HANC);
388 }
389
390 /* Inline function to enable raw vbi in the given channel */
disable_raw_feature(u8 channel_id,u8 index)391 static inline void disable_raw_feature(u8 channel_id, u8 index)
392 {
393 u32 ctrl_reg;
394 if (0 == channel_id)
395 ctrl_reg = VPIF_CH0_CTRL;
396 else
397 ctrl_reg = VPIF_CH1_CTRL;
398
399 if (1 == index)
400 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
401 else
402 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
403 }
404
enable_raw_feature(u8 channel_id,u8 index)405 static inline void enable_raw_feature(u8 channel_id, u8 index)
406 {
407 u32 ctrl_reg;
408 if (0 == channel_id)
409 ctrl_reg = VPIF_CH0_CTRL;
410 else
411 ctrl_reg = VPIF_CH1_CTRL;
412
413 if (1 == index)
414 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
415 else
416 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
417 }
418
419 /* inline function to enable/disable channel2 */
enable_channel2(int enable)420 static inline void enable_channel2(int enable)
421 {
422 if (enable) {
423 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
424 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL);
425 } else {
426 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
427 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL);
428 }
429 }
430
431 /* inline function to enable/disable channel3 */
enable_channel3(int enable)432 static inline void enable_channel3(int enable)
433 {
434 if (enable) {
435 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
436 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL);
437 } else {
438 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
439 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL);
440 }
441 }
442
443 /* inline function to enable interrupt for channel2 */
channel2_intr_enable(int enable)444 static inline void channel2_intr_enable(int enable)
445 {
446 unsigned long flags;
447
448 spin_lock_irqsave(&vpif_lock, flags);
449
450 if (enable) {
451 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
452 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
453 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN);
454 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
455 VPIF_INTEN_SET);
456 } else {
457 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN);
458 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
459 VPIF_INTEN_SET);
460 }
461 spin_unlock_irqrestore(&vpif_lock, flags);
462 }
463
464 /* inline function to enable interrupt for channel3 */
channel3_intr_enable(int enable)465 static inline void channel3_intr_enable(int enable)
466 {
467 unsigned long flags;
468
469 spin_lock_irqsave(&vpif_lock, flags);
470
471 if (enable) {
472 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
473 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
474
475 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN);
476 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
477 VPIF_INTEN_SET);
478 } else {
479 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN);
480 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
481 VPIF_INTEN_SET);
482 }
483 spin_unlock_irqrestore(&vpif_lock, flags);
484 }
485
486 /* inline function to enable raw vbi data for channel2 */
channel2_raw_enable(int enable,u8 index)487 static inline void channel2_raw_enable(int enable, u8 index)
488 {
489 u32 mask;
490
491 if (1 == index)
492 mask = VPIF_CH_VANC_EN_BIT;
493 else
494 mask = VPIF_CH_HANC_EN_BIT;
495
496 if (enable)
497 vpif_set_bit(VPIF_CH2_CTRL, mask);
498 else
499 vpif_clr_bit(VPIF_CH2_CTRL, mask);
500 }
501
502 /* inline function to enable raw vbi data for channel3*/
channel3_raw_enable(int enable,u8 index)503 static inline void channel3_raw_enable(int enable, u8 index)
504 {
505 u32 mask;
506
507 if (1 == index)
508 mask = VPIF_CH_VANC_EN_BIT;
509 else
510 mask = VPIF_CH_HANC_EN_BIT;
511
512 if (enable)
513 vpif_set_bit(VPIF_CH3_CTRL, mask);
514 else
515 vpif_clr_bit(VPIF_CH3_CTRL, mask);
516 }
517
518 /* inline function to set buffer addresses in case of Y/C non mux mode */
ch2_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)519 static inline void ch2_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,
520 unsigned long btm_strt_luma,
521 unsigned long top_strt_chroma,
522 unsigned long btm_strt_chroma)
523 {
524 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
525 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
526 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
527 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
528 }
529
530 /* inline function to set buffer addresses in VPIF registers for video data */
ch2_set_videobuf_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)531 static inline void ch2_set_videobuf_addr(unsigned long top_strt_luma,
532 unsigned long btm_strt_luma,
533 unsigned long top_strt_chroma,
534 unsigned long btm_strt_chroma)
535 {
536 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
537 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
538 regw(top_strt_chroma, VPIF_CH2_TOP_STRT_ADD_CHROMA);
539 regw(btm_strt_chroma, VPIF_CH2_BTM_STRT_ADD_CHROMA);
540 }
541
ch3_set_videobuf_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)542 static inline void ch3_set_videobuf_addr(unsigned long top_strt_luma,
543 unsigned long btm_strt_luma,
544 unsigned long top_strt_chroma,
545 unsigned long btm_strt_chroma)
546 {
547 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_LUMA);
548 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_LUMA);
549 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
550 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
551 }
552
553 /* inline function to set buffer addresses in VPIF registers for vbi data */
ch2_set_vbi_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)554 static inline void ch2_set_vbi_addr(unsigned long top_strt_luma,
555 unsigned long btm_strt_luma,
556 unsigned long top_strt_chroma,
557 unsigned long btm_strt_chroma)
558 {
559 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_VANC);
560 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_VANC);
561 }
562
ch3_set_vbi_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)563 static inline void ch3_set_vbi_addr(unsigned long top_strt_luma,
564 unsigned long btm_strt_luma,
565 unsigned long top_strt_chroma,
566 unsigned long btm_strt_chroma)
567 {
568 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_VANC);
569 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_VANC);
570 }
571
572 #define VPIF_MAX_NAME (30)
573
574 /* This structure will store size parameters as per the mode selected by user */
575 struct vpif_channel_config_params {
576 char name[VPIF_MAX_NAME]; /* Name of the mode */
577 u16 width; /* Indicates width of the image */
578 u16 height; /* Indicates height of the image */
579 u8 frm_fmt; /* Interlaced (0) or progressive (1) */
580 u8 ycmux_mode; /* This mode requires one (0) or two (1)
581 channels */
582 u16 eav2sav; /* length of eav 2 sav */
583 u16 sav2eav; /* length of sav 2 eav */
584 u16 l1, l3, l5, l7, l9, l11; /* Other parameter configurations */
585 u16 vsize; /* Vertical size of the image */
586 u8 capture_format; /* Indicates whether capture format
587 * is in BT or in CCD/CMOS */
588 u8 vbi_supported; /* Indicates whether this mode
589 * supports capturing vbi or not */
590 u8 hd_sd; /* HDTV (1) or SDTV (0) format */
591 v4l2_std_id stdid; /* SDTV format */
592 u32 dv_preset; /* HDTV format */
593 };
594
595 extern const unsigned int vpif_ch_params_count;
596 extern const struct vpif_channel_config_params ch_params[];
597
598 struct vpif_video_params;
599 struct vpif_params;
600 struct vpif_vbi_params;
601
602 int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id);
603 void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
604 u8 channel_id);
605 int vpif_channel_getfid(u8 channel_id);
606
607 enum data_size {
608 _8BITS = 0,
609 _10BITS,
610 _12BITS,
611 };
612
613 /* Structure for vpif parameters for raw vbi data */
614 struct vpif_vbi_params {
615 __u32 hstart0; /* Horizontal start of raw vbi data for first field */
616 __u32 vstart0; /* Vertical start of raw vbi data for first field */
617 __u32 hsize0; /* Horizontal size of raw vbi data for first field */
618 __u32 vsize0; /* Vertical size of raw vbi data for first field */
619 __u32 hstart1; /* Horizontal start of raw vbi data for second field */
620 __u32 vstart1; /* Vertical start of raw vbi data for second field */
621 __u32 hsize1; /* Horizontal size of raw vbi data for second field */
622 __u32 vsize1; /* Vertical size of raw vbi data for second field */
623 };
624
625 /* structure for vpif parameters */
626 struct vpif_video_params {
627 __u8 storage_mode; /* Indicates field or frame mode */
628 unsigned long hpitch;
629 v4l2_std_id stdid;
630 };
631
632 struct vpif_params {
633 struct vpif_interface iface;
634 struct vpif_video_params video_params;
635 struct vpif_channel_config_params std_info;
636 union param {
637 struct vpif_vbi_params vbi_params;
638 enum data_size data_sz;
639 } params;
640 };
641
642 #endif /* End of #ifndef VPIF_H */
643
644