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1 /*
2  *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
3  *  Copyright 2007-2010 Freescale Semiconductor, Inc.
4  *
5  *  This program is free software; you can redistribute it and/or
6  *  modify it under the terms of the GNU General Public License
7  *  as published by the Free Software Foundation; either version
8  *  2 of the License, or (at your option) any later version.
9  *
10  *  Modified by Cort Dougan (cort@cs.nmt.edu)
11  *  and Paul Mackerras (paulus@samba.org)
12  */
13 
14 /*
15  * This file handles the architecture-dependent parts of hardware exceptions
16  */
17 
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
38 
39 #include <asm/emulated_ops.h>
40 #include <asm/pgtable.h>
41 #include <asm/uaccess.h>
42 #include <asm/io.h>
43 #include <asm/machdep.h>
44 #include <asm/rtas.h>
45 #include <asm/pmc.h>
46 #ifdef CONFIG_PPC32
47 #include <asm/reg.h>
48 #endif
49 #ifdef CONFIG_PMAC_BACKLIGHT
50 #include <asm/backlight.h>
51 #endif
52 #ifdef CONFIG_PPC64
53 #include <asm/firmware.h>
54 #include <asm/processor.h>
55 #endif
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
58 #include <asm/rio.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
61 #include <asm/debug.h>
62 
63 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
64 int (*__debugger)(struct pt_regs *regs) __read_mostly;
65 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
66 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
67 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
68 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
69 int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly;
70 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
71 
72 EXPORT_SYMBOL(__debugger);
73 EXPORT_SYMBOL(__debugger_ipi);
74 EXPORT_SYMBOL(__debugger_bpt);
75 EXPORT_SYMBOL(__debugger_sstep);
76 EXPORT_SYMBOL(__debugger_iabr_match);
77 EXPORT_SYMBOL(__debugger_dabr_match);
78 EXPORT_SYMBOL(__debugger_fault_handler);
79 #endif
80 
81 /*
82  * Trap & Exception support
83  */
84 
85 #ifdef CONFIG_PMAC_BACKLIGHT
pmac_backlight_unblank(void)86 static void pmac_backlight_unblank(void)
87 {
88 	mutex_lock(&pmac_backlight_mutex);
89 	if (pmac_backlight) {
90 		struct backlight_properties *props;
91 
92 		props = &pmac_backlight->props;
93 		props->brightness = props->max_brightness;
94 		props->power = FB_BLANK_UNBLANK;
95 		backlight_update_status(pmac_backlight);
96 	}
97 	mutex_unlock(&pmac_backlight_mutex);
98 }
99 #else
pmac_backlight_unblank(void)100 static inline void pmac_backlight_unblank(void) { }
101 #endif
102 
103 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
104 static int die_owner = -1;
105 static unsigned int die_nest_count;
106 static int die_counter;
107 
oops_begin(struct pt_regs * regs)108 static unsigned __kprobes long oops_begin(struct pt_regs *regs)
109 {
110 	int cpu;
111 	unsigned long flags;
112 
113 	if (debugger(regs))
114 		return 1;
115 
116 	oops_enter();
117 
118 	/* racy, but better than risking deadlock. */
119 	raw_local_irq_save(flags);
120 	cpu = smp_processor_id();
121 	if (!arch_spin_trylock(&die_lock)) {
122 		if (cpu == die_owner)
123 			/* nested oops. should stop eventually */;
124 		else
125 			arch_spin_lock(&die_lock);
126 	}
127 	die_nest_count++;
128 	die_owner = cpu;
129 	console_verbose();
130 	bust_spinlocks(1);
131 	if (machine_is(powermac))
132 		pmac_backlight_unblank();
133 	return flags;
134 }
135 
oops_end(unsigned long flags,struct pt_regs * regs,int signr)136 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
137 			       int signr)
138 {
139 	bust_spinlocks(0);
140 	die_owner = -1;
141 	add_taint(TAINT_DIE);
142 	die_nest_count--;
143 	oops_exit();
144 	printk("\n");
145 	if (!die_nest_count)
146 		/* Nest count reaches zero, release the lock. */
147 		arch_spin_unlock(&die_lock);
148 	raw_local_irq_restore(flags);
149 
150 	crash_fadump(regs, "die oops");
151 
152 	/*
153 	 * A system reset (0x100) is a request to dump, so we always send
154 	 * it through the crashdump code.
155 	 */
156 	if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
157 		crash_kexec(regs);
158 
159 		/*
160 		 * We aren't the primary crash CPU. We need to send it
161 		 * to a holding pattern to avoid it ending up in the panic
162 		 * code.
163 		 */
164 		crash_kexec_secondary(regs);
165 	}
166 
167 	if (!signr)
168 		return;
169 
170 	/*
171 	 * While our oops output is serialised by a spinlock, output
172 	 * from panic() called below can race and corrupt it. If we
173 	 * know we are going to panic, delay for 1 second so we have a
174 	 * chance to get clean backtraces from all CPUs that are oopsing.
175 	 */
176 	if (in_interrupt() || panic_on_oops || !current->pid ||
177 	    is_global_init(current)) {
178 		mdelay(MSEC_PER_SEC);
179 	}
180 
181 	if (in_interrupt())
182 		panic("Fatal exception in interrupt");
183 	if (panic_on_oops)
184 		panic("Fatal exception");
185 	do_exit(signr);
186 }
187 
__die(const char * str,struct pt_regs * regs,long err)188 static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
189 {
190 	printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
191 #ifdef CONFIG_PREEMPT
192 	printk("PREEMPT ");
193 #endif
194 #ifdef CONFIG_SMP
195 	printk("SMP NR_CPUS=%d ", NR_CPUS);
196 #endif
197 #ifdef CONFIG_DEBUG_PAGEALLOC
198 	printk("DEBUG_PAGEALLOC ");
199 #endif
200 #ifdef CONFIG_NUMA
201 	printk("NUMA ");
202 #endif
203 	printk("%s\n", ppc_md.name ? ppc_md.name : "");
204 
205 	if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
206 		return 1;
207 
208 	print_modules();
209 	show_regs(regs);
210 
211 	return 0;
212 }
213 
die(const char * str,struct pt_regs * regs,long err)214 void die(const char *str, struct pt_regs *regs, long err)
215 {
216 	unsigned long flags = oops_begin(regs);
217 
218 	if (__die(str, regs, err))
219 		err = 0;
220 	oops_end(flags, regs, err);
221 }
222 
user_single_step_siginfo(struct task_struct * tsk,struct pt_regs * regs,siginfo_t * info)223 void user_single_step_siginfo(struct task_struct *tsk,
224 				struct pt_regs *regs, siginfo_t *info)
225 {
226 	memset(info, 0, sizeof(*info));
227 	info->si_signo = SIGTRAP;
228 	info->si_code = TRAP_TRACE;
229 	info->si_addr = (void __user *)regs->nip;
230 }
231 
_exception(int signr,struct pt_regs * regs,int code,unsigned long addr)232 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
233 {
234 	siginfo_t info;
235 	const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
236 			"at %08lx nip %08lx lr %08lx code %x\n";
237 	const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
238 			"at %016lx nip %016lx lr %016lx code %x\n";
239 
240 	if (!user_mode(regs)) {
241 		die("Exception in kernel mode", regs, signr);
242 		return;
243 	}
244 
245 	if (show_unhandled_signals && unhandled_signal(current, signr)) {
246 		printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
247 				   current->comm, current->pid, signr,
248 				   addr, regs->nip, regs->link, code);
249 	}
250 
251 	if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
252 		local_irq_enable();
253 
254 	memset(&info, 0, sizeof(info));
255 	info.si_signo = signr;
256 	info.si_code = code;
257 	info.si_addr = (void __user *) addr;
258 	force_sig_info(signr, &info, current);
259 }
260 
261 #ifdef CONFIG_PPC64
system_reset_exception(struct pt_regs * regs)262 void system_reset_exception(struct pt_regs *regs)
263 {
264 	/* See if any machine dependent calls */
265 	if (ppc_md.system_reset_exception) {
266 		if (ppc_md.system_reset_exception(regs))
267 			return;
268 	}
269 
270 	die("System Reset", regs, SIGABRT);
271 
272 	/* Must die if the interrupt is not recoverable */
273 	if (!(regs->msr & MSR_RI))
274 		panic("Unrecoverable System Reset");
275 
276 	/* What should we do here? We could issue a shutdown or hard reset. */
277 }
278 #endif
279 
280 /*
281  * I/O accesses can cause machine checks on powermacs.
282  * Check if the NIP corresponds to the address of a sync
283  * instruction for which there is an entry in the exception
284  * table.
285  * Note that the 601 only takes a machine check on TEA
286  * (transfer error ack) signal assertion, and does not
287  * set any of the top 16 bits of SRR1.
288  *  -- paulus.
289  */
check_io_access(struct pt_regs * regs)290 static inline int check_io_access(struct pt_regs *regs)
291 {
292 #ifdef CONFIG_PPC32
293 	unsigned long msr = regs->msr;
294 	const struct exception_table_entry *entry;
295 	unsigned int *nip = (unsigned int *)regs->nip;
296 
297 	if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
298 	    && (entry = search_exception_tables(regs->nip)) != NULL) {
299 		/*
300 		 * Check that it's a sync instruction, or somewhere
301 		 * in the twi; isync; nop sequence that inb/inw/inl uses.
302 		 * As the address is in the exception table
303 		 * we should be able to read the instr there.
304 		 * For the debug message, we look at the preceding
305 		 * load or store.
306 		 */
307 		if (*nip == 0x60000000)		/* nop */
308 			nip -= 2;
309 		else if (*nip == 0x4c00012c)	/* isync */
310 			--nip;
311 		if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
312 			/* sync or twi */
313 			unsigned int rb;
314 
315 			--nip;
316 			rb = (*nip >> 11) & 0x1f;
317 			printk(KERN_DEBUG "%s bad port %lx at %p\n",
318 			       (*nip & 0x100)? "OUT to": "IN from",
319 			       regs->gpr[rb] - _IO_BASE, nip);
320 			regs->msr |= MSR_RI;
321 			regs->nip = entry->fixup;
322 			return 1;
323 		}
324 	}
325 #endif /* CONFIG_PPC32 */
326 	return 0;
327 }
328 
329 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
330 /* On 4xx, the reason for the machine check or program exception
331    is in the ESR. */
332 #define get_reason(regs)	((regs)->dsisr)
333 #ifndef CONFIG_FSL_BOOKE
334 #define get_mc_reason(regs)	((regs)->dsisr)
335 #else
336 #define get_mc_reason(regs)	(mfspr(SPRN_MCSR))
337 #endif
338 #define REASON_FP		ESR_FP
339 #define REASON_ILLEGAL		(ESR_PIL | ESR_PUO)
340 #define REASON_PRIVILEGED	ESR_PPR
341 #define REASON_TRAP		ESR_PTR
342 
343 /* single-step stuff */
344 #define single_stepping(regs)	(current->thread.dbcr0 & DBCR0_IC)
345 #define clear_single_step(regs)	(current->thread.dbcr0 &= ~DBCR0_IC)
346 
347 #else
348 /* On non-4xx, the reason for the machine check or program
349    exception is in the MSR. */
350 #define get_reason(regs)	((regs)->msr)
351 #define get_mc_reason(regs)	((regs)->msr)
352 #define REASON_FP		0x100000
353 #define REASON_ILLEGAL		0x80000
354 #define REASON_PRIVILEGED	0x40000
355 #define REASON_TRAP		0x20000
356 
357 #define single_stepping(regs)	((regs)->msr & MSR_SE)
358 #define clear_single_step(regs)	((regs)->msr &= ~MSR_SE)
359 #endif
360 
361 #if defined(CONFIG_4xx)
machine_check_4xx(struct pt_regs * regs)362 int machine_check_4xx(struct pt_regs *regs)
363 {
364 	unsigned long reason = get_mc_reason(regs);
365 
366 	if (reason & ESR_IMCP) {
367 		printk("Instruction");
368 		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
369 	} else
370 		printk("Data");
371 	printk(" machine check in kernel mode.\n");
372 
373 	return 0;
374 }
375 
machine_check_440A(struct pt_regs * regs)376 int machine_check_440A(struct pt_regs *regs)
377 {
378 	unsigned long reason = get_mc_reason(regs);
379 
380 	printk("Machine check in kernel mode.\n");
381 	if (reason & ESR_IMCP){
382 		printk("Instruction Synchronous Machine Check exception\n");
383 		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
384 	}
385 	else {
386 		u32 mcsr = mfspr(SPRN_MCSR);
387 		if (mcsr & MCSR_IB)
388 			printk("Instruction Read PLB Error\n");
389 		if (mcsr & MCSR_DRB)
390 			printk("Data Read PLB Error\n");
391 		if (mcsr & MCSR_DWB)
392 			printk("Data Write PLB Error\n");
393 		if (mcsr & MCSR_TLBP)
394 			printk("TLB Parity Error\n");
395 		if (mcsr & MCSR_ICP){
396 			flush_instruction_cache();
397 			printk("I-Cache Parity Error\n");
398 		}
399 		if (mcsr & MCSR_DCSP)
400 			printk("D-Cache Search Parity Error\n");
401 		if (mcsr & MCSR_DCFP)
402 			printk("D-Cache Flush Parity Error\n");
403 		if (mcsr & MCSR_IMPE)
404 			printk("Machine Check exception is imprecise\n");
405 
406 		/* Clear MCSR */
407 		mtspr(SPRN_MCSR, mcsr);
408 	}
409 	return 0;
410 }
411 
machine_check_47x(struct pt_regs * regs)412 int machine_check_47x(struct pt_regs *regs)
413 {
414 	unsigned long reason = get_mc_reason(regs);
415 	u32 mcsr;
416 
417 	printk(KERN_ERR "Machine check in kernel mode.\n");
418 	if (reason & ESR_IMCP) {
419 		printk(KERN_ERR
420 		       "Instruction Synchronous Machine Check exception\n");
421 		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
422 		return 0;
423 	}
424 	mcsr = mfspr(SPRN_MCSR);
425 	if (mcsr & MCSR_IB)
426 		printk(KERN_ERR "Instruction Read PLB Error\n");
427 	if (mcsr & MCSR_DRB)
428 		printk(KERN_ERR "Data Read PLB Error\n");
429 	if (mcsr & MCSR_DWB)
430 		printk(KERN_ERR "Data Write PLB Error\n");
431 	if (mcsr & MCSR_TLBP)
432 		printk(KERN_ERR "TLB Parity Error\n");
433 	if (mcsr & MCSR_ICP) {
434 		flush_instruction_cache();
435 		printk(KERN_ERR "I-Cache Parity Error\n");
436 	}
437 	if (mcsr & MCSR_DCSP)
438 		printk(KERN_ERR "D-Cache Search Parity Error\n");
439 	if (mcsr & PPC47x_MCSR_GPR)
440 		printk(KERN_ERR "GPR Parity Error\n");
441 	if (mcsr & PPC47x_MCSR_FPR)
442 		printk(KERN_ERR "FPR Parity Error\n");
443 	if (mcsr & PPC47x_MCSR_IPR)
444 		printk(KERN_ERR "Machine Check exception is imprecise\n");
445 
446 	/* Clear MCSR */
447 	mtspr(SPRN_MCSR, mcsr);
448 
449 	return 0;
450 }
451 #elif defined(CONFIG_E500)
machine_check_e500mc(struct pt_regs * regs)452 int machine_check_e500mc(struct pt_regs *regs)
453 {
454 	unsigned long mcsr = mfspr(SPRN_MCSR);
455 	unsigned long reason = mcsr;
456 	int recoverable = 1;
457 
458 	if (reason & MCSR_LD) {
459 		recoverable = fsl_rio_mcheck_exception(regs);
460 		if (recoverable == 1)
461 			goto silent_out;
462 	}
463 
464 	printk("Machine check in kernel mode.\n");
465 	printk("Caused by (from MCSR=%lx): ", reason);
466 
467 	if (reason & MCSR_MCP)
468 		printk("Machine Check Signal\n");
469 
470 	if (reason & MCSR_ICPERR) {
471 		printk("Instruction Cache Parity Error\n");
472 
473 		/*
474 		 * This is recoverable by invalidating the i-cache.
475 		 */
476 		mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
477 		while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
478 			;
479 
480 		/*
481 		 * This will generally be accompanied by an instruction
482 		 * fetch error report -- only treat MCSR_IF as fatal
483 		 * if it wasn't due to an L1 parity error.
484 		 */
485 		reason &= ~MCSR_IF;
486 	}
487 
488 	if (reason & MCSR_DCPERR_MC) {
489 		printk("Data Cache Parity Error\n");
490 
491 		/*
492 		 * In write shadow mode we auto-recover from the error, but it
493 		 * may still get logged and cause a machine check.  We should
494 		 * only treat the non-write shadow case as non-recoverable.
495 		 */
496 		if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
497 			recoverable = 0;
498 	}
499 
500 	if (reason & MCSR_L2MMU_MHIT) {
501 		printk("Hit on multiple TLB entries\n");
502 		recoverable = 0;
503 	}
504 
505 	if (reason & MCSR_NMI)
506 		printk("Non-maskable interrupt\n");
507 
508 	if (reason & MCSR_IF) {
509 		printk("Instruction Fetch Error Report\n");
510 		recoverable = 0;
511 	}
512 
513 	if (reason & MCSR_LD) {
514 		printk("Load Error Report\n");
515 		recoverable = 0;
516 	}
517 
518 	if (reason & MCSR_ST) {
519 		printk("Store Error Report\n");
520 		recoverable = 0;
521 	}
522 
523 	if (reason & MCSR_LDG) {
524 		printk("Guarded Load Error Report\n");
525 		recoverable = 0;
526 	}
527 
528 	if (reason & MCSR_TLBSYNC)
529 		printk("Simultaneous tlbsync operations\n");
530 
531 	if (reason & MCSR_BSL2_ERR) {
532 		printk("Level 2 Cache Error\n");
533 		recoverable = 0;
534 	}
535 
536 	if (reason & MCSR_MAV) {
537 		u64 addr;
538 
539 		addr = mfspr(SPRN_MCAR);
540 		addr |= (u64)mfspr(SPRN_MCARU) << 32;
541 
542 		printk("Machine Check %s Address: %#llx\n",
543 		       reason & MCSR_MEA ? "Effective" : "Physical", addr);
544 	}
545 
546 silent_out:
547 	mtspr(SPRN_MCSR, mcsr);
548 	return mfspr(SPRN_MCSR) == 0 && recoverable;
549 }
550 
machine_check_e500(struct pt_regs * regs)551 int machine_check_e500(struct pt_regs *regs)
552 {
553 	unsigned long reason = get_mc_reason(regs);
554 
555 	if (reason & MCSR_BUS_RBERR) {
556 		if (fsl_rio_mcheck_exception(regs))
557 			return 1;
558 	}
559 
560 	printk("Machine check in kernel mode.\n");
561 	printk("Caused by (from MCSR=%lx): ", reason);
562 
563 	if (reason & MCSR_MCP)
564 		printk("Machine Check Signal\n");
565 	if (reason & MCSR_ICPERR)
566 		printk("Instruction Cache Parity Error\n");
567 	if (reason & MCSR_DCP_PERR)
568 		printk("Data Cache Push Parity Error\n");
569 	if (reason & MCSR_DCPERR)
570 		printk("Data Cache Parity Error\n");
571 	if (reason & MCSR_BUS_IAERR)
572 		printk("Bus - Instruction Address Error\n");
573 	if (reason & MCSR_BUS_RAERR)
574 		printk("Bus - Read Address Error\n");
575 	if (reason & MCSR_BUS_WAERR)
576 		printk("Bus - Write Address Error\n");
577 	if (reason & MCSR_BUS_IBERR)
578 		printk("Bus - Instruction Data Error\n");
579 	if (reason & MCSR_BUS_RBERR)
580 		printk("Bus - Read Data Bus Error\n");
581 	if (reason & MCSR_BUS_WBERR)
582 		printk("Bus - Read Data Bus Error\n");
583 	if (reason & MCSR_BUS_IPERR)
584 		printk("Bus - Instruction Parity Error\n");
585 	if (reason & MCSR_BUS_RPERR)
586 		printk("Bus - Read Parity Error\n");
587 
588 	return 0;
589 }
590 
machine_check_generic(struct pt_regs * regs)591 int machine_check_generic(struct pt_regs *regs)
592 {
593 	return 0;
594 }
595 #elif defined(CONFIG_E200)
machine_check_e200(struct pt_regs * regs)596 int machine_check_e200(struct pt_regs *regs)
597 {
598 	unsigned long reason = get_mc_reason(regs);
599 
600 	printk("Machine check in kernel mode.\n");
601 	printk("Caused by (from MCSR=%lx): ", reason);
602 
603 	if (reason & MCSR_MCP)
604 		printk("Machine Check Signal\n");
605 	if (reason & MCSR_CP_PERR)
606 		printk("Cache Push Parity Error\n");
607 	if (reason & MCSR_CPERR)
608 		printk("Cache Parity Error\n");
609 	if (reason & MCSR_EXCP_ERR)
610 		printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
611 	if (reason & MCSR_BUS_IRERR)
612 		printk("Bus - Read Bus Error on instruction fetch\n");
613 	if (reason & MCSR_BUS_DRERR)
614 		printk("Bus - Read Bus Error on data load\n");
615 	if (reason & MCSR_BUS_WRERR)
616 		printk("Bus - Write Bus Error on buffered store or cache line push\n");
617 
618 	return 0;
619 }
620 #else
machine_check_generic(struct pt_regs * regs)621 int machine_check_generic(struct pt_regs *regs)
622 {
623 	unsigned long reason = get_mc_reason(regs);
624 
625 	printk("Machine check in kernel mode.\n");
626 	printk("Caused by (from SRR1=%lx): ", reason);
627 	switch (reason & 0x601F0000) {
628 	case 0x80000:
629 		printk("Machine check signal\n");
630 		break;
631 	case 0:		/* for 601 */
632 	case 0x40000:
633 	case 0x140000:	/* 7450 MSS error and TEA */
634 		printk("Transfer error ack signal\n");
635 		break;
636 	case 0x20000:
637 		printk("Data parity error signal\n");
638 		break;
639 	case 0x10000:
640 		printk("Address parity error signal\n");
641 		break;
642 	case 0x20000000:
643 		printk("L1 Data Cache error\n");
644 		break;
645 	case 0x40000000:
646 		printk("L1 Instruction Cache error\n");
647 		break;
648 	case 0x00100000:
649 		printk("L2 data cache parity error\n");
650 		break;
651 	default:
652 		printk("Unknown values in msr\n");
653 	}
654 	return 0;
655 }
656 #endif /* everything else */
657 
machine_check_exception(struct pt_regs * regs)658 void machine_check_exception(struct pt_regs *regs)
659 {
660 	int recover = 0;
661 
662 	__get_cpu_var(irq_stat).mce_exceptions++;
663 
664 	/* See if any machine dependent calls. In theory, we would want
665 	 * to call the CPU first, and call the ppc_md. one if the CPU
666 	 * one returns a positive number. However there is existing code
667 	 * that assumes the board gets a first chance, so let's keep it
668 	 * that way for now and fix things later. --BenH.
669 	 */
670 	if (ppc_md.machine_check_exception)
671 		recover = ppc_md.machine_check_exception(regs);
672 	else if (cur_cpu_spec->machine_check)
673 		recover = cur_cpu_spec->machine_check(regs);
674 
675 	if (recover > 0)
676 		return;
677 
678 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
679 	/* the qspan pci read routines can cause machine checks -- Cort
680 	 *
681 	 * yuck !!! that totally needs to go away ! There are better ways
682 	 * to deal with that than having a wart in the mcheck handler.
683 	 * -- BenH
684 	 */
685 	bad_page_fault(regs, regs->dar, SIGBUS);
686 	return;
687 #endif
688 
689 	if (debugger_fault_handler(regs))
690 		return;
691 
692 	if (check_io_access(regs))
693 		return;
694 
695 	die("Machine check", regs, SIGBUS);
696 
697 	/* Must die if the interrupt is not recoverable */
698 	if (!(regs->msr & MSR_RI))
699 		panic("Unrecoverable Machine check");
700 }
701 
SMIException(struct pt_regs * regs)702 void SMIException(struct pt_regs *regs)
703 {
704 	die("System Management Interrupt", regs, SIGABRT);
705 }
706 
unknown_exception(struct pt_regs * regs)707 void unknown_exception(struct pt_regs *regs)
708 {
709 	printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
710 	       regs->nip, regs->msr, regs->trap);
711 
712 	_exception(SIGTRAP, regs, 0, 0);
713 }
714 
instruction_breakpoint_exception(struct pt_regs * regs)715 void instruction_breakpoint_exception(struct pt_regs *regs)
716 {
717 	if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
718 					5, SIGTRAP) == NOTIFY_STOP)
719 		return;
720 	if (debugger_iabr_match(regs))
721 		return;
722 	_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
723 }
724 
RunModeException(struct pt_regs * regs)725 void RunModeException(struct pt_regs *regs)
726 {
727 	_exception(SIGTRAP, regs, 0, 0);
728 }
729 
single_step_exception(struct pt_regs * regs)730 void __kprobes single_step_exception(struct pt_regs *regs)
731 {
732 	clear_single_step(regs);
733 
734 	if (notify_die(DIE_SSTEP, "single_step", regs, 5,
735 					5, SIGTRAP) == NOTIFY_STOP)
736 		return;
737 	if (debugger_sstep(regs))
738 		return;
739 
740 	_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
741 }
742 
743 /*
744  * After we have successfully emulated an instruction, we have to
745  * check if the instruction was being single-stepped, and if so,
746  * pretend we got a single-step exception.  This was pointed out
747  * by Kumar Gala.  -- paulus
748  */
emulate_single_step(struct pt_regs * regs)749 static void emulate_single_step(struct pt_regs *regs)
750 {
751 	if (single_stepping(regs))
752 		single_step_exception(regs);
753 }
754 
__parse_fpscr(unsigned long fpscr)755 static inline int __parse_fpscr(unsigned long fpscr)
756 {
757 	int ret = 0;
758 
759 	/* Invalid operation */
760 	if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
761 		ret = FPE_FLTINV;
762 
763 	/* Overflow */
764 	else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
765 		ret = FPE_FLTOVF;
766 
767 	/* Underflow */
768 	else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
769 		ret = FPE_FLTUND;
770 
771 	/* Divide by zero */
772 	else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
773 		ret = FPE_FLTDIV;
774 
775 	/* Inexact result */
776 	else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
777 		ret = FPE_FLTRES;
778 
779 	return ret;
780 }
781 
parse_fpe(struct pt_regs * regs)782 static void parse_fpe(struct pt_regs *regs)
783 {
784 	int code = 0;
785 
786 	flush_fp_to_thread(current);
787 
788 	code = __parse_fpscr(current->thread.fpscr.val);
789 
790 	_exception(SIGFPE, regs, code, regs->nip);
791 }
792 
793 /*
794  * Illegal instruction emulation support.  Originally written to
795  * provide the PVR to user applications using the mfspr rd, PVR.
796  * Return non-zero if we can't emulate, or -EFAULT if the associated
797  * memory access caused an access fault.  Return zero on success.
798  *
799  * There are a couple of ways to do this, either "decode" the instruction
800  * or directly match lots of bits.  In this case, matching lots of
801  * bits is faster and easier.
802  *
803  */
emulate_string_inst(struct pt_regs * regs,u32 instword)804 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
805 {
806 	u8 rT = (instword >> 21) & 0x1f;
807 	u8 rA = (instword >> 16) & 0x1f;
808 	u8 NB_RB = (instword >> 11) & 0x1f;
809 	u32 num_bytes;
810 	unsigned long EA;
811 	int pos = 0;
812 
813 	/* Early out if we are an invalid form of lswx */
814 	if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
815 		if ((rT == rA) || (rT == NB_RB))
816 			return -EINVAL;
817 
818 	EA = (rA == 0) ? 0 : regs->gpr[rA];
819 
820 	switch (instword & PPC_INST_STRING_MASK) {
821 		case PPC_INST_LSWX:
822 		case PPC_INST_STSWX:
823 			EA += NB_RB;
824 			num_bytes = regs->xer & 0x7f;
825 			break;
826 		case PPC_INST_LSWI:
827 		case PPC_INST_STSWI:
828 			num_bytes = (NB_RB == 0) ? 32 : NB_RB;
829 			break;
830 		default:
831 			return -EINVAL;
832 	}
833 
834 	while (num_bytes != 0)
835 	{
836 		u8 val;
837 		u32 shift = 8 * (3 - (pos & 0x3));
838 
839 		switch ((instword & PPC_INST_STRING_MASK)) {
840 			case PPC_INST_LSWX:
841 			case PPC_INST_LSWI:
842 				if (get_user(val, (u8 __user *)EA))
843 					return -EFAULT;
844 				/* first time updating this reg,
845 				 * zero it out */
846 				if (pos == 0)
847 					regs->gpr[rT] = 0;
848 				regs->gpr[rT] |= val << shift;
849 				break;
850 			case PPC_INST_STSWI:
851 			case PPC_INST_STSWX:
852 				val = regs->gpr[rT] >> shift;
853 				if (put_user(val, (u8 __user *)EA))
854 					return -EFAULT;
855 				break;
856 		}
857 		/* move EA to next address */
858 		EA += 1;
859 		num_bytes--;
860 
861 		/* manage our position within the register */
862 		if (++pos == 4) {
863 			pos = 0;
864 			if (++rT == 32)
865 				rT = 0;
866 		}
867 	}
868 
869 	return 0;
870 }
871 
emulate_popcntb_inst(struct pt_regs * regs,u32 instword)872 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
873 {
874 	u32 ra,rs;
875 	unsigned long tmp;
876 
877 	ra = (instword >> 16) & 0x1f;
878 	rs = (instword >> 21) & 0x1f;
879 
880 	tmp = regs->gpr[rs];
881 	tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
882 	tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
883 	tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
884 	regs->gpr[ra] = tmp;
885 
886 	return 0;
887 }
888 
emulate_isel(struct pt_regs * regs,u32 instword)889 static int emulate_isel(struct pt_regs *regs, u32 instword)
890 {
891 	u8 rT = (instword >> 21) & 0x1f;
892 	u8 rA = (instword >> 16) & 0x1f;
893 	u8 rB = (instword >> 11) & 0x1f;
894 	u8 BC = (instword >> 6) & 0x1f;
895 	u8 bit;
896 	unsigned long tmp;
897 
898 	tmp = (rA == 0) ? 0 : regs->gpr[rA];
899 	bit = (regs->ccr >> (31 - BC)) & 0x1;
900 
901 	regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
902 
903 	return 0;
904 }
905 
emulate_instruction(struct pt_regs * regs)906 static int emulate_instruction(struct pt_regs *regs)
907 {
908 	u32 instword;
909 	u32 rd;
910 
911 	if (!user_mode(regs) || (regs->msr & MSR_LE))
912 		return -EINVAL;
913 	CHECK_FULL_REGS(regs);
914 
915 	if (get_user(instword, (u32 __user *)(regs->nip)))
916 		return -EFAULT;
917 
918 	/* Emulate the mfspr rD, PVR. */
919 	if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
920 		PPC_WARN_EMULATED(mfpvr, regs);
921 		rd = (instword >> 21) & 0x1f;
922 		regs->gpr[rd] = mfspr(SPRN_PVR);
923 		return 0;
924 	}
925 
926 	/* Emulating the dcba insn is just a no-op.  */
927 	if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
928 		PPC_WARN_EMULATED(dcba, regs);
929 		return 0;
930 	}
931 
932 	/* Emulate the mcrxr insn.  */
933 	if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
934 		int shift = (instword >> 21) & 0x1c;
935 		unsigned long msk = 0xf0000000UL >> shift;
936 
937 		PPC_WARN_EMULATED(mcrxr, regs);
938 		regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
939 		regs->xer &= ~0xf0000000UL;
940 		return 0;
941 	}
942 
943 	/* Emulate load/store string insn. */
944 	if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
945 		PPC_WARN_EMULATED(string, regs);
946 		return emulate_string_inst(regs, instword);
947 	}
948 
949 	/* Emulate the popcntb (Population Count Bytes) instruction. */
950 	if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
951 		PPC_WARN_EMULATED(popcntb, regs);
952 		return emulate_popcntb_inst(regs, instword);
953 	}
954 
955 	/* Emulate isel (Integer Select) instruction */
956 	if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
957 		PPC_WARN_EMULATED(isel, regs);
958 		return emulate_isel(regs, instword);
959 	}
960 
961 #ifdef CONFIG_PPC64
962 	/* Emulate the mfspr rD, DSCR. */
963 	if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
964 		PPC_INST_MFSPR_DSCR_USER) ||
965 	     ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
966 		PPC_INST_MFSPR_DSCR)) &&
967 			cpu_has_feature(CPU_FTR_DSCR)) {
968 		PPC_WARN_EMULATED(mfdscr, regs);
969 		rd = (instword >> 21) & 0x1f;
970 		regs->gpr[rd] = mfspr(SPRN_DSCR);
971 		return 0;
972 	}
973 	/* Emulate the mtspr DSCR, rD. */
974 	if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
975 		PPC_INST_MTSPR_DSCR_USER) ||
976 	     ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
977 		PPC_INST_MTSPR_DSCR)) &&
978 			cpu_has_feature(CPU_FTR_DSCR)) {
979 		PPC_WARN_EMULATED(mtdscr, regs);
980 		rd = (instword >> 21) & 0x1f;
981 		current->thread.dscr = regs->gpr[rd];
982 		current->thread.dscr_inherit = 1;
983 		mtspr(SPRN_DSCR, current->thread.dscr);
984 		return 0;
985 	}
986 #endif
987 
988 	return -EINVAL;
989 }
990 
is_valid_bugaddr(unsigned long addr)991 int is_valid_bugaddr(unsigned long addr)
992 {
993 	return is_kernel_addr(addr);
994 }
995 
program_check_exception(struct pt_regs * regs)996 void __kprobes program_check_exception(struct pt_regs *regs)
997 {
998 	unsigned int reason = get_reason(regs);
999 	extern int do_mathemu(struct pt_regs *regs);
1000 
1001 	/* We can now get here via a FP Unavailable exception if the core
1002 	 * has no FPU, in that case the reason flags will be 0 */
1003 
1004 	if (reason & REASON_FP) {
1005 		/* IEEE FP exception */
1006 		parse_fpe(regs);
1007 		return;
1008 	}
1009 	if (reason & REASON_TRAP) {
1010 		/* Debugger is first in line to stop recursive faults in
1011 		 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1012 		if (debugger_bpt(regs))
1013 			return;
1014 
1015 		/* trap exception */
1016 		if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1017 				== NOTIFY_STOP)
1018 			return;
1019 
1020 		if (!(regs->msr & MSR_PR) &&  /* not user-mode */
1021 		    report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1022 			regs->nip += 4;
1023 			return;
1024 		}
1025 		_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1026 		return;
1027 	}
1028 
1029 	/* We restore the interrupt state now */
1030 	if (!arch_irq_disabled_regs(regs))
1031 		local_irq_enable();
1032 
1033 #ifdef CONFIG_MATH_EMULATION
1034 	/* (reason & REASON_ILLEGAL) would be the obvious thing here,
1035 	 * but there seems to be a hardware bug on the 405GP (RevD)
1036 	 * that means ESR is sometimes set incorrectly - either to
1037 	 * ESR_DST (!?) or 0.  In the process of chasing this with the
1038 	 * hardware people - not sure if it can happen on any illegal
1039 	 * instruction or only on FP instructions, whether there is a
1040 	 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
1041 	switch (do_mathemu(regs)) {
1042 	case 0:
1043 		emulate_single_step(regs);
1044 		return;
1045 	case 1: {
1046 			int code = 0;
1047 			code = __parse_fpscr(current->thread.fpscr.val);
1048 			_exception(SIGFPE, regs, code, regs->nip);
1049 			return;
1050 		}
1051 	case -EFAULT:
1052 		_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1053 		return;
1054 	}
1055 	/* fall through on any other errors */
1056 #endif /* CONFIG_MATH_EMULATION */
1057 
1058 	/* Try to emulate it if we should. */
1059 	if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1060 		switch (emulate_instruction(regs)) {
1061 		case 0:
1062 			regs->nip += 4;
1063 			emulate_single_step(regs);
1064 			return;
1065 		case -EFAULT:
1066 			_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1067 			return;
1068 		}
1069 	}
1070 
1071 	if (reason & REASON_PRIVILEGED)
1072 		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1073 	else
1074 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1075 }
1076 
alignment_exception(struct pt_regs * regs)1077 void alignment_exception(struct pt_regs *regs)
1078 {
1079 	int sig, code, fixed = 0;
1080 
1081 	/* We restore the interrupt state now */
1082 	if (!arch_irq_disabled_regs(regs))
1083 		local_irq_enable();
1084 
1085 	/* we don't implement logging of alignment exceptions */
1086 	if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1087 		fixed = fix_alignment(regs);
1088 
1089 	if (fixed == 1) {
1090 		regs->nip += 4;	/* skip over emulated instruction */
1091 		emulate_single_step(regs);
1092 		return;
1093 	}
1094 
1095 	/* Operand address was bad */
1096 	if (fixed == -EFAULT) {
1097 		sig = SIGSEGV;
1098 		code = SEGV_ACCERR;
1099 	} else {
1100 		sig = SIGBUS;
1101 		code = BUS_ADRALN;
1102 	}
1103 	if (user_mode(regs))
1104 		_exception(sig, regs, code, regs->dar);
1105 	else
1106 		bad_page_fault(regs, regs->dar, sig);
1107 }
1108 
StackOverflow(struct pt_regs * regs)1109 void StackOverflow(struct pt_regs *regs)
1110 {
1111 	printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1112 	       current, regs->gpr[1]);
1113 	debugger(regs);
1114 	show_regs(regs);
1115 	panic("kernel stack overflow");
1116 }
1117 
nonrecoverable_exception(struct pt_regs * regs)1118 void nonrecoverable_exception(struct pt_regs *regs)
1119 {
1120 	printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1121 	       regs->nip, regs->msr);
1122 	debugger(regs);
1123 	die("nonrecoverable exception", regs, SIGKILL);
1124 }
1125 
trace_syscall(struct pt_regs * regs)1126 void trace_syscall(struct pt_regs *regs)
1127 {
1128 	printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld    %s\n",
1129 	       current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1130 	       regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1131 }
1132 
kernel_fp_unavailable_exception(struct pt_regs * regs)1133 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1134 {
1135 	printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1136 			  "%lx at %lx\n", regs->trap, regs->nip);
1137 	die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1138 }
1139 
altivec_unavailable_exception(struct pt_regs * regs)1140 void altivec_unavailable_exception(struct pt_regs *regs)
1141 {
1142 	if (user_mode(regs)) {
1143 		/* A user program has executed an altivec instruction,
1144 		   but this kernel doesn't support altivec. */
1145 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1146 		return;
1147 	}
1148 
1149 	printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1150 			"%lx at %lx\n", regs->trap, regs->nip);
1151 	die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1152 }
1153 
vsx_unavailable_exception(struct pt_regs * regs)1154 void vsx_unavailable_exception(struct pt_regs *regs)
1155 {
1156 	if (user_mode(regs)) {
1157 		/* A user program has executed an vsx instruction,
1158 		   but this kernel doesn't support vsx. */
1159 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1160 		return;
1161 	}
1162 
1163 	printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1164 			"%lx at %lx\n", regs->trap, regs->nip);
1165 	die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1166 }
1167 
performance_monitor_exception(struct pt_regs * regs)1168 void performance_monitor_exception(struct pt_regs *regs)
1169 {
1170 	__get_cpu_var(irq_stat).pmu_irqs++;
1171 
1172 	perf_irq(regs);
1173 }
1174 
1175 #ifdef CONFIG_8xx
SoftwareEmulation(struct pt_regs * regs)1176 void SoftwareEmulation(struct pt_regs *regs)
1177 {
1178 	extern int do_mathemu(struct pt_regs *);
1179 	extern int Soft_emulate_8xx(struct pt_regs *);
1180 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
1181 	int errcode;
1182 #endif
1183 
1184 	CHECK_FULL_REGS(regs);
1185 
1186 	if (!user_mode(regs)) {
1187 		debugger(regs);
1188 		die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1189 	}
1190 
1191 #ifdef CONFIG_MATH_EMULATION
1192 	errcode = do_mathemu(regs);
1193 	if (errcode >= 0)
1194 		PPC_WARN_EMULATED(math, regs);
1195 
1196 	switch (errcode) {
1197 	case 0:
1198 		emulate_single_step(regs);
1199 		return;
1200 	case 1: {
1201 			int code = 0;
1202 			code = __parse_fpscr(current->thread.fpscr.val);
1203 			_exception(SIGFPE, regs, code, regs->nip);
1204 			return;
1205 		}
1206 	case -EFAULT:
1207 		_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1208 		return;
1209 	default:
1210 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1211 		return;
1212 	}
1213 
1214 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1215 	errcode = Soft_emulate_8xx(regs);
1216 	if (errcode >= 0)
1217 		PPC_WARN_EMULATED(8xx, regs);
1218 
1219 	switch (errcode) {
1220 	case 0:
1221 		emulate_single_step(regs);
1222 		return;
1223 	case 1:
1224 		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1225 		return;
1226 	case -EFAULT:
1227 		_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1228 		return;
1229 	}
1230 #else
1231 	_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1232 #endif
1233 }
1234 #endif /* CONFIG_8xx */
1235 
1236 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
handle_debug(struct pt_regs * regs,unsigned long debug_status)1237 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1238 {
1239 	int changed = 0;
1240 	/*
1241 	 * Determine the cause of the debug event, clear the
1242 	 * event flags and send a trap to the handler. Torez
1243 	 */
1244 	if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1245 		dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1246 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1247 		current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1248 #endif
1249 		do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1250 			     5);
1251 		changed |= 0x01;
1252 	}  else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1253 		dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1254 		do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1255 			     6);
1256 		changed |= 0x01;
1257 	}  else if (debug_status & DBSR_IAC1) {
1258 		current->thread.dbcr0 &= ~DBCR0_IAC1;
1259 		dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1260 		do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1261 			     1);
1262 		changed |= 0x01;
1263 	}  else if (debug_status & DBSR_IAC2) {
1264 		current->thread.dbcr0 &= ~DBCR0_IAC2;
1265 		do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1266 			     2);
1267 		changed |= 0x01;
1268 	}  else if (debug_status & DBSR_IAC3) {
1269 		current->thread.dbcr0 &= ~DBCR0_IAC3;
1270 		dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1271 		do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1272 			     3);
1273 		changed |= 0x01;
1274 	}  else if (debug_status & DBSR_IAC4) {
1275 		current->thread.dbcr0 &= ~DBCR0_IAC4;
1276 		do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1277 			     4);
1278 		changed |= 0x01;
1279 	}
1280 	/*
1281 	 * At the point this routine was called, the MSR(DE) was turned off.
1282 	 * Check all other debug flags and see if that bit needs to be turned
1283 	 * back on or not.
1284 	 */
1285 	if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
1286 		regs->msr |= MSR_DE;
1287 	else
1288 		/* Make sure the IDM flag is off */
1289 		current->thread.dbcr0 &= ~DBCR0_IDM;
1290 
1291 	if (changed & 0x01)
1292 		mtspr(SPRN_DBCR0, current->thread.dbcr0);
1293 }
1294 
DebugException(struct pt_regs * regs,unsigned long debug_status)1295 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1296 {
1297 	current->thread.dbsr = debug_status;
1298 
1299 	/* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1300 	 * on server, it stops on the target of the branch. In order to simulate
1301 	 * the server behaviour, we thus restart right away with a single step
1302 	 * instead of stopping here when hitting a BT
1303 	 */
1304 	if (debug_status & DBSR_BT) {
1305 		regs->msr &= ~MSR_DE;
1306 
1307 		/* Disable BT */
1308 		mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1309 		/* Clear the BT event */
1310 		mtspr(SPRN_DBSR, DBSR_BT);
1311 
1312 		/* Do the single step trick only when coming from userspace */
1313 		if (user_mode(regs)) {
1314 			current->thread.dbcr0 &= ~DBCR0_BT;
1315 			current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1316 			regs->msr |= MSR_DE;
1317 			return;
1318 		}
1319 
1320 		if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1321 			       5, SIGTRAP) == NOTIFY_STOP) {
1322 			return;
1323 		}
1324 		if (debugger_sstep(regs))
1325 			return;
1326 	} else if (debug_status & DBSR_IC) { 	/* Instruction complete */
1327 		regs->msr &= ~MSR_DE;
1328 
1329 		/* Disable instruction completion */
1330 		mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1331 		/* Clear the instruction completion event */
1332 		mtspr(SPRN_DBSR, DBSR_IC);
1333 
1334 		if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1335 			       5, SIGTRAP) == NOTIFY_STOP) {
1336 			return;
1337 		}
1338 
1339 		if (debugger_sstep(regs))
1340 			return;
1341 
1342 		if (user_mode(regs)) {
1343 			current->thread.dbcr0 &= ~DBCR0_IC;
1344 			if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
1345 					       current->thread.dbcr1))
1346 				regs->msr |= MSR_DE;
1347 			else
1348 				/* Make sure the IDM bit is off */
1349 				current->thread.dbcr0 &= ~DBCR0_IDM;
1350 		}
1351 
1352 		_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1353 	} else
1354 		handle_debug(regs, debug_status);
1355 }
1356 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1357 
1358 #if !defined(CONFIG_TAU_INT)
TAUException(struct pt_regs * regs)1359 void TAUException(struct pt_regs *regs)
1360 {
1361 	printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
1362 	       regs->nip, regs->msr, regs->trap, print_tainted());
1363 }
1364 #endif /* CONFIG_INT_TAU */
1365 
1366 #ifdef CONFIG_ALTIVEC
altivec_assist_exception(struct pt_regs * regs)1367 void altivec_assist_exception(struct pt_regs *regs)
1368 {
1369 	int err;
1370 
1371 	if (!user_mode(regs)) {
1372 		printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1373 		       " at %lx\n", regs->nip);
1374 		die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1375 	}
1376 
1377 	flush_altivec_to_thread(current);
1378 
1379 	PPC_WARN_EMULATED(altivec, regs);
1380 	err = emulate_altivec(regs);
1381 	if (err == 0) {
1382 		regs->nip += 4;		/* skip emulated instruction */
1383 		emulate_single_step(regs);
1384 		return;
1385 	}
1386 
1387 	if (err == -EFAULT) {
1388 		/* got an error reading the instruction */
1389 		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1390 	} else {
1391 		/* didn't recognize the instruction */
1392 		/* XXX quick hack for now: set the non-Java bit in the VSCR */
1393 		printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1394 				   "in %s at %lx\n", current->comm, regs->nip);
1395 		current->thread.vscr.u[3] |= 0x10000;
1396 	}
1397 }
1398 #endif /* CONFIG_ALTIVEC */
1399 
1400 #ifdef CONFIG_VSX
vsx_assist_exception(struct pt_regs * regs)1401 void vsx_assist_exception(struct pt_regs *regs)
1402 {
1403 	if (!user_mode(regs)) {
1404 		printk(KERN_EMERG "VSX assist exception in kernel mode"
1405 		       " at %lx\n", regs->nip);
1406 		die("Kernel VSX assist exception", regs, SIGILL);
1407 	}
1408 
1409 	flush_vsx_to_thread(current);
1410 	printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1411 	_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1412 }
1413 #endif /* CONFIG_VSX */
1414 
1415 #ifdef CONFIG_FSL_BOOKE
CacheLockingException(struct pt_regs * regs,unsigned long address,unsigned long error_code)1416 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1417 			   unsigned long error_code)
1418 {
1419 	/* We treat cache locking instructions from the user
1420 	 * as priv ops, in the future we could try to do
1421 	 * something smarter
1422 	 */
1423 	if (error_code & (ESR_DLK|ESR_ILK))
1424 		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1425 	return;
1426 }
1427 #endif /* CONFIG_FSL_BOOKE */
1428 
1429 #ifdef CONFIG_SPE
SPEFloatingPointException(struct pt_regs * regs)1430 void SPEFloatingPointException(struct pt_regs *regs)
1431 {
1432 	extern int do_spe_mathemu(struct pt_regs *regs);
1433 	unsigned long spefscr;
1434 	int fpexc_mode;
1435 	int code = 0;
1436 	int err;
1437 
1438 	flush_spe_to_thread(current);
1439 
1440 	spefscr = current->thread.spefscr;
1441 	fpexc_mode = current->thread.fpexc_mode;
1442 
1443 	if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1444 		code = FPE_FLTOVF;
1445 	}
1446 	else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1447 		code = FPE_FLTUND;
1448 	}
1449 	else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1450 		code = FPE_FLTDIV;
1451 	else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1452 		code = FPE_FLTINV;
1453 	}
1454 	else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1455 		code = FPE_FLTRES;
1456 
1457 	err = do_spe_mathemu(regs);
1458 	if (err == 0) {
1459 		regs->nip += 4;		/* skip emulated instruction */
1460 		emulate_single_step(regs);
1461 		return;
1462 	}
1463 
1464 	if (err == -EFAULT) {
1465 		/* got an error reading the instruction */
1466 		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1467 	} else if (err == -EINVAL) {
1468 		/* didn't recognize the instruction */
1469 		printk(KERN_ERR "unrecognized spe instruction "
1470 		       "in %s at %lx\n", current->comm, regs->nip);
1471 	} else {
1472 		_exception(SIGFPE, regs, code, regs->nip);
1473 	}
1474 
1475 	return;
1476 }
1477 
SPEFloatingPointRoundException(struct pt_regs * regs)1478 void SPEFloatingPointRoundException(struct pt_regs *regs)
1479 {
1480 	extern int speround_handler(struct pt_regs *regs);
1481 	int err;
1482 
1483 	preempt_disable();
1484 	if (regs->msr & MSR_SPE)
1485 		giveup_spe(current);
1486 	preempt_enable();
1487 
1488 	regs->nip -= 4;
1489 	err = speround_handler(regs);
1490 	if (err == 0) {
1491 		regs->nip += 4;		/* skip emulated instruction */
1492 		emulate_single_step(regs);
1493 		return;
1494 	}
1495 
1496 	if (err == -EFAULT) {
1497 		/* got an error reading the instruction */
1498 		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1499 	} else if (err == -EINVAL) {
1500 		/* didn't recognize the instruction */
1501 		printk(KERN_ERR "unrecognized spe instruction "
1502 		       "in %s at %lx\n", current->comm, regs->nip);
1503 	} else {
1504 		_exception(SIGFPE, regs, 0, regs->nip);
1505 		return;
1506 	}
1507 }
1508 #endif
1509 
1510 /*
1511  * We enter here if we get an unrecoverable exception, that is, one
1512  * that happened at a point where the RI (recoverable interrupt) bit
1513  * in the MSR is 0.  This indicates that SRR0/1 are live, and that
1514  * we therefore lost state by taking this exception.
1515  */
unrecoverable_exception(struct pt_regs * regs)1516 void unrecoverable_exception(struct pt_regs *regs)
1517 {
1518 	printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1519 	       regs->trap, regs->nip);
1520 	die("Unrecoverable exception", regs, SIGABRT);
1521 }
1522 
1523 #ifdef CONFIG_BOOKE_WDT
1524 /*
1525  * Default handler for a Watchdog exception,
1526  * spins until a reboot occurs
1527  */
WatchdogHandler(struct pt_regs * regs)1528 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1529 {
1530 	/* Generic WatchdogHandler, implement your own */
1531 	mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1532 	return;
1533 }
1534 
WatchdogException(struct pt_regs * regs)1535 void WatchdogException(struct pt_regs *regs)
1536 {
1537 	printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1538 	WatchdogHandler(regs);
1539 }
1540 #endif
1541 
1542 /*
1543  * We enter here if we discover during exception entry that we are
1544  * running in supervisor mode with a userspace value in the stack pointer.
1545  */
kernel_bad_stack(struct pt_regs * regs)1546 void kernel_bad_stack(struct pt_regs *regs)
1547 {
1548 	printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1549 	       regs->gpr[1], regs->nip);
1550 	die("Bad kernel stack pointer", regs, SIGABRT);
1551 }
1552 
trap_init(void)1553 void __init trap_init(void)
1554 {
1555 }
1556 
1557 
1558 #ifdef CONFIG_PPC_EMULATED_STATS
1559 
1560 #define WARN_EMULATED_SETUP(type)	.type = { .name = #type }
1561 
1562 struct ppc_emulated ppc_emulated = {
1563 #ifdef CONFIG_ALTIVEC
1564 	WARN_EMULATED_SETUP(altivec),
1565 #endif
1566 	WARN_EMULATED_SETUP(dcba),
1567 	WARN_EMULATED_SETUP(dcbz),
1568 	WARN_EMULATED_SETUP(fp_pair),
1569 	WARN_EMULATED_SETUP(isel),
1570 	WARN_EMULATED_SETUP(mcrxr),
1571 	WARN_EMULATED_SETUP(mfpvr),
1572 	WARN_EMULATED_SETUP(multiple),
1573 	WARN_EMULATED_SETUP(popcntb),
1574 	WARN_EMULATED_SETUP(spe),
1575 	WARN_EMULATED_SETUP(string),
1576 	WARN_EMULATED_SETUP(unaligned),
1577 #ifdef CONFIG_MATH_EMULATION
1578 	WARN_EMULATED_SETUP(math),
1579 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1580 	WARN_EMULATED_SETUP(8xx),
1581 #endif
1582 #ifdef CONFIG_VSX
1583 	WARN_EMULATED_SETUP(vsx),
1584 #endif
1585 #ifdef CONFIG_PPC64
1586 	WARN_EMULATED_SETUP(mfdscr),
1587 	WARN_EMULATED_SETUP(mtdscr),
1588 #endif
1589 };
1590 
1591 u32 ppc_warn_emulated;
1592 
ppc_warn_emulated_print(const char * type)1593 void ppc_warn_emulated_print(const char *type)
1594 {
1595 	pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1596 			    type);
1597 }
1598 
ppc_warn_emulated_init(void)1599 static int __init ppc_warn_emulated_init(void)
1600 {
1601 	struct dentry *dir, *d;
1602 	unsigned int i;
1603 	struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1604 
1605 	if (!powerpc_debugfs_root)
1606 		return -ENODEV;
1607 
1608 	dir = debugfs_create_dir("emulated_instructions",
1609 				 powerpc_debugfs_root);
1610 	if (!dir)
1611 		return -ENOMEM;
1612 
1613 	d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1614 			       &ppc_warn_emulated);
1615 	if (!d)
1616 		goto fail;
1617 
1618 	for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1619 		d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1620 				       (u32 *)&entries[i].val.counter);
1621 		if (!d)
1622 			goto fail;
1623 	}
1624 
1625 	return 0;
1626 
1627 fail:
1628 	debugfs_remove_recursive(dir);
1629 	return -ENOMEM;
1630 }
1631 
1632 device_initcall(ppc_warn_emulated_init);
1633 
1634 #endif /* CONFIG_PPC_EMULATED_STATS */
1635