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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef ATH9K_H
18 #define ATH9K_H
19 
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <linux/interrupt.h>
23 #include <linux/leds.h>
24 #include <linux/completion.h>
25 
26 #include "debug.h"
27 #include "common.h"
28 #include "mci.h"
29 
30 /*
31  * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
32  * should rely on this file or its contents.
33  */
34 
35 struct ath_node;
36 
37 /* Macro to expand scalars to 64-bit objects */
38 
39 #define	ito64(x) (sizeof(x) == 1) ?			\
40 	(((unsigned long long int)(x)) & (0xff)) :	\
41 	(sizeof(x) == 2) ?				\
42 	(((unsigned long long int)(x)) & 0xffff) :	\
43 	((sizeof(x) == 4) ?				\
44 	 (((unsigned long long int)(x)) & 0xffffffff) : \
45 	 (unsigned long long int)(x))
46 
47 /* increment with wrap-around */
48 #define INCR(_l, _sz)   do {			\
49 		(_l)++;				\
50 		(_l) &= ((_sz) - 1);		\
51 	} while (0)
52 
53 /* decrement with wrap-around */
54 #define DECR(_l,  _sz)  do {			\
55 		(_l)--;				\
56 		(_l) &= ((_sz) - 1);		\
57 	} while (0)
58 
59 #define TSF_TO_TU(_h,_l) \
60 	((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
61 
62 #define	ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
63 
64 struct ath_config {
65 	u16 txpowlimit;
66 	u8 cabqReadytime;
67 };
68 
69 /*************************/
70 /* Descriptor Management */
71 /*************************/
72 
73 #define ATH_TXBUF_RESET(_bf) do {				\
74 		(_bf)->bf_stale = false;			\
75 		(_bf)->bf_lastbf = NULL;			\
76 		(_bf)->bf_next = NULL;				\
77 		memset(&((_bf)->bf_state), 0,			\
78 		       sizeof(struct ath_buf_state));		\
79 	} while (0)
80 
81 /**
82  * enum buffer_type - Buffer type flags
83  *
84  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
85  * @BUF_AGGR: Indicates whether the buffer can be aggregated
86  *	(used in aggregation scheduling)
87  */
88 enum buffer_type {
89 	BUF_AMPDU		= BIT(0),
90 	BUF_AGGR		= BIT(1),
91 };
92 
93 #define bf_isampdu(bf)		(bf->bf_state.bf_type & BUF_AMPDU)
94 #define bf_isaggr(bf)		(bf->bf_state.bf_type & BUF_AGGR)
95 
96 #define ATH_TXSTATUS_RING_SIZE 512
97 
98 #define	DS2PHYS(_dd, _ds)						\
99 	((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
100 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
101 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
102 
103 struct ath_descdma {
104 	void *dd_desc;
105 	dma_addr_t dd_desc_paddr;
106 	u32 dd_desc_len;
107 	struct ath_buf *dd_bufptr;
108 };
109 
110 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
111 		      struct list_head *head, const char *name,
112 		      int nbuf, int ndesc, bool is_tx);
113 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
114 			 struct list_head *head);
115 
116 /***********/
117 /* RX / TX */
118 /***********/
119 
120 #define ATH_RXBUF               512
121 #define ATH_TXBUF               512
122 #define ATH_TXBUF_RESERVE       5
123 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
124 #define ATH_TXMAXTRY            13
125 
126 #define TID_TO_WME_AC(_tid)				\
127 	((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE :	\
128 	 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK :	\
129 	 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI :	\
130 	 WME_AC_VO)
131 
132 #define ATH_AGGR_DELIM_SZ          4
133 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
134 /* number of delimiters for encryption padding */
135 #define ATH_AGGR_ENCRYPTDELIM      10
136 /* minimum h/w qdepth to be sustained to maximize aggregation */
137 #define ATH_AGGR_MIN_QDEPTH        2
138 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
139 
140 #define IEEE80211_SEQ_SEQ_SHIFT    4
141 #define IEEE80211_SEQ_MAX          4096
142 #define IEEE80211_WEP_IVLEN        3
143 #define IEEE80211_WEP_KIDLEN       1
144 #define IEEE80211_WEP_CRCLEN       4
145 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +		\
146 				    (IEEE80211_WEP_IVLEN +	\
147 				     IEEE80211_WEP_KIDLEN +	\
148 				     IEEE80211_WEP_CRCLEN))
149 
150 /* return whether a bit at index _n in bitmap _bm is set
151  * _sz is the size of the bitmap  */
152 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&		\
153 				((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
154 
155 /* return block-ack bitmap index given sequence and starting sequence */
156 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
157 
158 /* return the seqno for _start + _offset */
159 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
160 
161 /* returns delimiter padding required given the packet length */
162 #define ATH_AGGR_GET_NDELIM(_len)					\
163        (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
164         DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
165 
166 #define BAW_WITHIN(_start, _bawsz, _seqno) \
167 	((((_seqno) - (_start)) & 4095) < (_bawsz))
168 
169 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
170 
171 #define ATH_TX_COMPLETE_POLL_INT	1000
172 
173 enum ATH_AGGR_STATUS {
174 	ATH_AGGR_DONE,
175 	ATH_AGGR_BAW_CLOSED,
176 	ATH_AGGR_LIMITED,
177 };
178 
179 #define ATH_TXFIFO_DEPTH 8
180 struct ath_txq {
181 	int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
182 	u32 axq_qnum; /* ath9k hardware queue number */
183 	void *axq_link;
184 	struct list_head axq_q;
185 	spinlock_t axq_lock;
186 	u32 axq_depth;
187 	u32 axq_ampdu_depth;
188 	bool stopped;
189 	bool axq_tx_inprogress;
190 	struct list_head axq_acq;
191 	struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
192 	u8 txq_headidx;
193 	u8 txq_tailidx;
194 	int pending_frames;
195 	struct sk_buff_head complete_q;
196 };
197 
198 struct ath_atx_ac {
199 	struct ath_txq *txq;
200 	int sched;
201 	struct list_head list;
202 	struct list_head tid_q;
203 	bool clear_ps_filter;
204 };
205 
206 struct ath_frame_info {
207 	struct ath_buf *bf;
208 	int framelen;
209 	enum ath9k_key_type keytype;
210 	u8 keyix;
211 	u8 retries;
212 	u8 rtscts_rate;
213 };
214 
215 struct ath_buf_state {
216 	u8 bf_type;
217 	u8 bfs_paprd;
218 	u8 ndelim;
219 	u16 seqno;
220 	unsigned long bfs_paprd_timestamp;
221 };
222 
223 struct ath_buf {
224 	struct list_head list;
225 	struct ath_buf *bf_lastbf;	/* last buf of this unit (a frame or
226 					   an aggregate) */
227 	struct ath_buf *bf_next;	/* next subframe in the aggregate */
228 	struct sk_buff *bf_mpdu;	/* enclosing frame structure */
229 	void *bf_desc;			/* virtual addr of desc */
230 	dma_addr_t bf_daddr;		/* physical addr of desc */
231 	dma_addr_t bf_buf_addr;	/* physical addr of data buffer, for DMA */
232 	bool bf_stale;
233 	struct ath_buf_state bf_state;
234 };
235 
236 struct ath_atx_tid {
237 	struct list_head list;
238 	struct sk_buff_head buf_q;
239 	struct ath_node *an;
240 	struct ath_atx_ac *ac;
241 	unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
242 	int bar_index;
243 	u16 seq_start;
244 	u16 seq_next;
245 	u16 baw_size;
246 	int tidno;
247 	int baw_head;   /* first un-acked tx buffer */
248 	int baw_tail;   /* next unused tx buffer slot */
249 	int sched;
250 	int paused;
251 	u8 state;
252 };
253 
254 struct ath_node {
255 #ifdef CONFIG_ATH9K_DEBUGFS
256 	struct list_head list; /* for sc->nodes */
257 #endif
258 	struct ieee80211_sta *sta; /* station struct we're part of */
259 	struct ieee80211_vif *vif; /* interface with which we're associated */
260 	struct ath_atx_tid tid[WME_NUM_TID];
261 	struct ath_atx_ac ac[WME_NUM_AC];
262 	int ps_key;
263 
264 	u16 maxampdu;
265 	u8 mpdudensity;
266 
267 	bool sleeping;
268 };
269 
270 #define AGGR_CLEANUP         BIT(1)
271 #define AGGR_ADDBA_COMPLETE  BIT(2)
272 #define AGGR_ADDBA_PROGRESS  BIT(3)
273 
274 struct ath_tx_control {
275 	struct ath_txq *txq;
276 	struct ath_node *an;
277 	u8 paprd;
278 };
279 
280 #define ATH_TX_ERROR        0x01
281 
282 /**
283  * @txq_map:  Index is mac80211 queue number.  This is
284  *  not necessarily the same as the hardware queue number
285  *  (axq_qnum).
286  */
287 struct ath_tx {
288 	u16 seq_no;
289 	u32 txqsetup;
290 	spinlock_t txbuflock;
291 	struct list_head txbuf;
292 	struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
293 	struct ath_descdma txdma;
294 	struct ath_txq *txq_map[WME_NUM_AC];
295 };
296 
297 struct ath_rx_edma {
298 	struct sk_buff_head rx_fifo;
299 	u32 rx_fifo_hwsize;
300 };
301 
302 struct ath_rx {
303 	u8 defant;
304 	u8 rxotherant;
305 	u32 *rxlink;
306 	unsigned int rxfilter;
307 	spinlock_t rxbuflock;
308 	struct list_head rxbuf;
309 	struct ath_descdma rxdma;
310 	struct ath_buf *rx_bufptr;
311 	struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
312 
313 	struct ath_buf *buf_hold;
314 	struct sk_buff *frag;
315 };
316 
317 int ath_startrecv(struct ath_softc *sc);
318 bool ath_stoprecv(struct ath_softc *sc);
319 void ath_flushrecv(struct ath_softc *sc);
320 u32 ath_calcrxfilter(struct ath_softc *sc);
321 int ath_rx_init(struct ath_softc *sc, int nbufs);
322 void ath_rx_cleanup(struct ath_softc *sc);
323 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
324 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
325 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
326 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
327 void ath_draintxq(struct ath_softc *sc,
328 		     struct ath_txq *txq, bool retry_tx);
329 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
330 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
331 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
332 int ath_tx_init(struct ath_softc *sc, int nbufs);
333 void ath_tx_cleanup(struct ath_softc *sc);
334 int ath_txq_update(struct ath_softc *sc, int qnum,
335 		   struct ath9k_tx_queue_info *q);
336 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
337 		 struct ath_tx_control *txctl);
338 void ath_tx_tasklet(struct ath_softc *sc);
339 void ath_tx_edma_tasklet(struct ath_softc *sc);
340 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
341 		      u16 tid, u16 *ssn);
342 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
343 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
344 
345 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
346 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
347 		       struct ath_node *an);
348 
349 /********/
350 /* VIFs */
351 /********/
352 
353 struct ath_vif {
354 	int av_bslot;
355 	bool is_bslot_active, primary_sta_vif;
356 	__le64 tsf_adjust; /* TSF adjustment for staggered beacons */
357 	struct ath_buf *av_bcbuf;
358 };
359 
360 /*******************/
361 /* Beacon Handling */
362 /*******************/
363 
364 /*
365  * Regardless of the number of beacons we stagger, (i.e. regardless of the
366  * number of BSSIDs) if a given beacon does not go out even after waiting this
367  * number of beacon intervals, the game's up.
368  */
369 #define BSTUCK_THRESH           	9
370 #define	ATH_BCBUF               	4
371 #define ATH_DEFAULT_BINTVAL     	100 /* TU */
372 #define ATH_DEFAULT_BMISS_LIMIT 	10
373 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
374 
375 struct ath_beacon_config {
376 	int beacon_interval;
377 	u16 listen_interval;
378 	u16 dtim_period;
379 	u16 bmiss_timeout;
380 	u8 dtim_count;
381 };
382 
383 struct ath_beacon {
384 	enum {
385 		OK,		/* no change needed */
386 		UPDATE,		/* update pending */
387 		COMMIT		/* beacon sent, commit change */
388 	} updateslot;		/* slot time update fsm */
389 
390 	u32 beaconq;
391 	u32 bmisscnt;
392 	u32 ast_be_xmit;
393 	u32 bc_tstamp;
394 	struct ieee80211_vif *bslot[ATH_BCBUF];
395 	int slottime;
396 	int slotupdate;
397 	struct ath9k_tx_queue_info beacon_qi;
398 	struct ath_descdma bdma;
399 	struct ath_txq *cabq;
400 	struct list_head bbuf;
401 
402 	bool tx_processed;
403 	bool tx_last;
404 };
405 
406 void ath_beacon_tasklet(unsigned long data);
407 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
408 int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
409 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
410 int ath_beaconq_config(struct ath_softc *sc);
411 void ath_set_beacon(struct ath_softc *sc);
412 void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
413 
414 /*******/
415 /* ANI */
416 /*******/
417 
418 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
419 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
420 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
421 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
422 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
423 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
424 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
425 
426 #define ATH_PAPRD_TIMEOUT	100 /* msecs */
427 
428 void ath_reset_work(struct work_struct *work);
429 void ath_hw_check(struct work_struct *work);
430 void ath_hw_pll_work(struct work_struct *work);
431 void ath_paprd_calibrate(struct work_struct *work);
432 void ath_ani_calibrate(unsigned long data);
433 void ath_start_ani(struct ath_common *common);
434 
435 /**********/
436 /* BTCOEX */
437 /**********/
438 
439 struct ath_btcoex {
440 	bool hw_timer_enabled;
441 	spinlock_t btcoex_lock;
442 	struct timer_list period_timer; /* Timer for BT period */
443 	u32 bt_priority_cnt;
444 	unsigned long bt_priority_time;
445 	int bt_stomp_type; /* Types of BT stomping */
446 	u32 btcoex_no_stomp; /* in usec */
447 	u32 btcoex_period; /* in usec */
448 	u32 btscan_no_stomp; /* in usec */
449 	u32 duty_cycle;
450 	struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
451 	struct ath_mci_profile mci;
452 };
453 
454 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
455 int ath9k_init_btcoex(struct ath_softc *sc);
456 void ath9k_deinit_btcoex(struct ath_softc *sc);
457 void ath9k_start_btcoex(struct ath_softc *sc);
458 void ath9k_stop_btcoex(struct ath_softc *sc);
459 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
460 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
461 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
462 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
463 #else
ath9k_init_btcoex(struct ath_softc * sc)464 static inline int ath9k_init_btcoex(struct ath_softc *sc)
465 {
466 	return 0;
467 }
ath9k_deinit_btcoex(struct ath_softc * sc)468 static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
469 {
470 }
ath9k_start_btcoex(struct ath_softc * sc)471 static inline void ath9k_start_btcoex(struct ath_softc *sc)
472 {
473 }
ath9k_stop_btcoex(struct ath_softc * sc)474 static inline void ath9k_stop_btcoex(struct ath_softc *sc)
475 {
476 }
ath9k_btcoex_handle_interrupt(struct ath_softc * sc,u32 status)477 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
478 						 u32 status)
479 {
480 }
ath9k_btcoex_aggr_limit(struct ath_softc * sc,u32 max_4ms_framelen)481 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
482 					  u32 max_4ms_framelen)
483 {
484 	return 0;
485 }
486 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
487 
488 /********************/
489 /*   LED Control    */
490 /********************/
491 
492 #define ATH_LED_PIN_DEF 		1
493 #define ATH_LED_PIN_9287		8
494 #define ATH_LED_PIN_9300		10
495 #define ATH_LED_PIN_9485		6
496 #define ATH_LED_PIN_9462		4
497 
498 #ifdef CONFIG_MAC80211_LEDS
499 void ath_init_leds(struct ath_softc *sc);
500 void ath_deinit_leds(struct ath_softc *sc);
501 #else
ath_init_leds(struct ath_softc * sc)502 static inline void ath_init_leds(struct ath_softc *sc)
503 {
504 }
505 
ath_deinit_leds(struct ath_softc * sc)506 static inline void ath_deinit_leds(struct ath_softc *sc)
507 {
508 }
509 #endif
510 
511 
512 /* Antenna diversity/combining */
513 #define ATH_ANT_RX_CURRENT_SHIFT 4
514 #define ATH_ANT_RX_MAIN_SHIFT 2
515 #define ATH_ANT_RX_MASK 0x3
516 
517 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
518 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
519 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
520 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
521 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
522 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
523 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
524 
525 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
526 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
527 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
528 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
529 
530 enum ath9k_ant_div_comb_lna_conf {
531 	ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
532 	ATH_ANT_DIV_COMB_LNA2,
533 	ATH_ANT_DIV_COMB_LNA1,
534 	ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
535 };
536 
537 struct ath_ant_comb {
538 	u16 count;
539 	u16 total_pkt_count;
540 	bool scan;
541 	bool scan_not_start;
542 	int main_total_rssi;
543 	int alt_total_rssi;
544 	int alt_recv_cnt;
545 	int main_recv_cnt;
546 	int rssi_lna1;
547 	int rssi_lna2;
548 	int rssi_add;
549 	int rssi_sub;
550 	int rssi_first;
551 	int rssi_second;
552 	int rssi_third;
553 	bool alt_good;
554 	int quick_scan_cnt;
555 	int main_conf;
556 	enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
557 	enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
558 	int first_bias;
559 	int second_bias;
560 	bool first_ratio;
561 	bool second_ratio;
562 	unsigned long scan_start_time;
563 };
564 
565 /********************/
566 /* Main driver core */
567 /********************/
568 
569 /*
570  * Default cache line size, in bytes.
571  * Used when PCI device not fully initialized by bootrom/BIOS
572 */
573 #define DEFAULT_CACHELINE       32
574 #define ATH_REGCLASSIDS_MAX     10
575 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
576 #define ATH_MAX_SW_RETRIES      30
577 #define ATH_CHAN_MAX            255
578 
579 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
580 #define ATH_RATE_DUMMY_MARKER   0
581 
582 #define SC_OP_INVALID                BIT(0)
583 #define SC_OP_BEACONS                BIT(1)
584 #define SC_OP_OFFCHANNEL             BIT(2)
585 #define SC_OP_RXFLUSH                BIT(3)
586 #define SC_OP_TSF_RESET              BIT(4)
587 #define SC_OP_BT_PRIORITY_DETECTED   BIT(5)
588 #define SC_OP_BT_SCAN                BIT(6)
589 #define SC_OP_ANI_RUN                BIT(7)
590 #define SC_OP_PRIM_STA_VIF           BIT(8)
591 
592 /* Powersave flags */
593 #define PS_WAIT_FOR_BEACON        BIT(0)
594 #define PS_WAIT_FOR_CAB           BIT(1)
595 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
596 #define PS_WAIT_FOR_TX_ACK        BIT(3)
597 #define PS_BEACON_SYNC            BIT(4)
598 
599 struct ath_rate_table;
600 
601 struct ath9k_vif_iter_data {
602 	const u8 *hw_macaddr; /* phy's hardware address, set
603 			       * before starting iteration for
604 			       * valid bssid mask.
605 			       */
606 	u8 mask[ETH_ALEN]; /* bssid mask */
607 	int naps;      /* number of AP vifs */
608 	int nmeshes;   /* number of mesh vifs */
609 	int nstations; /* number of station vifs */
610 	int nwds;      /* number of WDS vifs */
611 	int nadhocs;   /* number of adhoc vifs */
612 };
613 
614 struct ath_softc {
615 	struct ieee80211_hw *hw;
616 	struct device *dev;
617 
618 	struct survey_info *cur_survey;
619 	struct survey_info survey[ATH9K_NUM_CHANNELS];
620 
621 	struct tasklet_struct intr_tq;
622 	struct tasklet_struct bcon_tasklet;
623 	struct ath_hw *sc_ah;
624 	void __iomem *mem;
625 	int irq;
626 	spinlock_t sc_serial_rw;
627 	spinlock_t sc_pm_lock;
628 	spinlock_t sc_pcu_lock;
629 	struct mutex mutex;
630 	struct work_struct paprd_work;
631 	struct work_struct hw_check_work;
632 	struct work_struct hw_reset_work;
633 	struct completion paprd_complete;
634 
635 	unsigned int hw_busy_count;
636 
637 	u32 intrstatus;
638 	u32 sc_flags; /* SC_OP_* */
639 	u16 ps_flags; /* PS_* */
640 	u16 curtxpow;
641 	bool ps_enabled;
642 	bool ps_idle;
643 	short nbcnvifs;
644 	short nvifs;
645 	unsigned long ps_usecount;
646 
647 	struct ath_config config;
648 	struct ath_rx rx;
649 	struct ath_tx tx;
650 	struct ath_beacon beacon;
651 	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
652 
653 #ifdef CONFIG_MAC80211_LEDS
654 	bool led_registered;
655 	char led_name[32];
656 	struct led_classdev led_cdev;
657 #endif
658 
659 	struct ath9k_hw_cal_data caldata;
660 	int last_rssi;
661 
662 #ifdef CONFIG_ATH9K_DEBUGFS
663 	struct ath9k_debug debug;
664 	spinlock_t nodes_lock;
665 	struct list_head nodes; /* basically, stations */
666 	unsigned int tx_complete_poll_work_seen;
667 #endif
668 	struct ath_beacon_config cur_beacon_conf;
669 	struct delayed_work tx_complete_work;
670 	struct delayed_work hw_pll_work;
671 
672 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
673 	struct ath_btcoex btcoex;
674 	struct ath_mci_coex mci_coex;
675 #endif
676 
677 	struct ath_descdma txsdma;
678 
679 	struct ath_ant_comb ant_comb;
680 	u8 ant_tx, ant_rx;
681 };
682 
683 void ath9k_tasklet(unsigned long data);
684 int ath_cabq_update(struct ath_softc *);
685 
ath_read_cachesize(struct ath_common * common,int * csz)686 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
687 {
688 	common->bus_ops->read_cachesize(common, csz);
689 }
690 
691 extern struct ieee80211_ops ath9k_ops;
692 extern int ath9k_modparam_nohwcrypt;
693 extern int led_blink;
694 extern bool is_ath9k_unloaded;
695 
696 irqreturn_t ath_isr(int irq, void *dev);
697 int ath9k_init_device(u16 devid, struct ath_softc *sc,
698 		    const struct ath_bus_ops *bus_ops);
699 void ath9k_deinit_device(struct ath_softc *sc);
700 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
701 void ath9k_reload_chainmask_settings(struct ath_softc *sc);
702 
703 bool ath9k_uses_beacons(int type);
704 
705 #ifdef CONFIG_ATH9K_PCI
706 int ath_pci_init(void);
707 void ath_pci_exit(void);
708 #else
ath_pci_init(void)709 static inline int ath_pci_init(void) { return 0; };
ath_pci_exit(void)710 static inline void ath_pci_exit(void) {};
711 #endif
712 
713 #ifdef CONFIG_ATH9K_AHB
714 int ath_ahb_init(void);
715 void ath_ahb_exit(void);
716 #else
ath_ahb_init(void)717 static inline int ath_ahb_init(void) { return 0; };
ath_ahb_exit(void)718 static inline void ath_ahb_exit(void) {};
719 #endif
720 
721 void ath9k_ps_wakeup(struct ath_softc *sc);
722 void ath9k_ps_restore(struct ath_softc *sc);
723 
724 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
725 
726 void ath_start_rfkill_poll(struct ath_softc *sc);
727 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
728 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
729 			       struct ieee80211_vif *vif,
730 			       struct ath9k_vif_iter_data *iter_data);
731 
732 
733 #endif /* ATH9K_H */
734