1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "ar9003_phy.h"
19 #include "ar9003_rtt.h"
20
21 #define RTT_RESTORE_TIMEOUT 1000
22 #define RTT_ACCESS_TIMEOUT 100
23 #define RTT_BAD_VALUE 0x0bad0bad
24
25 /*
26 * RTT (Radio Retention Table) hardware implementation information
27 *
28 * There is an internal table (i.e. the rtt) for each chain (or bank).
29 * Each table contains 6 entries and each entry is corresponding to
30 * a specific calibration parameter as depicted below.
31 * 0~2 - DC offset DAC calibration: loop, low, high (offsetI/Q_...)
32 * 3 - Filter cal (filterfc)
33 * 4 - RX gain settings
34 * 5 - Peak detector offset calibration (agc_caldac)
35 */
36
ar9003_hw_rtt_enable(struct ath_hw * ah)37 void ar9003_hw_rtt_enable(struct ath_hw *ah)
38 {
39 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1);
40 }
41
ar9003_hw_rtt_disable(struct ath_hw * ah)42 void ar9003_hw_rtt_disable(struct ath_hw *ah)
43 {
44 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0);
45 }
46
ar9003_hw_rtt_set_mask(struct ath_hw * ah,u32 rtt_mask)47 void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask)
48 {
49 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
50 AR_PHY_RTT_CTRL_RESTORE_MASK, rtt_mask);
51 }
52
ar9003_hw_rtt_force_restore(struct ath_hw * ah)53 bool ar9003_hw_rtt_force_restore(struct ath_hw *ah)
54 {
55 if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
56 AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
57 0, RTT_RESTORE_TIMEOUT))
58 return false;
59
60 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
61 AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE, 1);
62
63 if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
64 AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
65 0, RTT_RESTORE_TIMEOUT))
66 return false;
67
68 return true;
69 }
70
ar9003_hw_rtt_load_hist_entry(struct ath_hw * ah,u8 chain,u32 index,u32 data28)71 static void ar9003_hw_rtt_load_hist_entry(struct ath_hw *ah, u8 chain,
72 u32 index, u32 data28)
73 {
74 u32 val;
75
76 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
77 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);
78
79 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
80 SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
81 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
82 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
83 udelay(1);
84
85 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
86 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
87 udelay(1);
88
89 if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
90 AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
91 RTT_ACCESS_TIMEOUT))
92 return;
93
94 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
95 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
96 udelay(1);
97
98 ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
99 AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
100 RTT_ACCESS_TIMEOUT);
101 }
102
ar9003_hw_rtt_load_hist(struct ath_hw * ah,u8 chain,u32 * table)103 void ar9003_hw_rtt_load_hist(struct ath_hw *ah, u8 chain, u32 *table)
104 {
105 int i;
106
107 for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
108 ar9003_hw_rtt_load_hist_entry(ah, chain, i, table[i]);
109 }
110
ar9003_hw_rtt_fill_hist_entry(struct ath_hw * ah,u8 chain,u32 index)111 static int ar9003_hw_rtt_fill_hist_entry(struct ath_hw *ah, u8 chain, u32 index)
112 {
113 u32 val;
114
115 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
116 SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
117 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
118
119 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
120 udelay(1);
121
122 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
123 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
124 udelay(1);
125
126 if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
127 AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
128 RTT_ACCESS_TIMEOUT))
129 return RTT_BAD_VALUE;
130
131 val = REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain));
132
133 return val;
134 }
135
ar9003_hw_rtt_fill_hist(struct ath_hw * ah,u8 chain,u32 * table)136 void ar9003_hw_rtt_fill_hist(struct ath_hw *ah, u8 chain, u32 *table)
137 {
138 int i;
139
140 for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
141 table[i] = ar9003_hw_rtt_fill_hist_entry(ah, chain, i);
142 }
143
ar9003_hw_rtt_clear_hist(struct ath_hw * ah)144 void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
145 {
146 int i, j;
147
148 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
149 if (!(ah->rxchainmask & (1 << i)))
150 continue;
151 for (j = 0; j < MAX_RTT_TABLE_ENTRY; j++)
152 ar9003_hw_rtt_load_hist_entry(ah, i, j, 0);
153 }
154 }
155