1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "htc.h"
18
19 MODULE_AUTHOR("Atheros Communications");
20 MODULE_LICENSE("Dual BSD/GPL");
21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
22
23 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
24 module_param_named(debug, ath9k_debug, uint, 0);
25 MODULE_PARM_DESC(debug, "Debugging mask");
26
27 int htc_modparam_nohwcrypt;
28 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
31 #define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
33 .hw_value = (_idx), \
34 .max_power = 20, \
35 }
36
37 #define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
41 .max_power = 20, \
42 }
43
44 static struct ieee80211_channel ath9k_2ghz_channels[] = {
45 CHAN2G(2412, 0), /* Channel 1 */
46 CHAN2G(2417, 1), /* Channel 2 */
47 CHAN2G(2422, 2), /* Channel 3 */
48 CHAN2G(2427, 3), /* Channel 4 */
49 CHAN2G(2432, 4), /* Channel 5 */
50 CHAN2G(2437, 5), /* Channel 6 */
51 CHAN2G(2442, 6), /* Channel 7 */
52 CHAN2G(2447, 7), /* Channel 8 */
53 CHAN2G(2452, 8), /* Channel 9 */
54 CHAN2G(2457, 9), /* Channel 10 */
55 CHAN2G(2462, 10), /* Channel 11 */
56 CHAN2G(2467, 11), /* Channel 12 */
57 CHAN2G(2472, 12), /* Channel 13 */
58 CHAN2G(2484, 13), /* Channel 14 */
59 };
60
61 static struct ieee80211_channel ath9k_5ghz_channels[] = {
62 /* _We_ call this UNII 1 */
63 CHAN5G(5180, 14), /* Channel 36 */
64 CHAN5G(5200, 15), /* Channel 40 */
65 CHAN5G(5220, 16), /* Channel 44 */
66 CHAN5G(5240, 17), /* Channel 48 */
67 /* _We_ call this UNII 2 */
68 CHAN5G(5260, 18), /* Channel 52 */
69 CHAN5G(5280, 19), /* Channel 56 */
70 CHAN5G(5300, 20), /* Channel 60 */
71 CHAN5G(5320, 21), /* Channel 64 */
72 /* _We_ call this "Middle band" */
73 CHAN5G(5500, 22), /* Channel 100 */
74 CHAN5G(5520, 23), /* Channel 104 */
75 CHAN5G(5540, 24), /* Channel 108 */
76 CHAN5G(5560, 25), /* Channel 112 */
77 CHAN5G(5580, 26), /* Channel 116 */
78 CHAN5G(5600, 27), /* Channel 120 */
79 CHAN5G(5620, 28), /* Channel 124 */
80 CHAN5G(5640, 29), /* Channel 128 */
81 CHAN5G(5660, 30), /* Channel 132 */
82 CHAN5G(5680, 31), /* Channel 136 */
83 CHAN5G(5700, 32), /* Channel 140 */
84 /* _We_ call this UNII 3 */
85 CHAN5G(5745, 33), /* Channel 149 */
86 CHAN5G(5765, 34), /* Channel 153 */
87 CHAN5G(5785, 35), /* Channel 157 */
88 CHAN5G(5805, 36), /* Channel 161 */
89 CHAN5G(5825, 37), /* Channel 165 */
90 };
91
92 /* Atheros hardware rate code addition for short premble */
93 #define SHPCHECK(__hw_rate, __flags) \
94 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
95
96 #define RATE(_bitrate, _hw_rate, _flags) { \
97 .bitrate = (_bitrate), \
98 .flags = (_flags), \
99 .hw_value = (_hw_rate), \
100 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
101 }
102
103 static struct ieee80211_rate ath9k_legacy_rates[] = {
104 RATE(10, 0x1b, 0),
105 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
106 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
107 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
108 RATE(60, 0x0b, 0),
109 RATE(90, 0x0f, 0),
110 RATE(120, 0x0a, 0),
111 RATE(180, 0x0e, 0),
112 RATE(240, 0x09, 0),
113 RATE(360, 0x0d, 0),
114 RATE(480, 0x08, 0),
115 RATE(540, 0x0c, 0),
116 };
117
118 #ifdef CONFIG_MAC80211_LEDS
119 static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
120 { .throughput = 0 * 1024, .blink_time = 334 },
121 { .throughput = 1 * 1024, .blink_time = 260 },
122 { .throughput = 5 * 1024, .blink_time = 220 },
123 { .throughput = 10 * 1024, .blink_time = 190 },
124 { .throughput = 20 * 1024, .blink_time = 170 },
125 { .throughput = 50 * 1024, .blink_time = 150 },
126 { .throughput = 70 * 1024, .blink_time = 130 },
127 { .throughput = 100 * 1024, .blink_time = 110 },
128 { .throughput = 200 * 1024, .blink_time = 80 },
129 { .throughput = 300 * 1024, .blink_time = 50 },
130 };
131 #endif
132
ath9k_htc_wait_for_target(struct ath9k_htc_priv * priv)133 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
134 {
135 int time_left;
136
137 if (atomic_read(&priv->htc->tgt_ready) > 0) {
138 atomic_dec(&priv->htc->tgt_ready);
139 return 0;
140 }
141
142 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
143 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
144 if (!time_left) {
145 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
146 return -ETIMEDOUT;
147 }
148
149 atomic_dec(&priv->htc->tgt_ready);
150
151 return 0;
152 }
153
ath9k_deinit_priv(struct ath9k_htc_priv * priv)154 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
155 {
156 ath9k_hw_deinit(priv->ah);
157 kfree(priv->ah);
158 priv->ah = NULL;
159 }
160
ath9k_deinit_device(struct ath9k_htc_priv * priv)161 static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
162 {
163 struct ieee80211_hw *hw = priv->hw;
164
165 wiphy_rfkill_stop_polling(hw->wiphy);
166 ath9k_deinit_leds(priv);
167 ieee80211_unregister_hw(hw);
168 ath9k_rx_cleanup(priv);
169 ath9k_tx_cleanup(priv);
170 ath9k_deinit_priv(priv);
171 }
172
ath9k_htc_connect_svc(struct ath9k_htc_priv * priv,u16 service_id,void (* tx)(void *,struct sk_buff *,enum htc_endpoint_id,bool txok),enum htc_endpoint_id * ep_id)173 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
174 u16 service_id,
175 void (*tx) (void *,
176 struct sk_buff *,
177 enum htc_endpoint_id,
178 bool txok),
179 enum htc_endpoint_id *ep_id)
180 {
181 struct htc_service_connreq req;
182
183 memset(&req, 0, sizeof(struct htc_service_connreq));
184
185 req.service_id = service_id;
186 req.ep_callbacks.priv = priv;
187 req.ep_callbacks.rx = ath9k_htc_rxep;
188 req.ep_callbacks.tx = tx;
189
190 return htc_connect_service(priv->htc, &req, ep_id);
191 }
192
ath9k_init_htc_services(struct ath9k_htc_priv * priv,u16 devid,u32 drv_info)193 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
194 u32 drv_info)
195 {
196 int ret;
197
198 /* WMI CMD*/
199 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
200 if (ret)
201 goto err;
202
203 /* Beacon */
204 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
205 &priv->beacon_ep);
206 if (ret)
207 goto err;
208
209 /* CAB */
210 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
211 &priv->cab_ep);
212 if (ret)
213 goto err;
214
215
216 /* UAPSD */
217 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
218 &priv->uapsd_ep);
219 if (ret)
220 goto err;
221
222 /* MGMT */
223 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
224 &priv->mgmt_ep);
225 if (ret)
226 goto err;
227
228 /* DATA BE */
229 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
230 &priv->data_be_ep);
231 if (ret)
232 goto err;
233
234 /* DATA BK */
235 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
236 &priv->data_bk_ep);
237 if (ret)
238 goto err;
239
240 /* DATA VI */
241 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
242 &priv->data_vi_ep);
243 if (ret)
244 goto err;
245
246 /* DATA VO */
247 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
248 &priv->data_vo_ep);
249 if (ret)
250 goto err;
251
252 /*
253 * Setup required credits before initializing HTC.
254 * This is a bit hacky, but, since queuing is done in
255 * the HIF layer, shouldn't matter much.
256 */
257
258 if (IS_AR7010_DEVICE(drv_info))
259 priv->htc->credits = 45;
260 else
261 priv->htc->credits = 33;
262
263 ret = htc_init(priv->htc);
264 if (ret)
265 goto err;
266
267 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
268 priv->htc->credits);
269
270 return 0;
271
272 err:
273 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
274 return ret;
275 }
276
ath9k_reg_notifier(struct wiphy * wiphy,struct regulatory_request * request)277 static int ath9k_reg_notifier(struct wiphy *wiphy,
278 struct regulatory_request *request)
279 {
280 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
281 struct ath9k_htc_priv *priv = hw->priv;
282
283 return ath_reg_notifier_apply(wiphy, request,
284 ath9k_hw_regulatory(priv->ah));
285 }
286
ath9k_regread(void * hw_priv,u32 reg_offset)287 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
288 {
289 struct ath_hw *ah = (struct ath_hw *) hw_priv;
290 struct ath_common *common = ath9k_hw_common(ah);
291 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
292 __be32 val, reg = cpu_to_be32(reg_offset);
293 int r;
294
295 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
296 (u8 *) ®, sizeof(reg),
297 (u8 *) &val, sizeof(val),
298 100);
299 if (unlikely(r)) {
300 ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n",
301 reg_offset, r);
302 return -EIO;
303 }
304
305 return be32_to_cpu(val);
306 }
307
ath9k_multi_regread(void * hw_priv,u32 * addr,u32 * val,u16 count)308 static void ath9k_multi_regread(void *hw_priv, u32 *addr,
309 u32 *val, u16 count)
310 {
311 struct ath_hw *ah = (struct ath_hw *) hw_priv;
312 struct ath_common *common = ath9k_hw_common(ah);
313 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
314 __be32 tmpaddr[8];
315 __be32 tmpval[8];
316 int i, ret;
317
318 for (i = 0; i < count; i++) {
319 tmpaddr[i] = cpu_to_be32(addr[i]);
320 }
321
322 ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
323 (u8 *)tmpaddr , sizeof(u32) * count,
324 (u8 *)tmpval, sizeof(u32) * count,
325 100);
326 if (unlikely(ret)) {
327 ath_dbg(common, WMI,
328 "Multiple REGISTER READ FAILED (count: %d)\n", count);
329 }
330
331 for (i = 0; i < count; i++) {
332 val[i] = be32_to_cpu(tmpval[i]);
333 }
334 }
335
ath9k_regwrite_single(void * hw_priv,u32 val,u32 reg_offset)336 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
337 {
338 struct ath_hw *ah = (struct ath_hw *) hw_priv;
339 struct ath_common *common = ath9k_hw_common(ah);
340 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
341 const __be32 buf[2] = {
342 cpu_to_be32(reg_offset),
343 cpu_to_be32(val),
344 };
345 int r;
346
347 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
348 (u8 *) &buf, sizeof(buf),
349 (u8 *) &val, sizeof(val),
350 100);
351 if (unlikely(r)) {
352 ath_dbg(common, WMI, "REGISTER WRITE FAILED:(0x%04x, %d)\n",
353 reg_offset, r);
354 }
355 }
356
ath9k_regwrite_buffer(void * hw_priv,u32 val,u32 reg_offset)357 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
358 {
359 struct ath_hw *ah = (struct ath_hw *) hw_priv;
360 struct ath_common *common = ath9k_hw_common(ah);
361 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
362 u32 rsp_status;
363 int r;
364
365 mutex_lock(&priv->wmi->multi_write_mutex);
366
367 /* Store the register/value */
368 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
369 cpu_to_be32(reg_offset);
370 priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
371 cpu_to_be32(val);
372
373 priv->wmi->multi_write_idx++;
374
375 /* If the buffer is full, send it out. */
376 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
377 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
378 (u8 *) &priv->wmi->multi_write,
379 sizeof(struct register_write) * priv->wmi->multi_write_idx,
380 (u8 *) &rsp_status, sizeof(rsp_status),
381 100);
382 if (unlikely(r)) {
383 ath_dbg(common, WMI,
384 "REGISTER WRITE FAILED, multi len: %d\n",
385 priv->wmi->multi_write_idx);
386 }
387 priv->wmi->multi_write_idx = 0;
388 }
389
390 mutex_unlock(&priv->wmi->multi_write_mutex);
391 }
392
ath9k_regwrite(void * hw_priv,u32 val,u32 reg_offset)393 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
394 {
395 struct ath_hw *ah = (struct ath_hw *) hw_priv;
396 struct ath_common *common = ath9k_hw_common(ah);
397 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
398
399 if (atomic_read(&priv->wmi->mwrite_cnt))
400 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
401 else
402 ath9k_regwrite_single(hw_priv, val, reg_offset);
403 }
404
ath9k_enable_regwrite_buffer(void * hw_priv)405 static void ath9k_enable_regwrite_buffer(void *hw_priv)
406 {
407 struct ath_hw *ah = (struct ath_hw *) hw_priv;
408 struct ath_common *common = ath9k_hw_common(ah);
409 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
410
411 atomic_inc(&priv->wmi->mwrite_cnt);
412 }
413
ath9k_regwrite_flush(void * hw_priv)414 static void ath9k_regwrite_flush(void *hw_priv)
415 {
416 struct ath_hw *ah = (struct ath_hw *) hw_priv;
417 struct ath_common *common = ath9k_hw_common(ah);
418 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
419 u32 rsp_status;
420 int r;
421
422 atomic_dec(&priv->wmi->mwrite_cnt);
423
424 mutex_lock(&priv->wmi->multi_write_mutex);
425
426 if (priv->wmi->multi_write_idx) {
427 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
428 (u8 *) &priv->wmi->multi_write,
429 sizeof(struct register_write) * priv->wmi->multi_write_idx,
430 (u8 *) &rsp_status, sizeof(rsp_status),
431 100);
432 if (unlikely(r)) {
433 ath_dbg(common, WMI,
434 "REGISTER WRITE FAILED, multi len: %d\n",
435 priv->wmi->multi_write_idx);
436 }
437 priv->wmi->multi_write_idx = 0;
438 }
439
440 mutex_unlock(&priv->wmi->multi_write_mutex);
441 }
442
ath9k_reg_rmw(void * hw_priv,u32 reg_offset,u32 set,u32 clr)443 static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
444 {
445 u32 val;
446
447 val = ath9k_regread(hw_priv, reg_offset);
448 val &= ~clr;
449 val |= set;
450 ath9k_regwrite(hw_priv, val, reg_offset);
451 return val;
452 }
453
ath_usb_read_cachesize(struct ath_common * common,int * csz)454 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
455 {
456 *csz = L1_CACHE_BYTES >> 2;
457 }
458
ath_usb_eeprom_read(struct ath_common * common,u32 off,u16 * data)459 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
460 {
461 struct ath_hw *ah = (struct ath_hw *) common->ah;
462
463 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
464
465 if (!ath9k_hw_wait(ah,
466 AR_EEPROM_STATUS_DATA,
467 AR_EEPROM_STATUS_DATA_BUSY |
468 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
469 AH_WAIT_TIMEOUT))
470 return false;
471
472 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
473 AR_EEPROM_STATUS_DATA_VAL);
474
475 return true;
476 }
477
478 static const struct ath_bus_ops ath9k_usb_bus_ops = {
479 .ath_bus_type = ATH_USB,
480 .read_cachesize = ath_usb_read_cachesize,
481 .eeprom_read = ath_usb_eeprom_read,
482 };
483
setup_ht_cap(struct ath9k_htc_priv * priv,struct ieee80211_sta_ht_cap * ht_info)484 static void setup_ht_cap(struct ath9k_htc_priv *priv,
485 struct ieee80211_sta_ht_cap *ht_info)
486 {
487 struct ath_common *common = ath9k_hw_common(priv->ah);
488 u8 tx_streams, rx_streams;
489 int i;
490
491 ht_info->ht_supported = true;
492 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
493 IEEE80211_HT_CAP_SM_PS |
494 IEEE80211_HT_CAP_SGI_40 |
495 IEEE80211_HT_CAP_DSSSCCK40;
496
497 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
498 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
499
500 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
501
502 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
503 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
504
505 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
506
507 /* ath9k_htc supports only 1 or 2 stream devices */
508 tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2);
509 rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2);
510
511 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
512 tx_streams, rx_streams);
513
514 if (tx_streams != rx_streams) {
515 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
516 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
517 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
518 }
519
520 for (i = 0; i < rx_streams; i++)
521 ht_info->mcs.rx_mask[i] = 0xff;
522
523 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
524 }
525
ath9k_init_queues(struct ath9k_htc_priv * priv)526 static int ath9k_init_queues(struct ath9k_htc_priv *priv)
527 {
528 struct ath_common *common = ath9k_hw_common(priv->ah);
529 int i;
530
531 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
532 priv->hwq_map[i] = -1;
533
534 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
535 if (priv->beaconq == -1) {
536 ath_err(common, "Unable to setup BEACON xmit queue\n");
537 goto err;
538 }
539
540 priv->cabq = ath9k_htc_cabq_setup(priv);
541 if (priv->cabq == -1) {
542 ath_err(common, "Unable to setup CAB xmit queue\n");
543 goto err;
544 }
545
546 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
547 ath_err(common, "Unable to setup xmit queue for BE traffic\n");
548 goto err;
549 }
550
551 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
552 ath_err(common, "Unable to setup xmit queue for BK traffic\n");
553 goto err;
554 }
555 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
556 ath_err(common, "Unable to setup xmit queue for VI traffic\n");
557 goto err;
558 }
559 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
560 ath_err(common, "Unable to setup xmit queue for VO traffic\n");
561 goto err;
562 }
563
564 return 0;
565
566 err:
567 return -EINVAL;
568 }
569
ath9k_init_channels_rates(struct ath9k_htc_priv * priv)570 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
571 {
572 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
573 priv->sbands[IEEE80211_BAND_2GHZ].channels =
574 ath9k_2ghz_channels;
575 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
576 priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
577 ARRAY_SIZE(ath9k_2ghz_channels);
578 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
579 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
580 ARRAY_SIZE(ath9k_legacy_rates);
581 }
582
583 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
584 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
585 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
586 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
587 ARRAY_SIZE(ath9k_5ghz_channels);
588 priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
589 ath9k_legacy_rates + 4;
590 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
591 ARRAY_SIZE(ath9k_legacy_rates) - 4;
592 }
593 }
594
ath9k_init_misc(struct ath9k_htc_priv * priv)595 static void ath9k_init_misc(struct ath9k_htc_priv *priv)
596 {
597 struct ath_common *common = ath9k_hw_common(priv->ah);
598
599 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
600
601 priv->ah->opmode = NL80211_IFTYPE_STATION;
602 }
603
ath9k_init_priv(struct ath9k_htc_priv * priv,u16 devid,char * product,u32 drv_info)604 static int ath9k_init_priv(struct ath9k_htc_priv *priv,
605 u16 devid, char *product,
606 u32 drv_info)
607 {
608 struct ath_hw *ah = NULL;
609 struct ath_common *common;
610 int i, ret = 0, csz = 0;
611
612 priv->op_flags |= OP_INVALID;
613
614 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
615 if (!ah)
616 return -ENOMEM;
617
618 ah->hw_version.devid = devid;
619 ah->hw_version.usbdev = drv_info;
620 ah->ah_flags |= AH_USE_EEPROM;
621 ah->reg_ops.read = ath9k_regread;
622 ah->reg_ops.multi_read = ath9k_multi_regread;
623 ah->reg_ops.write = ath9k_regwrite;
624 ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
625 ah->reg_ops.write_flush = ath9k_regwrite_flush;
626 ah->reg_ops.rmw = ath9k_reg_rmw;
627 priv->ah = ah;
628
629 common = ath9k_hw_common(ah);
630 common->ops = &ah->reg_ops;
631 common->bus_ops = &ath9k_usb_bus_ops;
632 common->ah = ah;
633 common->hw = priv->hw;
634 common->priv = priv;
635 common->debug_mask = ath9k_debug;
636
637 spin_lock_init(&priv->beacon_lock);
638 spin_lock_init(&priv->tx.tx_lock);
639 mutex_init(&priv->mutex);
640 mutex_init(&priv->htc_pm_lock);
641 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
642 (unsigned long)priv);
643 tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
644 (unsigned long)priv);
645 INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
646 INIT_WORK(&priv->ps_work, ath9k_ps_work);
647 INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
648 setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
649 (unsigned long)priv);
650
651 /*
652 * Cache line size is used to size and align various
653 * structures used to communicate with the hardware.
654 */
655 ath_read_cachesize(common, &csz);
656 common->cachelsz = csz << 2; /* convert to bytes */
657
658 ret = ath9k_hw_init(ah);
659 if (ret) {
660 ath_err(common,
661 "Unable to initialize hardware; initialization status: %d\n",
662 ret);
663 goto err_hw;
664 }
665
666 ret = ath9k_init_queues(priv);
667 if (ret)
668 goto err_queues;
669
670 for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
671 priv->cur_beacon_conf.bslot[i] = NULL;
672
673 ath9k_cmn_init_crypto(ah);
674 ath9k_init_channels_rates(priv);
675 ath9k_init_misc(priv);
676 ath9k_htc_init_btcoex(priv, product);
677
678 return 0;
679
680 err_queues:
681 ath9k_hw_deinit(ah);
682 err_hw:
683
684 kfree(ah);
685 priv->ah = NULL;
686
687 return ret;
688 }
689
ath9k_set_hw_capab(struct ath9k_htc_priv * priv,struct ieee80211_hw * hw)690 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
691 struct ieee80211_hw *hw)
692 {
693 struct ath_common *common = ath9k_hw_common(priv->ah);
694
695 hw->flags = IEEE80211_HW_SIGNAL_DBM |
696 IEEE80211_HW_AMPDU_AGGREGATION |
697 IEEE80211_HW_SPECTRUM_MGMT |
698 IEEE80211_HW_HAS_RATE_CONTROL |
699 IEEE80211_HW_RX_INCLUDES_FCS |
700 IEEE80211_HW_SUPPORTS_PS |
701 IEEE80211_HW_PS_NULLFUNC_STACK |
702 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
703 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
704
705 hw->wiphy->interface_modes =
706 BIT(NL80211_IFTYPE_STATION) |
707 BIT(NL80211_IFTYPE_ADHOC) |
708 BIT(NL80211_IFTYPE_AP) |
709 BIT(NL80211_IFTYPE_P2P_GO) |
710 BIT(NL80211_IFTYPE_P2P_CLIENT);
711
712 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
713
714 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
715
716 hw->queues = 4;
717 hw->channel_change_time = 5000;
718 hw->max_listen_interval = 10;
719
720 hw->vif_data_size = sizeof(struct ath9k_htc_vif);
721 hw->sta_data_size = sizeof(struct ath9k_htc_sta);
722
723 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
724 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
725 sizeof(struct htc_frame_hdr) + 4;
726
727 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
728 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
729 &priv->sbands[IEEE80211_BAND_2GHZ];
730 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
731 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
732 &priv->sbands[IEEE80211_BAND_5GHZ];
733
734 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
735 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
736 setup_ht_cap(priv,
737 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
738 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
739 setup_ht_cap(priv,
740 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
741 }
742
743 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
744 }
745
ath9k_init_firmware_version(struct ath9k_htc_priv * priv)746 static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
747 {
748 struct ieee80211_hw *hw = priv->hw;
749 struct wmi_fw_version cmd_rsp;
750 int ret;
751
752 memset(&cmd_rsp, 0, sizeof(cmd_rsp));
753
754 WMI_CMD(WMI_GET_FW_VERSION);
755 if (ret)
756 return -EINVAL;
757
758 priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
759 priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
760
761 snprintf(hw->wiphy->fw_version, ETHTOOL_BUSINFO_LEN, "%d.%d",
762 priv->fw_version_major,
763 priv->fw_version_minor);
764
765 dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
766 priv->fw_version_major,
767 priv->fw_version_minor);
768
769 /*
770 * Check if the available FW matches the driver's
771 * required version.
772 */
773 if (priv->fw_version_major != MAJOR_VERSION_REQ ||
774 priv->fw_version_minor < MINOR_VERSION_REQ) {
775 dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
776 MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
777 return -EINVAL;
778 }
779
780 return 0;
781 }
782
ath9k_init_device(struct ath9k_htc_priv * priv,u16 devid,char * product,u32 drv_info)783 static int ath9k_init_device(struct ath9k_htc_priv *priv,
784 u16 devid, char *product, u32 drv_info)
785 {
786 struct ieee80211_hw *hw = priv->hw;
787 struct ath_common *common;
788 struct ath_hw *ah;
789 int error = 0;
790 struct ath_regulatory *reg;
791 char hw_name[64];
792
793 /* Bring up device */
794 error = ath9k_init_priv(priv, devid, product, drv_info);
795 if (error != 0)
796 goto err_init;
797
798 ah = priv->ah;
799 common = ath9k_hw_common(ah);
800 ath9k_set_hw_capab(priv, hw);
801
802 error = ath9k_init_firmware_version(priv);
803 if (error != 0)
804 goto err_fw;
805
806 /* Initialize regulatory */
807 error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
808 ath9k_reg_notifier);
809 if (error)
810 goto err_regd;
811
812 reg = &common->regulatory;
813
814 /* Setup TX */
815 error = ath9k_tx_init(priv);
816 if (error != 0)
817 goto err_tx;
818
819 /* Setup RX */
820 error = ath9k_rx_init(priv);
821 if (error != 0)
822 goto err_rx;
823
824 ath9k_hw_disable(priv->ah);
825 #ifdef CONFIG_MAC80211_LEDS
826 /* must be initialized before ieee80211_register_hw */
827 priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
828 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
829 ARRAY_SIZE(ath9k_htc_tpt_blink));
830 #endif
831
832 /* Register with mac80211 */
833 error = ieee80211_register_hw(hw);
834 if (error)
835 goto err_register;
836
837 /* Handle world regulatory */
838 if (!ath_is_world_regd(reg)) {
839 error = regulatory_hint(hw->wiphy, reg->alpha2);
840 if (error)
841 goto err_world;
842 }
843
844 error = ath9k_htc_init_debug(priv->ah);
845 if (error) {
846 ath_err(common, "Unable to create debugfs files\n");
847 goto err_world;
848 }
849
850 ath_dbg(common, CONFIG,
851 "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, BE:%d, BK:%d, VI:%d, VO:%d\n",
852 priv->wmi_cmd_ep,
853 priv->beacon_ep,
854 priv->cab_ep,
855 priv->uapsd_ep,
856 priv->mgmt_ep,
857 priv->data_be_ep,
858 priv->data_bk_ep,
859 priv->data_vi_ep,
860 priv->data_vo_ep);
861
862 ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
863 wiphy_info(hw->wiphy, "%s\n", hw_name);
864
865 ath9k_init_leds(priv);
866 ath9k_start_rfkill_poll(priv);
867
868 return 0;
869
870 err_world:
871 ieee80211_unregister_hw(hw);
872 err_register:
873 ath9k_rx_cleanup(priv);
874 err_rx:
875 ath9k_tx_cleanup(priv);
876 err_tx:
877 /* Nothing */
878 err_regd:
879 /* Nothing */
880 err_fw:
881 ath9k_deinit_priv(priv);
882 err_init:
883 return error;
884 }
885
ath9k_htc_probe_device(struct htc_target * htc_handle,struct device * dev,u16 devid,char * product,u32 drv_info)886 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
887 u16 devid, char *product, u32 drv_info)
888 {
889 struct ieee80211_hw *hw;
890 struct ath9k_htc_priv *priv;
891 int ret;
892
893 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
894 if (!hw)
895 return -ENOMEM;
896
897 priv = hw->priv;
898 priv->hw = hw;
899 priv->htc = htc_handle;
900 priv->dev = dev;
901 htc_handle->drv_priv = priv;
902 SET_IEEE80211_DEV(hw, priv->dev);
903
904 ret = ath9k_htc_wait_for_target(priv);
905 if (ret)
906 goto err_free;
907
908 priv->wmi = ath9k_init_wmi(priv);
909 if (!priv->wmi) {
910 ret = -EINVAL;
911 goto err_free;
912 }
913
914 ret = ath9k_init_htc_services(priv, devid, drv_info);
915 if (ret)
916 goto err_init;
917
918 ret = ath9k_init_device(priv, devid, product, drv_info);
919 if (ret)
920 goto err_init;
921
922 return 0;
923
924 err_init:
925 ath9k_deinit_wmi(priv);
926 err_free:
927 ieee80211_free_hw(hw);
928 return ret;
929 }
930
ath9k_htc_disconnect_device(struct htc_target * htc_handle,bool hotunplug)931 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
932 {
933 if (htc_handle->drv_priv) {
934
935 /* Check if the device has been yanked out. */
936 if (hotunplug)
937 htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
938
939 ath9k_deinit_device(htc_handle->drv_priv);
940 ath9k_deinit_wmi(htc_handle->drv_priv);
941 ieee80211_free_hw(htc_handle->drv_priv->hw);
942 }
943 }
944
945 #ifdef CONFIG_PM
946
ath9k_htc_suspend(struct htc_target * htc_handle)947 void ath9k_htc_suspend(struct htc_target *htc_handle)
948 {
949 ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
950 }
951
ath9k_htc_resume(struct htc_target * htc_handle)952 int ath9k_htc_resume(struct htc_target *htc_handle)
953 {
954 struct ath9k_htc_priv *priv = htc_handle->drv_priv;
955 int ret;
956
957 ret = ath9k_htc_wait_for_target(priv);
958 if (ret)
959 return ret;
960
961 ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
962 priv->ah->hw_version.usbdev);
963 return ret;
964 }
965 #endif
966
ath9k_htc_init(void)967 static int __init ath9k_htc_init(void)
968 {
969 if (ath9k_hif_usb_init() < 0) {
970 printk(KERN_ERR
971 "ath9k_htc: No USB devices found,"
972 " driver not installed.\n");
973 return -ENODEV;
974 }
975
976 return 0;
977 }
978 module_init(ath9k_htc_init);
979
ath9k_htc_exit(void)980 static void __exit ath9k_htc_exit(void)
981 {
982 ath9k_hif_usb_exit();
983 printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
984 }
985 module_exit(ath9k_htc_exit);
986