1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
21
22 #include "hw.h"
23 #include "hw-ops.h"
24 #include "rc.h"
25 #include "ar9003_mac.h"
26 #include "ar9003_mci.h"
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29
30 MODULE_AUTHOR("Atheros Communications");
31 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33 MODULE_LICENSE("Dual BSD/GPL");
34
ath9k_init(void)35 static int __init ath9k_init(void)
36 {
37 return 0;
38 }
39 module_init(ath9k_init);
40
ath9k_exit(void)41 static void __exit ath9k_exit(void)
42 {
43 return;
44 }
45 module_exit(ath9k_exit);
46
47 /* Private hardware callbacks */
48
ath9k_hw_init_cal_settings(struct ath_hw * ah)49 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50 {
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 }
53
ath9k_hw_init_mode_regs(struct ath_hw * ah)54 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55 {
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 }
58
ath9k_hw_compute_pll_control(struct ath_hw * ah,struct ath9k_channel * chan)59 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
60 struct ath9k_channel *chan)
61 {
62 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63 }
64
ath9k_hw_init_mode_gain_regs(struct ath_hw * ah)65 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
66 {
67 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 return;
69
70 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71 }
72
ath9k_hw_ani_cache_ini_regs(struct ath_hw * ah)73 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
74 {
75 /* You will not have this callback if using the old ANI */
76 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 return;
78
79 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80 }
81
82 /********************/
83 /* Helper Functions */
84 /********************/
85
ath9k_hw_set_clockrate(struct ath_hw * ah)86 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
87 {
88 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
89 struct ath_common *common = ath9k_hw_common(ah);
90 unsigned int clockrate;
91
92 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
93 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
94 clockrate = 117;
95 else if (!ah->curchan) /* should really check for CCK instead */
96 clockrate = ATH9K_CLOCK_RATE_CCK;
97 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
98 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
99 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
100 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
101 else
102 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
103
104 if (conf_is_ht40(conf))
105 clockrate *= 2;
106
107 if (ah->curchan) {
108 if (IS_CHAN_HALF_RATE(ah->curchan))
109 clockrate /= 2;
110 if (IS_CHAN_QUARTER_RATE(ah->curchan))
111 clockrate /= 4;
112 }
113
114 common->clockrate = clockrate;
115 }
116
ath9k_hw_mac_to_clks(struct ath_hw * ah,u32 usecs)117 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
118 {
119 struct ath_common *common = ath9k_hw_common(ah);
120
121 return usecs * common->clockrate;
122 }
123
ath9k_hw_wait(struct ath_hw * ah,u32 reg,u32 mask,u32 val,u32 timeout)124 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
125 {
126 int i;
127
128 BUG_ON(timeout < AH_TIME_QUANTUM);
129
130 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
131 if ((REG_READ(ah, reg) & mask) == val)
132 return true;
133
134 udelay(AH_TIME_QUANTUM);
135 }
136
137 ath_dbg(ath9k_hw_common(ah), ANY,
138 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
139 timeout, reg, REG_READ(ah, reg), mask, val);
140
141 return false;
142 }
143 EXPORT_SYMBOL(ath9k_hw_wait);
144
ath9k_hw_write_array(struct ath_hw * ah,struct ar5416IniArray * array,int column,unsigned int * writecnt)145 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
146 int column, unsigned int *writecnt)
147 {
148 int r;
149
150 ENABLE_REGWRITE_BUFFER(ah);
151 for (r = 0; r < array->ia_rows; r++) {
152 REG_WRITE(ah, INI_RA(array, r, 0),
153 INI_RA(array, r, column));
154 DO_DELAY(*writecnt);
155 }
156 REGWRITE_BUFFER_FLUSH(ah);
157 }
158
ath9k_hw_reverse_bits(u32 val,u32 n)159 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
160 {
161 u32 retval;
162 int i;
163
164 for (i = 0, retval = 0; i < n; i++) {
165 retval = (retval << 1) | (val & 1);
166 val >>= 1;
167 }
168 return retval;
169 }
170
ath9k_hw_computetxtime(struct ath_hw * ah,u8 phy,int kbps,u32 frameLen,u16 rateix,bool shortPreamble)171 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
172 u8 phy, int kbps,
173 u32 frameLen, u16 rateix,
174 bool shortPreamble)
175 {
176 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
177
178 if (kbps == 0)
179 return 0;
180
181 switch (phy) {
182 case WLAN_RC_PHY_CCK:
183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
184 if (shortPreamble)
185 phyTime >>= 1;
186 numBits = frameLen << 3;
187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
188 break;
189 case WLAN_RC_PHY_OFDM:
190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
197 } else if (ah->curchan &&
198 IS_CHAN_HALF_RATE(ah->curchan)) {
199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME_HALF +
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
205 } else {
206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
207 numBits = OFDM_PLCP_BITS + (frameLen << 3);
208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
210 + (numSymbols * OFDM_SYMBOL_TIME);
211 }
212 break;
213 default:
214 ath_err(ath9k_hw_common(ah),
215 "Unknown phy %u (rate ix %u)\n", phy, rateix);
216 txTime = 0;
217 break;
218 }
219
220 return txTime;
221 }
222 EXPORT_SYMBOL(ath9k_hw_computetxtime);
223
ath9k_hw_get_channel_centers(struct ath_hw * ah,struct ath9k_channel * chan,struct chan_centers * centers)224 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
225 struct ath9k_channel *chan,
226 struct chan_centers *centers)
227 {
228 int8_t extoff;
229
230 if (!IS_CHAN_HT40(chan)) {
231 centers->ctl_center = centers->ext_center =
232 centers->synth_center = chan->channel;
233 return;
234 }
235
236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
237 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
238 centers->synth_center =
239 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
240 extoff = 1;
241 } else {
242 centers->synth_center =
243 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
244 extoff = -1;
245 }
246
247 centers->ctl_center =
248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
249 /* 25 MHz spacing is supported by hw but not on upper layers */
250 centers->ext_center =
251 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
252 }
253
254 /******************/
255 /* Chip Revisions */
256 /******************/
257
ath9k_hw_read_revisions(struct ath_hw * ah)258 static void ath9k_hw_read_revisions(struct ath_hw *ah)
259 {
260 u32 val;
261
262 switch (ah->hw_version.devid) {
263 case AR5416_AR9100_DEVID:
264 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
265 break;
266 case AR9300_DEVID_AR9330:
267 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
268 if (ah->get_mac_revision) {
269 ah->hw_version.macRev = ah->get_mac_revision();
270 } else {
271 val = REG_READ(ah, AR_SREV);
272 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
273 }
274 return;
275 case AR9300_DEVID_AR9340:
276 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
277 val = REG_READ(ah, AR_SREV);
278 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
279 return;
280 }
281
282 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
283
284 if (val == 0xFF) {
285 val = REG_READ(ah, AR_SREV);
286 ah->hw_version.macVersion =
287 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
288 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
289
290 if (AR_SREV_9462(ah))
291 ah->is_pciexpress = true;
292 else
293 ah->is_pciexpress = (val &
294 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
295 } else {
296 if (!AR_SREV_9100(ah))
297 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
298
299 ah->hw_version.macRev = val & AR_SREV_REVISION;
300
301 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
302 ah->is_pciexpress = true;
303 }
304 }
305
306 /************************************/
307 /* HW Attach, Detach, Init Routines */
308 /************************************/
309
ath9k_hw_disablepcie(struct ath_hw * ah)310 static void ath9k_hw_disablepcie(struct ath_hw *ah)
311 {
312 if (!AR_SREV_5416(ah))
313 return;
314
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
324
325 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
326 }
327
ath9k_hw_aspm_init(struct ath_hw * ah)328 static void ath9k_hw_aspm_init(struct ath_hw *ah)
329 {
330 struct ath_common *common = ath9k_hw_common(ah);
331
332 if (common->bus_ops->aspm_init)
333 common->bus_ops->aspm_init(common);
334 }
335
336 /* This should work for all families including legacy */
ath9k_hw_chip_test(struct ath_hw * ah)337 static bool ath9k_hw_chip_test(struct ath_hw *ah)
338 {
339 struct ath_common *common = ath9k_hw_common(ah);
340 u32 regAddr[2] = { AR_STA_ID0 };
341 u32 regHold[2];
342 static const u32 patternData[4] = {
343 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
344 };
345 int i, j, loop_max;
346
347 if (!AR_SREV_9300_20_OR_LATER(ah)) {
348 loop_max = 2;
349 regAddr[1] = AR_PHY_BASE + (8 << 2);
350 } else
351 loop_max = 1;
352
353 for (i = 0; i < loop_max; i++) {
354 u32 addr = regAddr[i];
355 u32 wrData, rdData;
356
357 regHold[i] = REG_READ(ah, addr);
358 for (j = 0; j < 0x100; j++) {
359 wrData = (j << 16) | j;
360 REG_WRITE(ah, addr, wrData);
361 rdData = REG_READ(ah, addr);
362 if (rdData != wrData) {
363 ath_err(common,
364 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
365 addr, wrData, rdData);
366 return false;
367 }
368 }
369 for (j = 0; j < 4; j++) {
370 wrData = patternData[j];
371 REG_WRITE(ah, addr, wrData);
372 rdData = REG_READ(ah, addr);
373 if (wrData != rdData) {
374 ath_err(common,
375 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
376 addr, wrData, rdData);
377 return false;
378 }
379 }
380 REG_WRITE(ah, regAddr[i], regHold[i]);
381 }
382 udelay(100);
383
384 return true;
385 }
386
ath9k_hw_init_config(struct ath_hw * ah)387 static void ath9k_hw_init_config(struct ath_hw *ah)
388 {
389 int i;
390
391 ah->config.dma_beacon_response_time = 2;
392 ah->config.sw_beacon_response_time = 10;
393 ah->config.additional_swba_backoff = 0;
394 ah->config.ack_6mb = 0x0;
395 ah->config.cwm_ignore_extcca = 0;
396 ah->config.pcie_clock_req = 0;
397 ah->config.pcie_waen = 0;
398 ah->config.analog_shiftreg = 1;
399 ah->config.enable_ani = true;
400
401 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
402 ah->config.spurchans[i][0] = AR_NO_SPUR;
403 ah->config.spurchans[i][1] = AR_NO_SPUR;
404 }
405
406 /* PAPRD needs some more work to be enabled */
407 ah->config.paprd_disable = 1;
408
409 ah->config.rx_intr_mitigation = true;
410 ah->config.pcieSerDesWrite = true;
411
412 /*
413 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
414 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
415 * This means we use it for all AR5416 devices, and the few
416 * minor PCI AR9280 devices out there.
417 *
418 * Serialization is required because these devices do not handle
419 * well the case of two concurrent reads/writes due to the latency
420 * involved. During one read/write another read/write can be issued
421 * on another CPU while the previous read/write may still be working
422 * on our hardware, if we hit this case the hardware poops in a loop.
423 * We prevent this by serializing reads and writes.
424 *
425 * This issue is not present on PCI-Express devices or pre-AR5416
426 * devices (legacy, 802.11abg).
427 */
428 if (num_possible_cpus() > 1)
429 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
430 }
431
ath9k_hw_init_defaults(struct ath_hw * ah)432 static void ath9k_hw_init_defaults(struct ath_hw *ah)
433 {
434 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
435
436 regulatory->country_code = CTRY_DEFAULT;
437 regulatory->power_limit = MAX_RATE_POWER;
438
439 ah->hw_version.magic = AR5416_MAGIC;
440 ah->hw_version.subvendorid = 0;
441
442 ah->atim_window = 0;
443 ah->sta_id1_defaults =
444 AR_STA_ID1_CRPT_MIC_ENABLE |
445 AR_STA_ID1_MCAST_KSRCH;
446 if (AR_SREV_9100(ah))
447 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
448 ah->enable_32kHz_clock = DONT_USE_32KHZ;
449 ah->slottime = ATH9K_SLOT_TIME_9;
450 ah->globaltxtimeout = (u32) -1;
451 ah->power_mode = ATH9K_PM_UNDEFINED;
452 ah->htc_reset_init = true;
453 }
454
ath9k_hw_init_macaddr(struct ath_hw * ah)455 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
456 {
457 struct ath_common *common = ath9k_hw_common(ah);
458 u32 sum;
459 int i;
460 u16 eeval;
461 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
462
463 sum = 0;
464 for (i = 0; i < 3; i++) {
465 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
466 sum += eeval;
467 common->macaddr[2 * i] = eeval >> 8;
468 common->macaddr[2 * i + 1] = eeval & 0xff;
469 }
470 if (sum == 0 || sum == 0xffff * 3)
471 return -EADDRNOTAVAIL;
472
473 return 0;
474 }
475
ath9k_hw_post_init(struct ath_hw * ah)476 static int ath9k_hw_post_init(struct ath_hw *ah)
477 {
478 struct ath_common *common = ath9k_hw_common(ah);
479 int ecode;
480
481 if (common->bus_ops->ath_bus_type != ATH_USB) {
482 if (!ath9k_hw_chip_test(ah))
483 return -ENODEV;
484 }
485
486 if (!AR_SREV_9300_20_OR_LATER(ah)) {
487 ecode = ar9002_hw_rf_claim(ah);
488 if (ecode != 0)
489 return ecode;
490 }
491
492 ecode = ath9k_hw_eeprom_init(ah);
493 if (ecode != 0)
494 return ecode;
495
496 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
497 ah->eep_ops->get_eeprom_ver(ah),
498 ah->eep_ops->get_eeprom_rev(ah));
499
500 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
501 if (ecode) {
502 ath_err(ath9k_hw_common(ah),
503 "Failed allocating banks for external radio\n");
504 ath9k_hw_rf_free_ext_banks(ah);
505 return ecode;
506 }
507
508 if (ah->config.enable_ani) {
509 ath9k_hw_ani_setup(ah);
510 ath9k_hw_ani_init(ah);
511 }
512
513 return 0;
514 }
515
ath9k_hw_attach_ops(struct ath_hw * ah)516 static void ath9k_hw_attach_ops(struct ath_hw *ah)
517 {
518 if (AR_SREV_9300_20_OR_LATER(ah))
519 ar9003_hw_attach_ops(ah);
520 else
521 ar9002_hw_attach_ops(ah);
522 }
523
524 /* Called for all hardware families */
__ath9k_hw_init(struct ath_hw * ah)525 static int __ath9k_hw_init(struct ath_hw *ah)
526 {
527 struct ath_common *common = ath9k_hw_common(ah);
528 int r = 0;
529
530 ath9k_hw_read_revisions(ah);
531
532 /*
533 * Read back AR_WA into a permanent copy and set bits 14 and 17.
534 * We need to do this to avoid RMW of this register. We cannot
535 * read the reg when chip is asleep.
536 */
537 ah->WARegVal = REG_READ(ah, AR_WA);
538 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
539 AR_WA_ASPM_TIMER_BASED_DISABLE);
540
541 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
542 ath_err(common, "Couldn't reset chip\n");
543 return -EIO;
544 }
545
546 if (AR_SREV_9462(ah))
547 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
548
549 ath9k_hw_init_defaults(ah);
550 ath9k_hw_init_config(ah);
551
552 ath9k_hw_attach_ops(ah);
553
554 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
555 ath_err(common, "Couldn't wakeup chip\n");
556 return -EIO;
557 }
558
559 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
560 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
561 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
562 !ah->is_pciexpress)) {
563 ah->config.serialize_regmode =
564 SER_REG_MODE_ON;
565 } else {
566 ah->config.serialize_regmode =
567 SER_REG_MODE_OFF;
568 }
569 }
570
571 ath_dbg(common, RESET, "serialize_regmode is %d\n",
572 ah->config.serialize_regmode);
573
574 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
575 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
576 else
577 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
578
579 switch (ah->hw_version.macVersion) {
580 case AR_SREV_VERSION_5416_PCI:
581 case AR_SREV_VERSION_5416_PCIE:
582 case AR_SREV_VERSION_9160:
583 case AR_SREV_VERSION_9100:
584 case AR_SREV_VERSION_9280:
585 case AR_SREV_VERSION_9285:
586 case AR_SREV_VERSION_9287:
587 case AR_SREV_VERSION_9271:
588 case AR_SREV_VERSION_9300:
589 case AR_SREV_VERSION_9330:
590 case AR_SREV_VERSION_9485:
591 case AR_SREV_VERSION_9340:
592 case AR_SREV_VERSION_9462:
593 break;
594 default:
595 ath_err(common,
596 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
597 ah->hw_version.macVersion, ah->hw_version.macRev);
598 return -EOPNOTSUPP;
599 }
600
601 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
602 AR_SREV_9330(ah))
603 ah->is_pciexpress = false;
604
605 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
606 ath9k_hw_init_cal_settings(ah);
607
608 ah->ani_function = ATH9K_ANI_ALL;
609 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
610 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
611 if (!AR_SREV_9300_20_OR_LATER(ah))
612 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
613
614 /* disable ANI for 9340 */
615 if (AR_SREV_9340(ah))
616 ah->config.enable_ani = false;
617
618 ath9k_hw_init_mode_regs(ah);
619
620 if (!ah->is_pciexpress)
621 ath9k_hw_disablepcie(ah);
622
623 r = ath9k_hw_post_init(ah);
624 if (r)
625 return r;
626
627 ath9k_hw_init_mode_gain_regs(ah);
628 r = ath9k_hw_fill_cap_info(ah);
629 if (r)
630 return r;
631
632 if (ah->is_pciexpress)
633 ath9k_hw_aspm_init(ah);
634
635 r = ath9k_hw_init_macaddr(ah);
636 if (r) {
637 ath_err(common, "Failed to initialize MAC address\n");
638 return r;
639 }
640
641 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
642 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
643 else
644 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
645
646 if (AR_SREV_9330(ah))
647 ah->bb_watchdog_timeout_ms = 85;
648 else
649 ah->bb_watchdog_timeout_ms = 25;
650
651 common->state = ATH_HW_INITIALIZED;
652
653 return 0;
654 }
655
ath9k_hw_init(struct ath_hw * ah)656 int ath9k_hw_init(struct ath_hw *ah)
657 {
658 int ret;
659 struct ath_common *common = ath9k_hw_common(ah);
660
661 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
662 switch (ah->hw_version.devid) {
663 case AR5416_DEVID_PCI:
664 case AR5416_DEVID_PCIE:
665 case AR5416_AR9100_DEVID:
666 case AR9160_DEVID_PCI:
667 case AR9280_DEVID_PCI:
668 case AR9280_DEVID_PCIE:
669 case AR9285_DEVID_PCIE:
670 case AR9287_DEVID_PCI:
671 case AR9287_DEVID_PCIE:
672 case AR2427_DEVID_PCIE:
673 case AR9300_DEVID_PCIE:
674 case AR9300_DEVID_AR9485_PCIE:
675 case AR9300_DEVID_AR9330:
676 case AR9300_DEVID_AR9340:
677 case AR9300_DEVID_AR9580:
678 case AR9300_DEVID_AR9462:
679 case AR9485_DEVID_AR1111:
680 break;
681 default:
682 if (common->bus_ops->ath_bus_type == ATH_USB)
683 break;
684 ath_err(common, "Hardware device ID 0x%04x not supported\n",
685 ah->hw_version.devid);
686 return -EOPNOTSUPP;
687 }
688
689 ret = __ath9k_hw_init(ah);
690 if (ret) {
691 ath_err(common,
692 "Unable to initialize hardware; initialization status: %d\n",
693 ret);
694 return ret;
695 }
696
697 return 0;
698 }
699 EXPORT_SYMBOL(ath9k_hw_init);
700
ath9k_hw_init_qos(struct ath_hw * ah)701 static void ath9k_hw_init_qos(struct ath_hw *ah)
702 {
703 ENABLE_REGWRITE_BUFFER(ah);
704
705 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
706 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
707
708 REG_WRITE(ah, AR_QOS_NO_ACK,
709 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
710 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
711 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
712
713 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
714 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
715 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
716 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
718
719 REGWRITE_BUFFER_FLUSH(ah);
720 }
721
ar9003_get_pll_sqsum_dvc(struct ath_hw * ah)722 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
723 {
724 struct ath_common *common = ath9k_hw_common(ah);
725 int i = 0;
726
727 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
728 udelay(100);
729 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
730
731 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
732
733 udelay(100);
734
735 if (WARN_ON_ONCE(i >= 100)) {
736 ath_err(common, "PLL4 meaurement not done\n");
737 break;
738 }
739
740 i++;
741 }
742
743 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
744 }
745 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
746
ath9k_hw_init_pll(struct ath_hw * ah,struct ath9k_channel * chan)747 static void ath9k_hw_init_pll(struct ath_hw *ah,
748 struct ath9k_channel *chan)
749 {
750 u32 pll;
751
752 if (AR_SREV_9485(ah)) {
753
754 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
755 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
756 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
758 AR_CH0_DPLL2_KD, 0x40);
759 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
760 AR_CH0_DPLL2_KI, 0x4);
761
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
763 AR_CH0_BB_DPLL1_REFDIV, 0x5);
764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
765 AR_CH0_BB_DPLL1_NINI, 0x58);
766 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
767 AR_CH0_BB_DPLL1_NFRAC, 0x0);
768
769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
770 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
771 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
772 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
773 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
774 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
775
776 /* program BB PLL phase_shift to 0x6 */
777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
778 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
779
780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
781 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
782 udelay(1000);
783 } else if (AR_SREV_9330(ah)) {
784 u32 ddr_dpll2, pll_control2, kd;
785
786 if (ah->is_clk_25mhz) {
787 ddr_dpll2 = 0x18e82f01;
788 pll_control2 = 0xe04a3d;
789 kd = 0x1d;
790 } else {
791 ddr_dpll2 = 0x19e82f01;
792 pll_control2 = 0x886666;
793 kd = 0x3d;
794 }
795
796 /* program DDR PLL ki and kd value */
797 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
798
799 /* program DDR PLL phase_shift */
800 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
801 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
802
803 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
804 udelay(1000);
805
806 /* program refdiv, nint, frac to RTC register */
807 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
808
809 /* program BB PLL kd and ki value */
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
812
813 /* program BB PLL phase_shift */
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
815 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
816 } else if (AR_SREV_9340(ah)) {
817 u32 regval, pll2_divint, pll2_divfrac, refdiv;
818
819 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
820 udelay(1000);
821
822 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
823 udelay(100);
824
825 if (ah->is_clk_25mhz) {
826 pll2_divint = 0x54;
827 pll2_divfrac = 0x1eb85;
828 refdiv = 3;
829 } else {
830 pll2_divint = 88;
831 pll2_divfrac = 0;
832 refdiv = 5;
833 }
834
835 regval = REG_READ(ah, AR_PHY_PLL_MODE);
836 regval |= (0x1 << 16);
837 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
838 udelay(100);
839
840 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
841 (pll2_divint << 18) | pll2_divfrac);
842 udelay(100);
843
844 regval = REG_READ(ah, AR_PHY_PLL_MODE);
845 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
846 (0x4 << 26) | (0x18 << 19);
847 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
848 REG_WRITE(ah, AR_PHY_PLL_MODE,
849 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
850 udelay(1000);
851 }
852
853 pll = ath9k_hw_compute_pll_control(ah, chan);
854
855 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
856
857 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
858 udelay(1000);
859
860 /* Switch the core clock for ar9271 to 117Mhz */
861 if (AR_SREV_9271(ah)) {
862 udelay(500);
863 REG_WRITE(ah, 0x50040, 0x304);
864 }
865
866 udelay(RTC_PLL_SETTLE_DELAY);
867
868 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
869
870 if (AR_SREV_9340(ah)) {
871 if (ah->is_clk_25mhz) {
872 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
873 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
874 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
875 } else {
876 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
877 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
878 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
879 }
880 udelay(100);
881 }
882 }
883
ath9k_hw_init_interrupt_masks(struct ath_hw * ah,enum nl80211_iftype opmode)884 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
885 enum nl80211_iftype opmode)
886 {
887 u32 sync_default = AR_INTR_SYNC_DEFAULT;
888 u32 imr_reg = AR_IMR_TXERR |
889 AR_IMR_TXURN |
890 AR_IMR_RXERR |
891 AR_IMR_RXORN |
892 AR_IMR_BCNMISC;
893
894 if (AR_SREV_9340(ah))
895 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
896
897 if (AR_SREV_9300_20_OR_LATER(ah)) {
898 imr_reg |= AR_IMR_RXOK_HP;
899 if (ah->config.rx_intr_mitigation)
900 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
901 else
902 imr_reg |= AR_IMR_RXOK_LP;
903
904 } else {
905 if (ah->config.rx_intr_mitigation)
906 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
907 else
908 imr_reg |= AR_IMR_RXOK;
909 }
910
911 if (ah->config.tx_intr_mitigation)
912 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
913 else
914 imr_reg |= AR_IMR_TXOK;
915
916 if (opmode == NL80211_IFTYPE_AP)
917 imr_reg |= AR_IMR_MIB;
918
919 ENABLE_REGWRITE_BUFFER(ah);
920
921 REG_WRITE(ah, AR_IMR, imr_reg);
922 ah->imrs2_reg |= AR_IMR_S2_GTT;
923 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
924
925 if (!AR_SREV_9100(ah)) {
926 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
927 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
928 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
929 }
930
931 REGWRITE_BUFFER_FLUSH(ah);
932
933 if (AR_SREV_9300_20_OR_LATER(ah)) {
934 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
935 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
936 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
937 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
938 }
939 }
940
ath9k_hw_set_sifs_time(struct ath_hw * ah,u32 us)941 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
942 {
943 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
944 val = min(val, (u32) 0xFFFF);
945 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
946 }
947
ath9k_hw_setslottime(struct ath_hw * ah,u32 us)948 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
949 {
950 u32 val = ath9k_hw_mac_to_clks(ah, us);
951 val = min(val, (u32) 0xFFFF);
952 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
953 }
954
ath9k_hw_set_ack_timeout(struct ath_hw * ah,u32 us)955 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
956 {
957 u32 val = ath9k_hw_mac_to_clks(ah, us);
958 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
959 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
960 }
961
ath9k_hw_set_cts_timeout(struct ath_hw * ah,u32 us)962 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
963 {
964 u32 val = ath9k_hw_mac_to_clks(ah, us);
965 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
966 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
967 }
968
ath9k_hw_set_global_txtimeout(struct ath_hw * ah,u32 tu)969 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
970 {
971 if (tu > 0xFFFF) {
972 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
973 tu);
974 ah->globaltxtimeout = (u32) -1;
975 return false;
976 } else {
977 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
978 ah->globaltxtimeout = tu;
979 return true;
980 }
981 }
982
ath9k_hw_init_global_settings(struct ath_hw * ah)983 void ath9k_hw_init_global_settings(struct ath_hw *ah)
984 {
985 struct ath_common *common = ath9k_hw_common(ah);
986 struct ieee80211_conf *conf = &common->hw->conf;
987 const struct ath9k_channel *chan = ah->curchan;
988 int acktimeout, ctstimeout;
989 int slottime;
990 int sifstime;
991 int rx_lat = 0, tx_lat = 0, eifs = 0;
992 u32 reg;
993
994 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
995 ah->misc_mode);
996
997 if (!chan)
998 return;
999
1000 if (ah->misc_mode != 0)
1001 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1002
1003 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1004 rx_lat = 41;
1005 else
1006 rx_lat = 37;
1007 tx_lat = 54;
1008
1009 if (IS_CHAN_HALF_RATE(chan)) {
1010 eifs = 175;
1011 rx_lat *= 2;
1012 tx_lat *= 2;
1013 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1014 tx_lat += 11;
1015
1016 slottime = 13;
1017 sifstime = 32;
1018 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1019 eifs = 340;
1020 rx_lat = (rx_lat * 4) - 1;
1021 tx_lat *= 4;
1022 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1023 tx_lat += 22;
1024
1025 slottime = 21;
1026 sifstime = 64;
1027 } else {
1028 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1029 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1030 reg = AR_USEC_ASYNC_FIFO;
1031 } else {
1032 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1033 common->clockrate;
1034 reg = REG_READ(ah, AR_USEC);
1035 }
1036 rx_lat = MS(reg, AR_USEC_RX_LAT);
1037 tx_lat = MS(reg, AR_USEC_TX_LAT);
1038
1039 slottime = ah->slottime;
1040 if (IS_CHAN_5GHZ(chan))
1041 sifstime = 16;
1042 else
1043 sifstime = 10;
1044 }
1045
1046 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1047 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1048 ctstimeout = acktimeout;
1049
1050 /*
1051 * Workaround for early ACK timeouts, add an offset to match the
1052 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1053 * This was initially only meant to work around an issue with delayed
1054 * BA frames in some implementations, but it has been found to fix ACK
1055 * timeout issues in other cases as well.
1056 */
1057 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) {
1058 acktimeout += 64 - sifstime - ah->slottime;
1059 ctstimeout += 48 - sifstime - ah->slottime;
1060 }
1061
1062
1063 ath9k_hw_set_sifs_time(ah, sifstime);
1064 ath9k_hw_setslottime(ah, slottime);
1065 ath9k_hw_set_ack_timeout(ah, acktimeout);
1066 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1067 if (ah->globaltxtimeout != (u32) -1)
1068 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1069
1070 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1071 REG_RMW(ah, AR_USEC,
1072 (common->clockrate - 1) |
1073 SM(rx_lat, AR_USEC_RX_LAT) |
1074 SM(tx_lat, AR_USEC_TX_LAT),
1075 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1076
1077 }
1078 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1079
ath9k_hw_deinit(struct ath_hw * ah)1080 void ath9k_hw_deinit(struct ath_hw *ah)
1081 {
1082 struct ath_common *common = ath9k_hw_common(ah);
1083
1084 if (common->state < ATH_HW_INITIALIZED)
1085 goto free_hw;
1086
1087 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1088
1089 free_hw:
1090 ath9k_hw_rf_free_ext_banks(ah);
1091 }
1092 EXPORT_SYMBOL(ath9k_hw_deinit);
1093
1094 /*******/
1095 /* INI */
1096 /*******/
1097
ath9k_regd_get_ctl(struct ath_regulatory * reg,struct ath9k_channel * chan)1098 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1099 {
1100 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1101
1102 if (IS_CHAN_B(chan))
1103 ctl |= CTL_11B;
1104 else if (IS_CHAN_G(chan))
1105 ctl |= CTL_11G;
1106 else
1107 ctl |= CTL_11A;
1108
1109 return ctl;
1110 }
1111
1112 /****************************************/
1113 /* Reset and Channel Switching Routines */
1114 /****************************************/
1115
ath9k_hw_set_dma(struct ath_hw * ah)1116 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1117 {
1118 struct ath_common *common = ath9k_hw_common(ah);
1119
1120 ENABLE_REGWRITE_BUFFER(ah);
1121
1122 /*
1123 * set AHB_MODE not to do cacheline prefetches
1124 */
1125 if (!AR_SREV_9300_20_OR_LATER(ah))
1126 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1127
1128 /*
1129 * let mac dma reads be in 128 byte chunks
1130 */
1131 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1132
1133 REGWRITE_BUFFER_FLUSH(ah);
1134
1135 /*
1136 * Restore TX Trigger Level to its pre-reset value.
1137 * The initial value depends on whether aggregation is enabled, and is
1138 * adjusted whenever underruns are detected.
1139 */
1140 if (!AR_SREV_9300_20_OR_LATER(ah))
1141 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1142
1143 ENABLE_REGWRITE_BUFFER(ah);
1144
1145 /*
1146 * let mac dma writes be in 128 byte chunks
1147 */
1148 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1149
1150 /*
1151 * Setup receive FIFO threshold to hold off TX activities
1152 */
1153 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1154
1155 if (AR_SREV_9300_20_OR_LATER(ah)) {
1156 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1157 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1158
1159 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1160 ah->caps.rx_status_len);
1161 }
1162
1163 /*
1164 * reduce the number of usable entries in PCU TXBUF to avoid
1165 * wrap around issues.
1166 */
1167 if (AR_SREV_9285(ah)) {
1168 /* For AR9285 the number of Fifos are reduced to half.
1169 * So set the usable tx buf size also to half to
1170 * avoid data/delimiter underruns
1171 */
1172 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1173 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1174 } else if (!AR_SREV_9271(ah)) {
1175 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1176 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1177 }
1178
1179 REGWRITE_BUFFER_FLUSH(ah);
1180
1181 if (AR_SREV_9300_20_OR_LATER(ah))
1182 ath9k_hw_reset_txstatus_ring(ah);
1183 }
1184
ath9k_hw_set_operating_mode(struct ath_hw * ah,int opmode)1185 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1186 {
1187 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1188 u32 set = AR_STA_ID1_KSRCH_MODE;
1189
1190 switch (opmode) {
1191 case NL80211_IFTYPE_ADHOC:
1192 case NL80211_IFTYPE_MESH_POINT:
1193 set |= AR_STA_ID1_ADHOC;
1194 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1195 break;
1196 case NL80211_IFTYPE_AP:
1197 set |= AR_STA_ID1_STA_AP;
1198 /* fall through */
1199 case NL80211_IFTYPE_STATION:
1200 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1201 break;
1202 default:
1203 if (!ah->is_monitoring)
1204 set = 0;
1205 break;
1206 }
1207 REG_RMW(ah, AR_STA_ID1, set, mask);
1208 }
1209
ath9k_hw_get_delta_slope_vals(struct ath_hw * ah,u32 coef_scaled,u32 * coef_mantissa,u32 * coef_exponent)1210 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1211 u32 *coef_mantissa, u32 *coef_exponent)
1212 {
1213 u32 coef_exp, coef_man;
1214
1215 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1216 if ((coef_scaled >> coef_exp) & 0x1)
1217 break;
1218
1219 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1220
1221 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1222
1223 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1224 *coef_exponent = coef_exp - 16;
1225 }
1226
ath9k_hw_set_reset(struct ath_hw * ah,int type)1227 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1228 {
1229 u32 rst_flags;
1230 u32 tmpReg;
1231
1232 if (AR_SREV_9100(ah)) {
1233 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1234 AR_RTC_DERIVED_CLK_PERIOD, 1);
1235 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1236 }
1237
1238 ENABLE_REGWRITE_BUFFER(ah);
1239
1240 if (AR_SREV_9300_20_OR_LATER(ah)) {
1241 REG_WRITE(ah, AR_WA, ah->WARegVal);
1242 udelay(10);
1243 }
1244
1245 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1246 AR_RTC_FORCE_WAKE_ON_INT);
1247
1248 if (AR_SREV_9100(ah)) {
1249 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1250 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1251 } else {
1252 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1253 if (tmpReg &
1254 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1255 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1256 u32 val;
1257 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1258
1259 val = AR_RC_HOSTIF;
1260 if (!AR_SREV_9300_20_OR_LATER(ah))
1261 val |= AR_RC_AHB;
1262 REG_WRITE(ah, AR_RC, val);
1263
1264 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1265 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1266
1267 rst_flags = AR_RTC_RC_MAC_WARM;
1268 if (type == ATH9K_RESET_COLD)
1269 rst_flags |= AR_RTC_RC_MAC_COLD;
1270 }
1271
1272 if (AR_SREV_9330(ah)) {
1273 int npend = 0;
1274 int i;
1275
1276 /* AR9330 WAR:
1277 * call external reset function to reset WMAC if:
1278 * - doing a cold reset
1279 * - we have pending frames in the TX queues
1280 */
1281
1282 for (i = 0; i < AR_NUM_QCU; i++) {
1283 npend = ath9k_hw_numtxpending(ah, i);
1284 if (npend)
1285 break;
1286 }
1287
1288 if (ah->external_reset &&
1289 (npend || type == ATH9K_RESET_COLD)) {
1290 int reset_err = 0;
1291
1292 ath_dbg(ath9k_hw_common(ah), RESET,
1293 "reset MAC via external reset\n");
1294
1295 reset_err = ah->external_reset();
1296 if (reset_err) {
1297 ath_err(ath9k_hw_common(ah),
1298 "External reset failed, err=%d\n",
1299 reset_err);
1300 return false;
1301 }
1302
1303 REG_WRITE(ah, AR_RTC_RESET, 1);
1304 }
1305 }
1306
1307 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1308
1309 REGWRITE_BUFFER_FLUSH(ah);
1310
1311 udelay(50);
1312
1313 REG_WRITE(ah, AR_RTC_RC, 0);
1314 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1315 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1316 return false;
1317 }
1318
1319 if (!AR_SREV_9100(ah))
1320 REG_WRITE(ah, AR_RC, 0);
1321
1322 if (AR_SREV_9100(ah))
1323 udelay(50);
1324
1325 return true;
1326 }
1327
ath9k_hw_set_reset_power_on(struct ath_hw * ah)1328 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1329 {
1330 ENABLE_REGWRITE_BUFFER(ah);
1331
1332 if (AR_SREV_9300_20_OR_LATER(ah)) {
1333 REG_WRITE(ah, AR_WA, ah->WARegVal);
1334 udelay(10);
1335 }
1336
1337 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1338 AR_RTC_FORCE_WAKE_ON_INT);
1339
1340 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1341 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1342
1343 REG_WRITE(ah, AR_RTC_RESET, 0);
1344
1345 REGWRITE_BUFFER_FLUSH(ah);
1346
1347 if (!AR_SREV_9300_20_OR_LATER(ah))
1348 udelay(2);
1349
1350 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1351 REG_WRITE(ah, AR_RC, 0);
1352
1353 REG_WRITE(ah, AR_RTC_RESET, 1);
1354
1355 if (!ath9k_hw_wait(ah,
1356 AR_RTC_STATUS,
1357 AR_RTC_STATUS_M,
1358 AR_RTC_STATUS_ON,
1359 AH_WAIT_TIMEOUT)) {
1360 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1361 return false;
1362 }
1363
1364 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1365 }
1366
ath9k_hw_set_reset_reg(struct ath_hw * ah,u32 type)1367 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1368 {
1369 bool ret = false;
1370
1371 if (AR_SREV_9300_20_OR_LATER(ah)) {
1372 REG_WRITE(ah, AR_WA, ah->WARegVal);
1373 udelay(10);
1374 }
1375
1376 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1377 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1378
1379 switch (type) {
1380 case ATH9K_RESET_POWER_ON:
1381 ret = ath9k_hw_set_reset_power_on(ah);
1382 break;
1383 case ATH9K_RESET_WARM:
1384 case ATH9K_RESET_COLD:
1385 ret = ath9k_hw_set_reset(ah, type);
1386 break;
1387 default:
1388 break;
1389 }
1390
1391 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1392 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1393
1394 return ret;
1395 }
1396
ath9k_hw_chip_reset(struct ath_hw * ah,struct ath9k_channel * chan)1397 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1398 struct ath9k_channel *chan)
1399 {
1400 int reset_type = ATH9K_RESET_WARM;
1401
1402 if (AR_SREV_9280(ah)) {
1403 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1404 reset_type = ATH9K_RESET_POWER_ON;
1405 else
1406 reset_type = ATH9K_RESET_COLD;
1407 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1408 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1409 reset_type = ATH9K_RESET_COLD;
1410
1411 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1412 return false;
1413
1414 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1415 return false;
1416
1417 ah->chip_fullsleep = false;
1418 ath9k_hw_init_pll(ah, chan);
1419 ath9k_hw_set_rfmode(ah, chan);
1420
1421 return true;
1422 }
1423
ath9k_hw_channel_change(struct ath_hw * ah,struct ath9k_channel * chan)1424 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1425 struct ath9k_channel *chan)
1426 {
1427 struct ath_common *common = ath9k_hw_common(ah);
1428 u32 qnum;
1429 int r;
1430 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1431 bool band_switch, mode_diff;
1432 u8 ini_reloaded;
1433
1434 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1435 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1436 CHANNEL_5GHZ));
1437 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1438
1439 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1440 if (ath9k_hw_numtxpending(ah, qnum)) {
1441 ath_dbg(common, QUEUE,
1442 "Transmit frames pending on queue %d\n", qnum);
1443 return false;
1444 }
1445 }
1446
1447 if (!ath9k_hw_rfbus_req(ah)) {
1448 ath_err(common, "Could not kill baseband RX\n");
1449 return false;
1450 }
1451
1452 if (edma && (band_switch || mode_diff)) {
1453 ath9k_hw_mark_phy_inactive(ah);
1454 udelay(5);
1455
1456 ath9k_hw_init_pll(ah, NULL);
1457
1458 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1459 ath_err(common, "Failed to do fast channel change\n");
1460 return false;
1461 }
1462 }
1463
1464 ath9k_hw_set_channel_regs(ah, chan);
1465
1466 r = ath9k_hw_rf_set_freq(ah, chan);
1467 if (r) {
1468 ath_err(common, "Failed to set channel\n");
1469 return false;
1470 }
1471 ath9k_hw_set_clockrate(ah);
1472 ath9k_hw_apply_txpower(ah, chan, false);
1473 ath9k_hw_rfbus_done(ah);
1474
1475 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1476 ath9k_hw_set_delta_slope(ah, chan);
1477
1478 ath9k_hw_spur_mitigate_freq(ah, chan);
1479
1480 if (edma && (band_switch || mode_diff)) {
1481 ah->ah_flags |= AH_FASTCC;
1482 if (band_switch || ini_reloaded)
1483 ah->eep_ops->set_board_values(ah, chan);
1484
1485 ath9k_hw_init_bb(ah, chan);
1486
1487 if (band_switch || ini_reloaded)
1488 ath9k_hw_init_cal(ah, chan);
1489 ah->ah_flags &= ~AH_FASTCC;
1490 }
1491
1492 return true;
1493 }
1494
ath9k_hw_apply_gpio_override(struct ath_hw * ah)1495 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1496 {
1497 u32 gpio_mask = ah->gpio_mask;
1498 int i;
1499
1500 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1501 if (!(gpio_mask & 1))
1502 continue;
1503
1504 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1505 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1506 }
1507 }
1508
ath9k_hw_check_alive(struct ath_hw * ah)1509 bool ath9k_hw_check_alive(struct ath_hw *ah)
1510 {
1511 int count = 50;
1512 u32 reg;
1513
1514 if (AR_SREV_9285_12_OR_LATER(ah))
1515 return true;
1516
1517 do {
1518 reg = REG_READ(ah, AR_OBS_BUS_1);
1519
1520 if ((reg & 0x7E7FFFEF) == 0x00702400)
1521 continue;
1522
1523 switch (reg & 0x7E000B00) {
1524 case 0x1E000000:
1525 case 0x52000B00:
1526 case 0x18000B00:
1527 continue;
1528 default:
1529 return true;
1530 }
1531 } while (count-- > 0);
1532
1533 return false;
1534 }
1535 EXPORT_SYMBOL(ath9k_hw_check_alive);
1536
1537 /*
1538 * Fast channel change:
1539 * (Change synthesizer based on channel freq without resetting chip)
1540 *
1541 * Don't do FCC when
1542 * - Flag is not set
1543 * - Chip is just coming out of full sleep
1544 * - Channel to be set is same as current channel
1545 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1546 */
ath9k_hw_do_fastcc(struct ath_hw * ah,struct ath9k_channel * chan)1547 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1548 {
1549 struct ath_common *common = ath9k_hw_common(ah);
1550 int ret;
1551
1552 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1553 goto fail;
1554
1555 if (ah->chip_fullsleep)
1556 goto fail;
1557
1558 if (!ah->curchan)
1559 goto fail;
1560
1561 if (chan->channel == ah->curchan->channel)
1562 goto fail;
1563
1564 if ((chan->channelFlags & CHANNEL_ALL) !=
1565 (ah->curchan->channelFlags & CHANNEL_ALL))
1566 goto fail;
1567
1568 if (!ath9k_hw_check_alive(ah))
1569 goto fail;
1570
1571 /*
1572 * For AR9462, make sure that calibration data for
1573 * re-using are present.
1574 */
1575 if (AR_SREV_9462(ah) && (!ah->caldata ||
1576 !ah->caldata->done_txiqcal_once ||
1577 !ah->caldata->done_txclcal_once ||
1578 !ah->caldata->rtt_hist.num_readings))
1579 goto fail;
1580
1581 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1582 ah->curchan->channel, chan->channel);
1583
1584 ret = ath9k_hw_channel_change(ah, chan);
1585 if (!ret)
1586 goto fail;
1587
1588 ath9k_hw_loadnf(ah, ah->curchan);
1589 ath9k_hw_start_nfcal(ah, true);
1590
1591 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah))
1592 ar9003_mci_2g5g_switch(ah, true);
1593
1594 if (AR_SREV_9271(ah))
1595 ar9002_hw_load_ani_reg(ah, chan);
1596
1597 return 0;
1598 fail:
1599 return -EINVAL;
1600 }
1601
ath9k_hw_reset(struct ath_hw * ah,struct ath9k_channel * chan,struct ath9k_hw_cal_data * caldata,bool fastcc)1602 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1603 struct ath9k_hw_cal_data *caldata, bool fastcc)
1604 {
1605 struct ath_common *common = ath9k_hw_common(ah);
1606 u32 saveLedState;
1607 u32 saveDefAntenna;
1608 u32 macStaId1;
1609 u64 tsf = 0;
1610 int i, r;
1611 bool start_mci_reset = false;
1612 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1613 bool save_fullsleep = ah->chip_fullsleep;
1614
1615 if (mci) {
1616 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1617 if (start_mci_reset)
1618 return 0;
1619 }
1620
1621 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1622 return -EIO;
1623
1624 if (ah->curchan && !ah->chip_fullsleep)
1625 ath9k_hw_getnf(ah, ah->curchan);
1626
1627 ah->caldata = caldata;
1628 if (caldata &&
1629 (chan->channel != caldata->channel ||
1630 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1631 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1632 /* Operating channel changed, reset channel calibration data */
1633 memset(caldata, 0, sizeof(*caldata));
1634 ath9k_init_nfcal_hist_buffer(ah, chan);
1635 }
1636 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1637
1638 if (fastcc) {
1639 r = ath9k_hw_do_fastcc(ah, chan);
1640 if (!r)
1641 return r;
1642 }
1643
1644 if (mci)
1645 ar9003_mci_stop_bt(ah, save_fullsleep);
1646
1647 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1648 if (saveDefAntenna == 0)
1649 saveDefAntenna = 1;
1650
1651 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1652
1653 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1654 if (AR_SREV_9100(ah) ||
1655 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1656 tsf = ath9k_hw_gettsf64(ah);
1657
1658 saveLedState = REG_READ(ah, AR_CFG_LED) &
1659 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1660 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1661
1662 ath9k_hw_mark_phy_inactive(ah);
1663
1664 ah->paprd_table_write_done = false;
1665
1666 /* Only required on the first reset */
1667 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1668 REG_WRITE(ah,
1669 AR9271_RESET_POWER_DOWN_CONTROL,
1670 AR9271_RADIO_RF_RST);
1671 udelay(50);
1672 }
1673
1674 if (!ath9k_hw_chip_reset(ah, chan)) {
1675 ath_err(common, "Chip reset failed\n");
1676 return -EINVAL;
1677 }
1678
1679 /* Only required on the first reset */
1680 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1681 ah->htc_reset_init = false;
1682 REG_WRITE(ah,
1683 AR9271_RESET_POWER_DOWN_CONTROL,
1684 AR9271_GATE_MAC_CTL);
1685 udelay(50);
1686 }
1687
1688 /* Restore TSF */
1689 if (tsf)
1690 ath9k_hw_settsf64(ah, tsf);
1691
1692 if (AR_SREV_9280_20_OR_LATER(ah))
1693 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1694
1695 if (!AR_SREV_9300_20_OR_LATER(ah))
1696 ar9002_hw_enable_async_fifo(ah);
1697
1698 r = ath9k_hw_process_ini(ah, chan);
1699 if (r)
1700 return r;
1701
1702 if (mci)
1703 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1704
1705 /*
1706 * Some AR91xx SoC devices frequently fail to accept TSF writes
1707 * right after the chip reset. When that happens, write a new
1708 * value after the initvals have been applied, with an offset
1709 * based on measured time difference
1710 */
1711 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1712 tsf += 1500;
1713 ath9k_hw_settsf64(ah, tsf);
1714 }
1715
1716 /* Setup MFP options for CCMP */
1717 if (AR_SREV_9280_20_OR_LATER(ah)) {
1718 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1719 * frames when constructing CCMP AAD. */
1720 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1721 0xc7ff);
1722 ah->sw_mgmt_crypto = false;
1723 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1724 /* Disable hardware crypto for management frames */
1725 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1726 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1727 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1728 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1729 ah->sw_mgmt_crypto = true;
1730 } else
1731 ah->sw_mgmt_crypto = true;
1732
1733 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1734 ath9k_hw_set_delta_slope(ah, chan);
1735
1736 ath9k_hw_spur_mitigate_freq(ah, chan);
1737 ah->eep_ops->set_board_values(ah, chan);
1738
1739 ENABLE_REGWRITE_BUFFER(ah);
1740
1741 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1742 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1743 | macStaId1
1744 | AR_STA_ID1_RTS_USE_DEF
1745 | (ah->config.
1746 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1747 | ah->sta_id1_defaults);
1748 ath_hw_setbssidmask(common);
1749 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1750 ath9k_hw_write_associd(ah);
1751 REG_WRITE(ah, AR_ISR, ~0);
1752 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1753
1754 REGWRITE_BUFFER_FLUSH(ah);
1755
1756 ath9k_hw_set_operating_mode(ah, ah->opmode);
1757
1758 r = ath9k_hw_rf_set_freq(ah, chan);
1759 if (r)
1760 return r;
1761
1762 ath9k_hw_set_clockrate(ah);
1763
1764 ENABLE_REGWRITE_BUFFER(ah);
1765
1766 for (i = 0; i < AR_NUM_DCU; i++)
1767 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1768
1769 REGWRITE_BUFFER_FLUSH(ah);
1770
1771 ah->intr_txqs = 0;
1772 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1773 ath9k_hw_resettxqueue(ah, i);
1774
1775 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1776 ath9k_hw_ani_cache_ini_regs(ah);
1777 ath9k_hw_init_qos(ah);
1778
1779 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1780 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1781
1782 ath9k_hw_init_global_settings(ah);
1783
1784 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1785 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1786 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1787 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1788 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1789 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1790 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1791 }
1792
1793 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1794
1795 ath9k_hw_set_dma(ah);
1796
1797 REG_WRITE(ah, AR_OBS, 8);
1798
1799 if (ah->config.rx_intr_mitigation) {
1800 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1801 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1802 }
1803
1804 if (ah->config.tx_intr_mitigation) {
1805 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1806 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1807 }
1808
1809 ath9k_hw_init_bb(ah, chan);
1810
1811 if (caldata) {
1812 caldata->done_txiqcal_once = false;
1813 caldata->done_txclcal_once = false;
1814 caldata->rtt_hist.num_readings = 0;
1815 }
1816 if (!ath9k_hw_init_cal(ah, chan))
1817 return -EIO;
1818
1819 ath9k_hw_loadnf(ah, chan);
1820 ath9k_hw_start_nfcal(ah, true);
1821
1822 if (mci && ar9003_mci_end_reset(ah, chan, caldata))
1823 return -EIO;
1824
1825 ENABLE_REGWRITE_BUFFER(ah);
1826
1827 ath9k_hw_restore_chainmask(ah);
1828 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1829
1830 REGWRITE_BUFFER_FLUSH(ah);
1831
1832 /*
1833 * For big endian systems turn on swapping for descriptors
1834 */
1835 if (AR_SREV_9100(ah)) {
1836 u32 mask;
1837 mask = REG_READ(ah, AR_CFG);
1838 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1839 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1840 mask);
1841 } else {
1842 mask =
1843 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1844 REG_WRITE(ah, AR_CFG, mask);
1845 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1846 REG_READ(ah, AR_CFG));
1847 }
1848 } else {
1849 if (common->bus_ops->ath_bus_type == ATH_USB) {
1850 /* Configure AR9271 target WLAN */
1851 if (AR_SREV_9271(ah))
1852 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1853 else
1854 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1855 }
1856 #ifdef __BIG_ENDIAN
1857 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1858 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1859 else
1860 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1861 #endif
1862 }
1863
1864 if (ath9k_hw_btcoex_is_enabled(ah))
1865 ath9k_hw_btcoex_enable(ah);
1866
1867 if (mci)
1868 ar9003_mci_check_bt(ah);
1869
1870 if (AR_SREV_9300_20_OR_LATER(ah)) {
1871 ar9003_hw_bb_watchdog_config(ah);
1872
1873 ar9003_hw_disable_phy_restart(ah);
1874 }
1875
1876 ath9k_hw_apply_gpio_override(ah);
1877
1878 return 0;
1879 }
1880 EXPORT_SYMBOL(ath9k_hw_reset);
1881
1882 /******************************/
1883 /* Power Management (Chipset) */
1884 /******************************/
1885
1886 /*
1887 * Notify Power Mgt is disabled in self-generated frames.
1888 * If requested, force chip to sleep.
1889 */
ath9k_set_power_sleep(struct ath_hw * ah,int setChip)1890 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1891 {
1892 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1893 if (setChip) {
1894 if (AR_SREV_9462(ah)) {
1895 REG_WRITE(ah, AR_TIMER_MODE,
1896 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1897 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1898 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1899 REG_WRITE(ah, AR_SLP32_INC,
1900 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1901 /* xxx Required for WLAN only case ? */
1902 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1903 udelay(100);
1904 }
1905
1906 /*
1907 * Clear the RTC force wake bit to allow the
1908 * mac to go to sleep.
1909 */
1910 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1911
1912 if (AR_SREV_9462(ah))
1913 udelay(100);
1914
1915 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1916 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1917
1918 /* Shutdown chip. Active low */
1919 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
1920 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1921 udelay(2);
1922 }
1923 }
1924
1925 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1926 if (AR_SREV_9300_20_OR_LATER(ah))
1927 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1928 }
1929
1930 /*
1931 * Notify Power Management is enabled in self-generating
1932 * frames. If request, set power mode of chip to
1933 * auto/normal. Duration in units of 128us (1/8 TU).
1934 */
ath9k_set_power_network_sleep(struct ath_hw * ah,int setChip)1935 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1936 {
1937 u32 val;
1938
1939 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1940 if (setChip) {
1941 struct ath9k_hw_capabilities *pCap = &ah->caps;
1942
1943 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1944 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1945 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1946 AR_RTC_FORCE_WAKE_ON_INT);
1947 } else {
1948
1949 /* When chip goes into network sleep, it could be waken
1950 * up by MCI_INT interrupt caused by BT's HW messages
1951 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1952 * rate (~100us). This will cause chip to leave and
1953 * re-enter network sleep mode frequently, which in
1954 * consequence will have WLAN MCI HW to generate lots of
1955 * SYS_WAKING and SYS_SLEEPING messages which will make
1956 * BT CPU to busy to process.
1957 */
1958 if (AR_SREV_9462(ah)) {
1959 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
1960 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
1961 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
1962 }
1963 /*
1964 * Clear the RTC force wake bit to allow the
1965 * mac to go to sleep.
1966 */
1967 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1968 AR_RTC_FORCE_WAKE_EN);
1969
1970 if (AR_SREV_9462(ah))
1971 udelay(30);
1972 }
1973 }
1974
1975 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1976 if (AR_SREV_9300_20_OR_LATER(ah))
1977 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1978 }
1979
ath9k_hw_set_power_awake(struct ath_hw * ah,int setChip)1980 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1981 {
1982 u32 val;
1983 int i;
1984
1985 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1986 if (AR_SREV_9300_20_OR_LATER(ah)) {
1987 REG_WRITE(ah, AR_WA, ah->WARegVal);
1988 udelay(10);
1989 }
1990
1991 if (setChip) {
1992 if ((REG_READ(ah, AR_RTC_STATUS) &
1993 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1994 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
1995 return false;
1996 }
1997 if (!AR_SREV_9300_20_OR_LATER(ah))
1998 ath9k_hw_init_pll(ah, NULL);
1999 }
2000 if (AR_SREV_9100(ah))
2001 REG_SET_BIT(ah, AR_RTC_RESET,
2002 AR_RTC_RESET_EN);
2003
2004 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2005 AR_RTC_FORCE_WAKE_EN);
2006 udelay(50);
2007
2008 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2009 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2010 if (val == AR_RTC_STATUS_ON)
2011 break;
2012 udelay(50);
2013 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2014 AR_RTC_FORCE_WAKE_EN);
2015 }
2016 if (i == 0) {
2017 ath_err(ath9k_hw_common(ah),
2018 "Failed to wakeup in %uus\n",
2019 POWER_UP_TIME / 20);
2020 return false;
2021 }
2022 }
2023
2024 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2025
2026 return true;
2027 }
2028
ath9k_hw_setpower(struct ath_hw * ah,enum ath9k_power_mode mode)2029 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2030 {
2031 struct ath_common *common = ath9k_hw_common(ah);
2032 int status = true, setChip = true;
2033 static const char *modes[] = {
2034 "AWAKE",
2035 "FULL-SLEEP",
2036 "NETWORK SLEEP",
2037 "UNDEFINED"
2038 };
2039
2040 if (ah->power_mode == mode)
2041 return status;
2042
2043 ath_dbg(common, RESET, "%s -> %s\n",
2044 modes[ah->power_mode], modes[mode]);
2045
2046 switch (mode) {
2047 case ATH9K_PM_AWAKE:
2048 status = ath9k_hw_set_power_awake(ah, setChip);
2049
2050 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2051 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2052
2053 break;
2054 case ATH9K_PM_FULL_SLEEP:
2055 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2056 ar9003_mci_set_full_sleep(ah);
2057
2058 ath9k_set_power_sleep(ah, setChip);
2059 ah->chip_fullsleep = true;
2060 break;
2061 case ATH9K_PM_NETWORK_SLEEP:
2062
2063 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2064 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2065
2066 ath9k_set_power_network_sleep(ah, setChip);
2067 break;
2068 default:
2069 ath_err(common, "Unknown power mode %u\n", mode);
2070 return false;
2071 }
2072 ah->power_mode = mode;
2073
2074 /*
2075 * XXX: If this warning never comes up after a while then
2076 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2077 * ath9k_hw_setpower() return type void.
2078 */
2079
2080 if (!(ah->ah_flags & AH_UNPLUGGED))
2081 ATH_DBG_WARN_ON_ONCE(!status);
2082
2083 return status;
2084 }
2085 EXPORT_SYMBOL(ath9k_hw_setpower);
2086
2087 /*******************/
2088 /* Beacon Handling */
2089 /*******************/
2090
ath9k_hw_beaconinit(struct ath_hw * ah,u32 next_beacon,u32 beacon_period)2091 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2092 {
2093 int flags = 0;
2094
2095 ENABLE_REGWRITE_BUFFER(ah);
2096
2097 switch (ah->opmode) {
2098 case NL80211_IFTYPE_ADHOC:
2099 case NL80211_IFTYPE_MESH_POINT:
2100 REG_SET_BIT(ah, AR_TXCFG,
2101 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2102 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2103 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2104 flags |= AR_NDP_TIMER_EN;
2105 case NL80211_IFTYPE_AP:
2106 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2107 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2108 TU_TO_USEC(ah->config.dma_beacon_response_time));
2109 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2110 TU_TO_USEC(ah->config.sw_beacon_response_time));
2111 flags |=
2112 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2113 break;
2114 default:
2115 ath_dbg(ath9k_hw_common(ah), BEACON,
2116 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2117 return;
2118 break;
2119 }
2120
2121 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2122 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2123 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2124 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2125
2126 REGWRITE_BUFFER_FLUSH(ah);
2127
2128 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2129 }
2130 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2131
ath9k_hw_set_sta_beacon_timers(struct ath_hw * ah,const struct ath9k_beacon_state * bs)2132 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2133 const struct ath9k_beacon_state *bs)
2134 {
2135 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2136 struct ath9k_hw_capabilities *pCap = &ah->caps;
2137 struct ath_common *common = ath9k_hw_common(ah);
2138
2139 ENABLE_REGWRITE_BUFFER(ah);
2140
2141 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2142
2143 REG_WRITE(ah, AR_BEACON_PERIOD,
2144 TU_TO_USEC(bs->bs_intval));
2145 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2146 TU_TO_USEC(bs->bs_intval));
2147
2148 REGWRITE_BUFFER_FLUSH(ah);
2149
2150 REG_RMW_FIELD(ah, AR_RSSI_THR,
2151 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2152
2153 beaconintval = bs->bs_intval;
2154
2155 if (bs->bs_sleepduration > beaconintval)
2156 beaconintval = bs->bs_sleepduration;
2157
2158 dtimperiod = bs->bs_dtimperiod;
2159 if (bs->bs_sleepduration > dtimperiod)
2160 dtimperiod = bs->bs_sleepduration;
2161
2162 if (beaconintval == dtimperiod)
2163 nextTbtt = bs->bs_nextdtim;
2164 else
2165 nextTbtt = bs->bs_nexttbtt;
2166
2167 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2168 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2169 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2170 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2171
2172 ENABLE_REGWRITE_BUFFER(ah);
2173
2174 REG_WRITE(ah, AR_NEXT_DTIM,
2175 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2176 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2177
2178 REG_WRITE(ah, AR_SLEEP1,
2179 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2180 | AR_SLEEP1_ASSUME_DTIM);
2181
2182 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2183 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2184 else
2185 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2186
2187 REG_WRITE(ah, AR_SLEEP2,
2188 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2189
2190 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2191 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2192
2193 REGWRITE_BUFFER_FLUSH(ah);
2194
2195 REG_SET_BIT(ah, AR_TIMER_MODE,
2196 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2197 AR_DTIM_TIMER_EN);
2198
2199 /* TSF Out of Range Threshold */
2200 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2201 }
2202 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2203
2204 /*******************/
2205 /* HW Capabilities */
2206 /*******************/
2207
fixup_chainmask(u8 chip_chainmask,u8 eeprom_chainmask)2208 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2209 {
2210 eeprom_chainmask &= chip_chainmask;
2211 if (eeprom_chainmask)
2212 return eeprom_chainmask;
2213 else
2214 return chip_chainmask;
2215 }
2216
2217 /**
2218 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2219 * @ah: the atheros hardware data structure
2220 *
2221 * We enable DFS support upstream on chipsets which have passed a series
2222 * of tests. The testing requirements are going to be documented. Desired
2223 * test requirements are documented at:
2224 *
2225 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2226 *
2227 * Once a new chipset gets properly tested an individual commit can be used
2228 * to document the testing for DFS for that chipset.
2229 */
ath9k_hw_dfs_tested(struct ath_hw * ah)2230 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2231 {
2232
2233 switch (ah->hw_version.macVersion) {
2234 /* AR9580 will likely be our first target to get testing on */
2235 case AR_SREV_VERSION_9580:
2236 default:
2237 return false;
2238 }
2239 }
2240
ath9k_hw_fill_cap_info(struct ath_hw * ah)2241 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2242 {
2243 struct ath9k_hw_capabilities *pCap = &ah->caps;
2244 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2245 struct ath_common *common = ath9k_hw_common(ah);
2246 unsigned int chip_chainmask;
2247
2248 u16 eeval;
2249 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2250
2251 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2252 regulatory->current_rd = eeval;
2253
2254 if (ah->opmode != NL80211_IFTYPE_AP &&
2255 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2256 if (regulatory->current_rd == 0x64 ||
2257 regulatory->current_rd == 0x65)
2258 regulatory->current_rd += 5;
2259 else if (regulatory->current_rd == 0x41)
2260 regulatory->current_rd = 0x43;
2261 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2262 regulatory->current_rd);
2263 }
2264
2265 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2266 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2267 ath_err(common,
2268 "no band has been marked as supported in EEPROM\n");
2269 return -EINVAL;
2270 }
2271
2272 if (eeval & AR5416_OPFLAGS_11A)
2273 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2274
2275 if (eeval & AR5416_OPFLAGS_11G)
2276 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2277
2278 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2279 chip_chainmask = 1;
2280 else if (AR_SREV_9462(ah))
2281 chip_chainmask = 3;
2282 else if (!AR_SREV_9280_20_OR_LATER(ah))
2283 chip_chainmask = 7;
2284 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2285 chip_chainmask = 3;
2286 else
2287 chip_chainmask = 7;
2288
2289 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2290 /*
2291 * For AR9271 we will temporarilly uses the rx chainmax as read from
2292 * the EEPROM.
2293 */
2294 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2295 !(eeval & AR5416_OPFLAGS_11A) &&
2296 !(AR_SREV_9271(ah)))
2297 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2298 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2299 else if (AR_SREV_9100(ah))
2300 pCap->rx_chainmask = 0x7;
2301 else
2302 /* Use rx_chainmask from EEPROM. */
2303 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2304
2305 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2306 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2307 ah->txchainmask = pCap->tx_chainmask;
2308 ah->rxchainmask = pCap->rx_chainmask;
2309
2310 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2311
2312 /* enable key search for every frame in an aggregate */
2313 if (AR_SREV_9300_20_OR_LATER(ah))
2314 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2315
2316 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2317
2318 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2319 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2320 else
2321 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2322
2323 if (AR_SREV_9271(ah))
2324 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2325 else if (AR_DEVID_7010(ah))
2326 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2327 else if (AR_SREV_9300_20_OR_LATER(ah))
2328 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2329 else if (AR_SREV_9287_11_OR_LATER(ah))
2330 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2331 else if (AR_SREV_9285_12_OR_LATER(ah))
2332 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2333 else if (AR_SREV_9280_20_OR_LATER(ah))
2334 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2335 else
2336 pCap->num_gpio_pins = AR_NUM_GPIO;
2337
2338 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2339 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2340 else
2341 pCap->rts_aggr_limit = (8 * 1024);
2342
2343 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2344 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2345 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2346 ah->rfkill_gpio =
2347 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2348 ah->rfkill_polarity =
2349 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2350
2351 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2352 }
2353 #endif
2354 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2355 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2356 else
2357 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2358
2359 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2360 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2361 else
2362 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2363
2364 if (AR_SREV_9300_20_OR_LATER(ah)) {
2365 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2366 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2367 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2368
2369 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2370 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2371 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2372 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2373 pCap->txs_len = sizeof(struct ar9003_txs);
2374 if (!ah->config.paprd_disable &&
2375 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2376 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2377 } else {
2378 pCap->tx_desc_len = sizeof(struct ath_desc);
2379 if (AR_SREV_9280_20(ah))
2380 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2381 }
2382
2383 if (AR_SREV_9300_20_OR_LATER(ah))
2384 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2385
2386 if (AR_SREV_9300_20_OR_LATER(ah))
2387 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2388
2389 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2390 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2391
2392 if (AR_SREV_9285(ah))
2393 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2394 ant_div_ctl1 =
2395 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2396 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2397 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2398 }
2399 if (AR_SREV_9300_20_OR_LATER(ah)) {
2400 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2401 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2402 }
2403
2404
2405 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2406 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2407 /*
2408 * enable the diversity-combining algorithm only when
2409 * both enable_lna_div and enable_fast_div are set
2410 * Table for Diversity
2411 * ant_div_alt_lnaconf bit 0-1
2412 * ant_div_main_lnaconf bit 2-3
2413 * ant_div_alt_gaintb bit 4
2414 * ant_div_main_gaintb bit 5
2415 * enable_ant_div_lnadiv bit 6
2416 * enable_ant_fast_div bit 7
2417 */
2418 if ((ant_div_ctl1 >> 0x6) == 0x3)
2419 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2420 }
2421
2422 if (AR_SREV_9485_10(ah)) {
2423 pCap->pcie_lcr_extsync_en = true;
2424 pCap->pcie_lcr_offset = 0x80;
2425 }
2426
2427 if (ath9k_hw_dfs_tested(ah))
2428 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2429
2430 tx_chainmask = pCap->tx_chainmask;
2431 rx_chainmask = pCap->rx_chainmask;
2432 while (tx_chainmask || rx_chainmask) {
2433 if (tx_chainmask & BIT(0))
2434 pCap->max_txchains++;
2435 if (rx_chainmask & BIT(0))
2436 pCap->max_rxchains++;
2437
2438 tx_chainmask >>= 1;
2439 rx_chainmask >>= 1;
2440 }
2441
2442 if (AR_SREV_9300_20_OR_LATER(ah)) {
2443 ah->enabled_cals |= TX_IQ_CAL;
2444 if (AR_SREV_9485_OR_LATER(ah))
2445 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2446 }
2447
2448 if (AR_SREV_9462(ah)) {
2449
2450 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2451 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2452
2453 if (AR_SREV_9462_20(ah))
2454 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2455
2456 }
2457
2458
2459 return 0;
2460 }
2461
2462 /****************************/
2463 /* GPIO / RFKILL / Antennae */
2464 /****************************/
2465
ath9k_hw_gpio_cfg_output_mux(struct ath_hw * ah,u32 gpio,u32 type)2466 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2467 u32 gpio, u32 type)
2468 {
2469 int addr;
2470 u32 gpio_shift, tmp;
2471
2472 if (gpio > 11)
2473 addr = AR_GPIO_OUTPUT_MUX3;
2474 else if (gpio > 5)
2475 addr = AR_GPIO_OUTPUT_MUX2;
2476 else
2477 addr = AR_GPIO_OUTPUT_MUX1;
2478
2479 gpio_shift = (gpio % 6) * 5;
2480
2481 if (AR_SREV_9280_20_OR_LATER(ah)
2482 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2483 REG_RMW(ah, addr, (type << gpio_shift),
2484 (0x1f << gpio_shift));
2485 } else {
2486 tmp = REG_READ(ah, addr);
2487 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2488 tmp &= ~(0x1f << gpio_shift);
2489 tmp |= (type << gpio_shift);
2490 REG_WRITE(ah, addr, tmp);
2491 }
2492 }
2493
ath9k_hw_cfg_gpio_input(struct ath_hw * ah,u32 gpio)2494 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2495 {
2496 u32 gpio_shift;
2497
2498 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2499
2500 if (AR_DEVID_7010(ah)) {
2501 gpio_shift = gpio;
2502 REG_RMW(ah, AR7010_GPIO_OE,
2503 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2504 (AR7010_GPIO_OE_MASK << gpio_shift));
2505 return;
2506 }
2507
2508 gpio_shift = gpio << 1;
2509 REG_RMW(ah,
2510 AR_GPIO_OE_OUT,
2511 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2512 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2513 }
2514 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2515
ath9k_hw_gpio_get(struct ath_hw * ah,u32 gpio)2516 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2517 {
2518 #define MS_REG_READ(x, y) \
2519 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2520
2521 if (gpio >= ah->caps.num_gpio_pins)
2522 return 0xffffffff;
2523
2524 if (AR_DEVID_7010(ah)) {
2525 u32 val;
2526 val = REG_READ(ah, AR7010_GPIO_IN);
2527 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2528 } else if (AR_SREV_9300_20_OR_LATER(ah))
2529 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2530 AR_GPIO_BIT(gpio)) != 0;
2531 else if (AR_SREV_9271(ah))
2532 return MS_REG_READ(AR9271, gpio) != 0;
2533 else if (AR_SREV_9287_11_OR_LATER(ah))
2534 return MS_REG_READ(AR9287, gpio) != 0;
2535 else if (AR_SREV_9285_12_OR_LATER(ah))
2536 return MS_REG_READ(AR9285, gpio) != 0;
2537 else if (AR_SREV_9280_20_OR_LATER(ah))
2538 return MS_REG_READ(AR928X, gpio) != 0;
2539 else
2540 return MS_REG_READ(AR, gpio) != 0;
2541 }
2542 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2543
ath9k_hw_cfg_output(struct ath_hw * ah,u32 gpio,u32 ah_signal_type)2544 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2545 u32 ah_signal_type)
2546 {
2547 u32 gpio_shift;
2548
2549 if (AR_DEVID_7010(ah)) {
2550 gpio_shift = gpio;
2551 REG_RMW(ah, AR7010_GPIO_OE,
2552 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2553 (AR7010_GPIO_OE_MASK << gpio_shift));
2554 return;
2555 }
2556
2557 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2558 gpio_shift = 2 * gpio;
2559 REG_RMW(ah,
2560 AR_GPIO_OE_OUT,
2561 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2562 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2563 }
2564 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2565
ath9k_hw_set_gpio(struct ath_hw * ah,u32 gpio,u32 val)2566 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2567 {
2568 if (AR_DEVID_7010(ah)) {
2569 val = val ? 0 : 1;
2570 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2571 AR_GPIO_BIT(gpio));
2572 return;
2573 }
2574
2575 if (AR_SREV_9271(ah))
2576 val = ~val;
2577
2578 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2579 AR_GPIO_BIT(gpio));
2580 }
2581 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2582
ath9k_hw_setantenna(struct ath_hw * ah,u32 antenna)2583 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2584 {
2585 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2586 }
2587 EXPORT_SYMBOL(ath9k_hw_setantenna);
2588
2589 /*********************/
2590 /* General Operation */
2591 /*********************/
2592
ath9k_hw_getrxfilter(struct ath_hw * ah)2593 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2594 {
2595 u32 bits = REG_READ(ah, AR_RX_FILTER);
2596 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2597
2598 if (phybits & AR_PHY_ERR_RADAR)
2599 bits |= ATH9K_RX_FILTER_PHYRADAR;
2600 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2601 bits |= ATH9K_RX_FILTER_PHYERR;
2602
2603 return bits;
2604 }
2605 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2606
ath9k_hw_setrxfilter(struct ath_hw * ah,u32 bits)2607 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2608 {
2609 u32 phybits;
2610
2611 ENABLE_REGWRITE_BUFFER(ah);
2612
2613 if (AR_SREV_9462(ah))
2614 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2615
2616 REG_WRITE(ah, AR_RX_FILTER, bits);
2617
2618 phybits = 0;
2619 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2620 phybits |= AR_PHY_ERR_RADAR;
2621 if (bits & ATH9K_RX_FILTER_PHYERR)
2622 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2623 REG_WRITE(ah, AR_PHY_ERR, phybits);
2624
2625 if (phybits)
2626 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2627 else
2628 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2629
2630 REGWRITE_BUFFER_FLUSH(ah);
2631 }
2632 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2633
ath9k_hw_phy_disable(struct ath_hw * ah)2634 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2635 {
2636 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2637 return false;
2638
2639 ath9k_hw_init_pll(ah, NULL);
2640 ah->htc_reset_init = true;
2641 return true;
2642 }
2643 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2644
ath9k_hw_disable(struct ath_hw * ah)2645 bool ath9k_hw_disable(struct ath_hw *ah)
2646 {
2647 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2648 return false;
2649
2650 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2651 return false;
2652
2653 ath9k_hw_init_pll(ah, NULL);
2654 return true;
2655 }
2656 EXPORT_SYMBOL(ath9k_hw_disable);
2657
get_antenna_gain(struct ath_hw * ah,struct ath9k_channel * chan)2658 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2659 {
2660 enum eeprom_param gain_param;
2661
2662 if (IS_CHAN_2GHZ(chan))
2663 gain_param = EEP_ANTENNA_GAIN_2G;
2664 else
2665 gain_param = EEP_ANTENNA_GAIN_5G;
2666
2667 return ah->eep_ops->get_eeprom(ah, gain_param);
2668 }
2669
ath9k_hw_apply_txpower(struct ath_hw * ah,struct ath9k_channel * chan,bool test)2670 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2671 bool test)
2672 {
2673 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2674 struct ieee80211_channel *channel;
2675 int chan_pwr, new_pwr, max_gain;
2676 int ant_gain, ant_reduction = 0;
2677
2678 if (!chan)
2679 return;
2680
2681 channel = chan->chan;
2682 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2683 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2684 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2685
2686 ant_gain = get_antenna_gain(ah, chan);
2687 if (ant_gain > max_gain)
2688 ant_reduction = ant_gain - max_gain;
2689
2690 ah->eep_ops->set_txpower(ah, chan,
2691 ath9k_regd_get_ctl(reg, chan),
2692 ant_reduction, new_pwr, test);
2693 }
2694
ath9k_hw_set_txpowerlimit(struct ath_hw * ah,u32 limit,bool test)2695 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2696 {
2697 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2698 struct ath9k_channel *chan = ah->curchan;
2699 struct ieee80211_channel *channel = chan->chan;
2700
2701 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2702 if (test)
2703 channel->max_power = MAX_RATE_POWER / 2;
2704
2705 ath9k_hw_apply_txpower(ah, chan, test);
2706
2707 if (test)
2708 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2709 }
2710 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2711
ath9k_hw_setopmode(struct ath_hw * ah)2712 void ath9k_hw_setopmode(struct ath_hw *ah)
2713 {
2714 ath9k_hw_set_operating_mode(ah, ah->opmode);
2715 }
2716 EXPORT_SYMBOL(ath9k_hw_setopmode);
2717
ath9k_hw_setmcastfilter(struct ath_hw * ah,u32 filter0,u32 filter1)2718 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2719 {
2720 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2721 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2722 }
2723 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2724
ath9k_hw_write_associd(struct ath_hw * ah)2725 void ath9k_hw_write_associd(struct ath_hw *ah)
2726 {
2727 struct ath_common *common = ath9k_hw_common(ah);
2728
2729 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2730 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2731 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2732 }
2733 EXPORT_SYMBOL(ath9k_hw_write_associd);
2734
2735 #define ATH9K_MAX_TSF_READ 10
2736
ath9k_hw_gettsf64(struct ath_hw * ah)2737 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2738 {
2739 u32 tsf_lower, tsf_upper1, tsf_upper2;
2740 int i;
2741
2742 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2743 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2744 tsf_lower = REG_READ(ah, AR_TSF_L32);
2745 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2746 if (tsf_upper2 == tsf_upper1)
2747 break;
2748 tsf_upper1 = tsf_upper2;
2749 }
2750
2751 WARN_ON( i == ATH9K_MAX_TSF_READ );
2752
2753 return (((u64)tsf_upper1 << 32) | tsf_lower);
2754 }
2755 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2756
ath9k_hw_settsf64(struct ath_hw * ah,u64 tsf64)2757 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2758 {
2759 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2760 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2761 }
2762 EXPORT_SYMBOL(ath9k_hw_settsf64);
2763
ath9k_hw_reset_tsf(struct ath_hw * ah)2764 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2765 {
2766 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2767 AH_TSF_WRITE_TIMEOUT))
2768 ath_dbg(ath9k_hw_common(ah), RESET,
2769 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2770
2771 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2772 }
2773 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2774
ath9k_hw_set_tsfadjust(struct ath_hw * ah,u32 setting)2775 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2776 {
2777 if (setting)
2778 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2779 else
2780 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2781 }
2782 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2783
ath9k_hw_set11nmac2040(struct ath_hw * ah)2784 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2785 {
2786 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2787 u32 macmode;
2788
2789 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2790 macmode = AR_2040_JOINED_RX_CLEAR;
2791 else
2792 macmode = 0;
2793
2794 REG_WRITE(ah, AR_2040_MODE, macmode);
2795 }
2796
2797 /* HW Generic timers configuration */
2798
2799 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2800 {
2801 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2802 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2803 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2804 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2805 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2806 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2807 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2808 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2809 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2810 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2811 AR_NDP2_TIMER_MODE, 0x0002},
2812 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2813 AR_NDP2_TIMER_MODE, 0x0004},
2814 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2815 AR_NDP2_TIMER_MODE, 0x0008},
2816 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2817 AR_NDP2_TIMER_MODE, 0x0010},
2818 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2819 AR_NDP2_TIMER_MODE, 0x0020},
2820 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2821 AR_NDP2_TIMER_MODE, 0x0040},
2822 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2823 AR_NDP2_TIMER_MODE, 0x0080}
2824 };
2825
2826 /* HW generic timer primitives */
2827
2828 /* compute and clear index of rightmost 1 */
rightmost_index(struct ath_gen_timer_table * timer_table,u32 * mask)2829 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2830 {
2831 u32 b;
2832
2833 b = *mask;
2834 b &= (0-b);
2835 *mask &= ~b;
2836 b *= debruijn32;
2837 b >>= 27;
2838
2839 return timer_table->gen_timer_index[b];
2840 }
2841
ath9k_hw_gettsf32(struct ath_hw * ah)2842 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2843 {
2844 return REG_READ(ah, AR_TSF_L32);
2845 }
2846 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2847
ath_gen_timer_alloc(struct ath_hw * ah,void (* trigger)(void *),void (* overflow)(void *),void * arg,u8 timer_index)2848 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2849 void (*trigger)(void *),
2850 void (*overflow)(void *),
2851 void *arg,
2852 u8 timer_index)
2853 {
2854 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2855 struct ath_gen_timer *timer;
2856
2857 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2858
2859 if (timer == NULL) {
2860 ath_err(ath9k_hw_common(ah),
2861 "Failed to allocate memory for hw timer[%d]\n",
2862 timer_index);
2863 return NULL;
2864 }
2865
2866 /* allocate a hardware generic timer slot */
2867 timer_table->timers[timer_index] = timer;
2868 timer->index = timer_index;
2869 timer->trigger = trigger;
2870 timer->overflow = overflow;
2871 timer->arg = arg;
2872
2873 return timer;
2874 }
2875 EXPORT_SYMBOL(ath_gen_timer_alloc);
2876
ath9k_hw_gen_timer_start(struct ath_hw * ah,struct ath_gen_timer * timer,u32 trig_timeout,u32 timer_period)2877 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2878 struct ath_gen_timer *timer,
2879 u32 trig_timeout,
2880 u32 timer_period)
2881 {
2882 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2883 u32 tsf, timer_next;
2884
2885 BUG_ON(!timer_period);
2886
2887 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2888
2889 tsf = ath9k_hw_gettsf32(ah);
2890
2891 timer_next = tsf + trig_timeout;
2892
2893 ath_dbg(ath9k_hw_common(ah), HWTIMER,
2894 "current tsf %x period %x timer_next %x\n",
2895 tsf, timer_period, timer_next);
2896
2897 /*
2898 * Program generic timer registers
2899 */
2900 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2901 timer_next);
2902 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2903 timer_period);
2904 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2905 gen_tmr_configuration[timer->index].mode_mask);
2906
2907 if (AR_SREV_9462(ah)) {
2908 /*
2909 * Starting from AR9462, each generic timer can select which tsf
2910 * to use. But we still follow the old rule, 0 - 7 use tsf and
2911 * 8 - 15 use tsf2.
2912 */
2913 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2914 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2915 (1 << timer->index));
2916 else
2917 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2918 (1 << timer->index));
2919 }
2920
2921 /* Enable both trigger and thresh interrupt masks */
2922 REG_SET_BIT(ah, AR_IMR_S5,
2923 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2924 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2925 }
2926 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2927
ath9k_hw_gen_timer_stop(struct ath_hw * ah,struct ath_gen_timer * timer)2928 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2929 {
2930 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2931
2932 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2933 (timer->index >= ATH_MAX_GEN_TIMER)) {
2934 return;
2935 }
2936
2937 /* Clear generic timer enable bits. */
2938 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2939 gen_tmr_configuration[timer->index].mode_mask);
2940
2941 /* Disable both trigger and thresh interrupt masks */
2942 REG_CLR_BIT(ah, AR_IMR_S5,
2943 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2944 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2945
2946 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2947 }
2948 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2949
ath_gen_timer_free(struct ath_hw * ah,struct ath_gen_timer * timer)2950 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2951 {
2952 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2953
2954 /* free the hardware generic timer slot */
2955 timer_table->timers[timer->index] = NULL;
2956 kfree(timer);
2957 }
2958 EXPORT_SYMBOL(ath_gen_timer_free);
2959
2960 /*
2961 * Generic Timer Interrupts handling
2962 */
ath_gen_timer_isr(struct ath_hw * ah)2963 void ath_gen_timer_isr(struct ath_hw *ah)
2964 {
2965 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2966 struct ath_gen_timer *timer;
2967 struct ath_common *common = ath9k_hw_common(ah);
2968 u32 trigger_mask, thresh_mask, index;
2969
2970 /* get hardware generic timer interrupt status */
2971 trigger_mask = ah->intr_gen_timer_trigger;
2972 thresh_mask = ah->intr_gen_timer_thresh;
2973 trigger_mask &= timer_table->timer_mask.val;
2974 thresh_mask &= timer_table->timer_mask.val;
2975
2976 trigger_mask &= ~thresh_mask;
2977
2978 while (thresh_mask) {
2979 index = rightmost_index(timer_table, &thresh_mask);
2980 timer = timer_table->timers[index];
2981 BUG_ON(!timer);
2982 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
2983 index);
2984 timer->overflow(timer->arg);
2985 }
2986
2987 while (trigger_mask) {
2988 index = rightmost_index(timer_table, &trigger_mask);
2989 timer = timer_table->timers[index];
2990 BUG_ON(!timer);
2991 ath_dbg(common, HWTIMER,
2992 "Gen timer[%d] trigger\n", index);
2993 timer->trigger(timer->arg);
2994 }
2995 }
2996 EXPORT_SYMBOL(ath_gen_timer_isr);
2997
2998 /********/
2999 /* HTC */
3000 /********/
3001
3002 static struct {
3003 u32 version;
3004 const char * name;
3005 } ath_mac_bb_names[] = {
3006 /* Devices with external radios */
3007 { AR_SREV_VERSION_5416_PCI, "5416" },
3008 { AR_SREV_VERSION_5416_PCIE, "5418" },
3009 { AR_SREV_VERSION_9100, "9100" },
3010 { AR_SREV_VERSION_9160, "9160" },
3011 /* Single-chip solutions */
3012 { AR_SREV_VERSION_9280, "9280" },
3013 { AR_SREV_VERSION_9285, "9285" },
3014 { AR_SREV_VERSION_9287, "9287" },
3015 { AR_SREV_VERSION_9271, "9271" },
3016 { AR_SREV_VERSION_9300, "9300" },
3017 { AR_SREV_VERSION_9330, "9330" },
3018 { AR_SREV_VERSION_9340, "9340" },
3019 { AR_SREV_VERSION_9485, "9485" },
3020 { AR_SREV_VERSION_9462, "9462" },
3021 };
3022
3023 /* For devices with external radios */
3024 static struct {
3025 u16 version;
3026 const char * name;
3027 } ath_rf_names[] = {
3028 { 0, "5133" },
3029 { AR_RAD5133_SREV_MAJOR, "5133" },
3030 { AR_RAD5122_SREV_MAJOR, "5122" },
3031 { AR_RAD2133_SREV_MAJOR, "2133" },
3032 { AR_RAD2122_SREV_MAJOR, "2122" }
3033 };
3034
3035 /*
3036 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3037 */
ath9k_hw_mac_bb_name(u32 mac_bb_version)3038 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3039 {
3040 int i;
3041
3042 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3043 if (ath_mac_bb_names[i].version == mac_bb_version) {
3044 return ath_mac_bb_names[i].name;
3045 }
3046 }
3047
3048 return "????";
3049 }
3050
3051 /*
3052 * Return the RF name. "????" is returned if the RF is unknown.
3053 * Used for devices with external radios.
3054 */
ath9k_hw_rf_name(u16 rf_version)3055 static const char *ath9k_hw_rf_name(u16 rf_version)
3056 {
3057 int i;
3058
3059 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3060 if (ath_rf_names[i].version == rf_version) {
3061 return ath_rf_names[i].name;
3062 }
3063 }
3064
3065 return "????";
3066 }
3067
ath9k_hw_name(struct ath_hw * ah,char * hw_name,size_t len)3068 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3069 {
3070 int used;
3071
3072 /* chipsets >= AR9280 are single-chip */
3073 if (AR_SREV_9280_20_OR_LATER(ah)) {
3074 used = snprintf(hw_name, len,
3075 "Atheros AR%s Rev:%x",
3076 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3077 ah->hw_version.macRev);
3078 }
3079 else {
3080 used = snprintf(hw_name, len,
3081 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3082 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3083 ah->hw_version.macRev,
3084 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3085 AR_RADIO_SREV_MAJOR)),
3086 ah->hw_version.phyRev);
3087 }
3088
3089 hw_name[used] = '\0';
3090 }
3091 EXPORT_SYMBOL(ath9k_hw_name);
3092