1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
30 #include "radeon.h"
31 #include "atom.h"
32 #include "atom-bits.h"
33
atombios_overscan_setup(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37 {
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 } else if (a2 > a1) {
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 }
67 break;
68 case RMX_FULL:
69 default:
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74 break;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77 }
78
atombios_scaler_setup(struct drm_crtc * crtc)79 static void atombios_scaler_setup(struct drm_crtc *crtc)
80 {
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
111 if (is_tv) {
112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
140 } else if (is_cv) {
141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
166 }
167 }
168
atombios_lock_crtc(struct drm_crtc * crtc,int lock)169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170 {
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184 }
185
atombios_enable_crtc(struct drm_crtc * crtc,int state)186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187 {
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200 }
201
atombios_enable_crtc_memreq(struct drm_crtc * crtc,int state)202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203 {
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216 }
217
atombios_blank_crtc(struct drm_crtc * crtc,int state)218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219 {
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232 }
233
atombios_powergate_crtc(struct drm_crtc * crtc,int state)234 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
235 {
236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
237 struct drm_device *dev = crtc->dev;
238 struct radeon_device *rdev = dev->dev_private;
239 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
240 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
241
242 memset(&args, 0, sizeof(args));
243
244 args.ucDispPipeId = radeon_crtc->crtc_id;
245 args.ucEnable = state;
246
247 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
248 }
249
atombios_crtc_dpms(struct drm_crtc * crtc,int mode)250 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
251 {
252 struct drm_device *dev = crtc->dev;
253 struct radeon_device *rdev = dev->dev_private;
254 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
255
256 switch (mode) {
257 case DRM_MODE_DPMS_ON:
258 radeon_crtc->enabled = true;
259 /* adjust pm to dpms changes BEFORE enabling crtcs */
260 radeon_pm_compute_clocks(rdev);
261 atombios_enable_crtc(crtc, ATOM_ENABLE);
262 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
263 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
264 atombios_blank_crtc(crtc, ATOM_DISABLE);
265 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
266 radeon_crtc_load_lut(crtc);
267 break;
268 case DRM_MODE_DPMS_STANDBY:
269 case DRM_MODE_DPMS_SUSPEND:
270 case DRM_MODE_DPMS_OFF:
271 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
272 if (radeon_crtc->enabled)
273 atombios_blank_crtc(crtc, ATOM_ENABLE);
274 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
275 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
276 atombios_enable_crtc(crtc, ATOM_DISABLE);
277 radeon_crtc->enabled = false;
278 /* adjust pm to dpms changes AFTER disabling crtcs */
279 radeon_pm_compute_clocks(rdev);
280 break;
281 }
282 }
283
284 static void
atombios_set_crtc_dtd_timing(struct drm_crtc * crtc,struct drm_display_mode * mode)285 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
286 struct drm_display_mode *mode)
287 {
288 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
289 struct drm_device *dev = crtc->dev;
290 struct radeon_device *rdev = dev->dev_private;
291 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
292 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
293 u16 misc = 0;
294
295 memset(&args, 0, sizeof(args));
296 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
297 args.usH_Blanking_Time =
298 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
299 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
300 args.usV_Blanking_Time =
301 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
302 args.usH_SyncOffset =
303 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
304 args.usH_SyncWidth =
305 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
306 args.usV_SyncOffset =
307 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
308 args.usV_SyncWidth =
309 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
310 args.ucH_Border = radeon_crtc->h_border;
311 args.ucV_Border = radeon_crtc->v_border;
312
313 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
314 misc |= ATOM_VSYNC_POLARITY;
315 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
316 misc |= ATOM_HSYNC_POLARITY;
317 if (mode->flags & DRM_MODE_FLAG_CSYNC)
318 misc |= ATOM_COMPOSITESYNC;
319 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
320 misc |= ATOM_INTERLACE;
321 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
322 misc |= ATOM_DOUBLE_CLOCK_MODE;
323
324 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
325 args.ucCRTC = radeon_crtc->crtc_id;
326
327 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
328 }
329
atombios_crtc_set_timing(struct drm_crtc * crtc,struct drm_display_mode * mode)330 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
331 struct drm_display_mode *mode)
332 {
333 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
334 struct drm_device *dev = crtc->dev;
335 struct radeon_device *rdev = dev->dev_private;
336 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
337 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
338 u16 misc = 0;
339
340 memset(&args, 0, sizeof(args));
341 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
342 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
343 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
344 args.usH_SyncWidth =
345 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
346 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
347 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
348 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
349 args.usV_SyncWidth =
350 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
351
352 args.ucOverscanRight = radeon_crtc->h_border;
353 args.ucOverscanLeft = radeon_crtc->h_border;
354 args.ucOverscanBottom = radeon_crtc->v_border;
355 args.ucOverscanTop = radeon_crtc->v_border;
356
357 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
358 misc |= ATOM_VSYNC_POLARITY;
359 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
360 misc |= ATOM_HSYNC_POLARITY;
361 if (mode->flags & DRM_MODE_FLAG_CSYNC)
362 misc |= ATOM_COMPOSITESYNC;
363 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
364 misc |= ATOM_INTERLACE;
365 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
366 misc |= ATOM_DOUBLE_CLOCK_MODE;
367
368 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
369 args.ucCRTC = radeon_crtc->crtc_id;
370
371 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
372 }
373
atombios_disable_ss(struct radeon_device * rdev,int pll_id)374 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
375 {
376 u32 ss_cntl;
377
378 if (ASIC_IS_DCE4(rdev)) {
379 switch (pll_id) {
380 case ATOM_PPLL1:
381 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
382 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
383 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
384 break;
385 case ATOM_PPLL2:
386 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
387 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
388 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
389 break;
390 case ATOM_DCPLL:
391 case ATOM_PPLL_INVALID:
392 return;
393 }
394 } else if (ASIC_IS_AVIVO(rdev)) {
395 switch (pll_id) {
396 case ATOM_PPLL1:
397 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
398 ss_cntl &= ~1;
399 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
400 break;
401 case ATOM_PPLL2:
402 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
403 ss_cntl &= ~1;
404 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
405 break;
406 case ATOM_DCPLL:
407 case ATOM_PPLL_INVALID:
408 return;
409 }
410 }
411 }
412
413
414 union atom_enable_ss {
415 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
416 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
417 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
418 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
419 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
420 };
421
atombios_crtc_program_ss(struct radeon_device * rdev,int enable,int pll_id,int crtc_id,struct radeon_atom_ss * ss)422 static void atombios_crtc_program_ss(struct radeon_device *rdev,
423 int enable,
424 int pll_id,
425 int crtc_id,
426 struct radeon_atom_ss *ss)
427 {
428 unsigned i;
429 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
430 union atom_enable_ss args;
431
432 if (!enable) {
433 for (i = 0; i < rdev->num_crtc; i++) {
434 if (rdev->mode_info.crtcs[i] &&
435 rdev->mode_info.crtcs[i]->enabled &&
436 i != crtc_id &&
437 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
438 /* one other crtc is using this pll don't turn
439 * off spread spectrum as it might turn off
440 * display on active crtc
441 */
442 return;
443 }
444 }
445 }
446
447 memset(&args, 0, sizeof(args));
448
449 if (ASIC_IS_DCE5(rdev)) {
450 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
451 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
452 switch (pll_id) {
453 case ATOM_PPLL1:
454 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
455 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
456 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
457 break;
458 case ATOM_PPLL2:
459 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
460 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
461 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
462 break;
463 case ATOM_DCPLL:
464 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
465 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
466 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
467 break;
468 case ATOM_PPLL_INVALID:
469 return;
470 }
471 args.v3.ucEnable = enable;
472 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
473 args.v3.ucEnable = ATOM_DISABLE;
474 } else if (ASIC_IS_DCE4(rdev)) {
475 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
476 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
477 switch (pll_id) {
478 case ATOM_PPLL1:
479 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
480 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
481 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
482 break;
483 case ATOM_PPLL2:
484 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
485 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
486 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
487 break;
488 case ATOM_DCPLL:
489 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
490 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
491 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
492 break;
493 case ATOM_PPLL_INVALID:
494 return;
495 }
496 args.v2.ucEnable = enable;
497 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
498 args.v2.ucEnable = ATOM_DISABLE;
499 } else if (ASIC_IS_DCE3(rdev)) {
500 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
501 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
502 args.v1.ucSpreadSpectrumStep = ss->step;
503 args.v1.ucSpreadSpectrumDelay = ss->delay;
504 args.v1.ucSpreadSpectrumRange = ss->range;
505 args.v1.ucPpll = pll_id;
506 args.v1.ucEnable = enable;
507 } else if (ASIC_IS_AVIVO(rdev)) {
508 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
509 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
510 atombios_disable_ss(rdev, pll_id);
511 return;
512 }
513 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
514 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
515 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
516 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
517 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
518 args.lvds_ss_2.ucEnable = enable;
519 } else {
520 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
521 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
522 atombios_disable_ss(rdev, pll_id);
523 return;
524 }
525 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
526 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
527 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
528 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
529 args.lvds_ss.ucEnable = enable;
530 }
531 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
532 }
533
534 union adjust_pixel_clock {
535 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
536 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
537 };
538
atombios_adjust_pll(struct drm_crtc * crtc,struct drm_display_mode * mode,struct radeon_pll * pll,bool ss_enabled,struct radeon_atom_ss * ss)539 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
540 struct drm_display_mode *mode,
541 struct radeon_pll *pll,
542 bool ss_enabled,
543 struct radeon_atom_ss *ss)
544 {
545 struct drm_device *dev = crtc->dev;
546 struct radeon_device *rdev = dev->dev_private;
547 struct drm_encoder *encoder = NULL;
548 struct radeon_encoder *radeon_encoder = NULL;
549 struct drm_connector *connector = NULL;
550 u32 adjusted_clock = mode->clock;
551 int encoder_mode = 0;
552 u32 dp_clock = mode->clock;
553 int bpc = 8;
554 bool is_duallink = false;
555
556 /* reset the pll flags */
557 pll->flags = 0;
558
559 if (ASIC_IS_AVIVO(rdev)) {
560 if ((rdev->family == CHIP_RS600) ||
561 (rdev->family == CHIP_RS690) ||
562 (rdev->family == CHIP_RS740))
563 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
564 RADEON_PLL_PREFER_CLOSEST_LOWER);
565
566 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
567 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
568 else
569 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
570
571 if (rdev->family < CHIP_RV770)
572 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
573 /* use frac fb div on APUs */
574 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
575 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
576 } else {
577 pll->flags |= RADEON_PLL_LEGACY;
578
579 if (mode->clock > 200000) /* range limits??? */
580 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
581 else
582 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
583 }
584
585 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
586 if (encoder->crtc == crtc) {
587 radeon_encoder = to_radeon_encoder(encoder);
588 connector = radeon_get_connector_for_encoder(encoder);
589 /* if (connector && connector->display_info.bpc)
590 bpc = connector->display_info.bpc; */
591 encoder_mode = atombios_get_encoder_mode(encoder);
592 is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
593 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
594 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
595 if (connector) {
596 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
597 struct radeon_connector_atom_dig *dig_connector =
598 radeon_connector->con_priv;
599
600 dp_clock = dig_connector->dp_clock;
601 }
602 }
603
604 /* use recommended ref_div for ss */
605 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
606 if (ss_enabled) {
607 if (ss->refdiv) {
608 pll->flags |= RADEON_PLL_USE_REF_DIV;
609 pll->reference_div = ss->refdiv;
610 if (ASIC_IS_AVIVO(rdev))
611 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
612 }
613 }
614 }
615
616 if (ASIC_IS_AVIVO(rdev)) {
617 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
618 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
619 adjusted_clock = mode->clock * 2;
620 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
621 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
622 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
623 pll->flags |= RADEON_PLL_IS_LCD;
624 } else {
625 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
626 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
627 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
628 pll->flags |= RADEON_PLL_USE_REF_DIV;
629 }
630 break;
631 }
632 }
633
634 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
635 * accordingly based on the encoder/transmitter to work around
636 * special hw requirements.
637 */
638 if (ASIC_IS_DCE3(rdev)) {
639 union adjust_pixel_clock args;
640 u8 frev, crev;
641 int index;
642
643 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
644 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
645 &crev))
646 return adjusted_clock;
647
648 memset(&args, 0, sizeof(args));
649
650 switch (frev) {
651 case 1:
652 switch (crev) {
653 case 1:
654 case 2:
655 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
656 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
657 args.v1.ucEncodeMode = encoder_mode;
658 if (ss_enabled && ss->percentage)
659 args.v1.ucConfig |=
660 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
661
662 atom_execute_table(rdev->mode_info.atom_context,
663 index, (uint32_t *)&args);
664 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
665 break;
666 case 3:
667 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
668 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
669 args.v3.sInput.ucEncodeMode = encoder_mode;
670 args.v3.sInput.ucDispPllConfig = 0;
671 if (ss_enabled && ss->percentage)
672 args.v3.sInput.ucDispPllConfig |=
673 DISPPLL_CONFIG_SS_ENABLE;
674 if (ENCODER_MODE_IS_DP(encoder_mode)) {
675 args.v3.sInput.ucDispPllConfig |=
676 DISPPLL_CONFIG_COHERENT_MODE;
677 /* 16200 or 27000 */
678 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
679 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
680 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
681 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
682 /* deep color support */
683 args.v3.sInput.usPixelClock =
684 cpu_to_le16((mode->clock * bpc / 8) / 10);
685 if (dig->coherent_mode)
686 args.v3.sInput.ucDispPllConfig |=
687 DISPPLL_CONFIG_COHERENT_MODE;
688 if (is_duallink)
689 args.v3.sInput.ucDispPllConfig |=
690 DISPPLL_CONFIG_DUAL_LINK;
691 }
692 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
693 ENCODER_OBJECT_ID_NONE)
694 args.v3.sInput.ucExtTransmitterID =
695 radeon_encoder_get_dp_bridge_encoder_id(encoder);
696 else
697 args.v3.sInput.ucExtTransmitterID = 0;
698
699 atom_execute_table(rdev->mode_info.atom_context,
700 index, (uint32_t *)&args);
701 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
702 if (args.v3.sOutput.ucRefDiv) {
703 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
704 pll->flags |= RADEON_PLL_USE_REF_DIV;
705 pll->reference_div = args.v3.sOutput.ucRefDiv;
706 }
707 if (args.v3.sOutput.ucPostDiv) {
708 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
709 pll->flags |= RADEON_PLL_USE_POST_DIV;
710 pll->post_div = args.v3.sOutput.ucPostDiv;
711 }
712 break;
713 default:
714 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
715 return adjusted_clock;
716 }
717 break;
718 default:
719 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
720 return adjusted_clock;
721 }
722 }
723 return adjusted_clock;
724 }
725
726 union set_pixel_clock {
727 SET_PIXEL_CLOCK_PS_ALLOCATION base;
728 PIXEL_CLOCK_PARAMETERS v1;
729 PIXEL_CLOCK_PARAMETERS_V2 v2;
730 PIXEL_CLOCK_PARAMETERS_V3 v3;
731 PIXEL_CLOCK_PARAMETERS_V5 v5;
732 PIXEL_CLOCK_PARAMETERS_V6 v6;
733 };
734
735 /* on DCE5, make sure the voltage is high enough to support the
736 * required disp clk.
737 */
atombios_crtc_set_disp_eng_pll(struct radeon_device * rdev,u32 dispclk)738 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
739 u32 dispclk)
740 {
741 u8 frev, crev;
742 int index;
743 union set_pixel_clock args;
744
745 memset(&args, 0, sizeof(args));
746
747 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
748 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
749 &crev))
750 return;
751
752 switch (frev) {
753 case 1:
754 switch (crev) {
755 case 5:
756 /* if the default dcpll clock is specified,
757 * SetPixelClock provides the dividers
758 */
759 args.v5.ucCRTC = ATOM_CRTC_INVALID;
760 args.v5.usPixelClock = cpu_to_le16(dispclk);
761 args.v5.ucPpll = ATOM_DCPLL;
762 break;
763 case 6:
764 /* if the default dcpll clock is specified,
765 * SetPixelClock provides the dividers
766 */
767 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
768 if (ASIC_IS_DCE61(rdev))
769 args.v6.ucPpll = ATOM_EXT_PLL1;
770 else if (ASIC_IS_DCE6(rdev))
771 args.v6.ucPpll = ATOM_PPLL0;
772 else
773 args.v6.ucPpll = ATOM_DCPLL;
774 break;
775 default:
776 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
777 return;
778 }
779 break;
780 default:
781 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
782 return;
783 }
784 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
785 }
786
atombios_crtc_program_pll(struct drm_crtc * crtc,u32 crtc_id,int pll_id,u32 encoder_mode,u32 encoder_id,u32 clock,u32 ref_div,u32 fb_div,u32 frac_fb_div,u32 post_div,int bpc,bool ss_enabled,struct radeon_atom_ss * ss)787 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
788 u32 crtc_id,
789 int pll_id,
790 u32 encoder_mode,
791 u32 encoder_id,
792 u32 clock,
793 u32 ref_div,
794 u32 fb_div,
795 u32 frac_fb_div,
796 u32 post_div,
797 int bpc,
798 bool ss_enabled,
799 struct radeon_atom_ss *ss)
800 {
801 struct drm_device *dev = crtc->dev;
802 struct radeon_device *rdev = dev->dev_private;
803 u8 frev, crev;
804 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
805 union set_pixel_clock args;
806
807 memset(&args, 0, sizeof(args));
808
809 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
810 &crev))
811 return;
812
813 switch (frev) {
814 case 1:
815 switch (crev) {
816 case 1:
817 if (clock == ATOM_DISABLE)
818 return;
819 args.v1.usPixelClock = cpu_to_le16(clock / 10);
820 args.v1.usRefDiv = cpu_to_le16(ref_div);
821 args.v1.usFbDiv = cpu_to_le16(fb_div);
822 args.v1.ucFracFbDiv = frac_fb_div;
823 args.v1.ucPostDiv = post_div;
824 args.v1.ucPpll = pll_id;
825 args.v1.ucCRTC = crtc_id;
826 args.v1.ucRefDivSrc = 1;
827 break;
828 case 2:
829 args.v2.usPixelClock = cpu_to_le16(clock / 10);
830 args.v2.usRefDiv = cpu_to_le16(ref_div);
831 args.v2.usFbDiv = cpu_to_le16(fb_div);
832 args.v2.ucFracFbDiv = frac_fb_div;
833 args.v2.ucPostDiv = post_div;
834 args.v2.ucPpll = pll_id;
835 args.v2.ucCRTC = crtc_id;
836 args.v2.ucRefDivSrc = 1;
837 break;
838 case 3:
839 args.v3.usPixelClock = cpu_to_le16(clock / 10);
840 args.v3.usRefDiv = cpu_to_le16(ref_div);
841 args.v3.usFbDiv = cpu_to_le16(fb_div);
842 args.v3.ucFracFbDiv = frac_fb_div;
843 args.v3.ucPostDiv = post_div;
844 args.v3.ucPpll = pll_id;
845 args.v3.ucMiscInfo = (pll_id << 2);
846 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
847 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
848 args.v3.ucTransmitterId = encoder_id;
849 args.v3.ucEncoderMode = encoder_mode;
850 break;
851 case 5:
852 args.v5.ucCRTC = crtc_id;
853 args.v5.usPixelClock = cpu_to_le16(clock / 10);
854 args.v5.ucRefDiv = ref_div;
855 args.v5.usFbDiv = cpu_to_le16(fb_div);
856 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
857 args.v5.ucPostDiv = post_div;
858 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
859 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
860 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
861 switch (bpc) {
862 case 8:
863 default:
864 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
865 break;
866 case 10:
867 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
868 break;
869 }
870 args.v5.ucTransmitterID = encoder_id;
871 args.v5.ucEncoderMode = encoder_mode;
872 args.v5.ucPpll = pll_id;
873 break;
874 case 6:
875 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
876 args.v6.ucRefDiv = ref_div;
877 args.v6.usFbDiv = cpu_to_le16(fb_div);
878 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
879 args.v6.ucPostDiv = post_div;
880 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
881 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
882 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
883 switch (bpc) {
884 case 8:
885 default:
886 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
887 break;
888 case 10:
889 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
890 break;
891 case 12:
892 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
893 break;
894 case 16:
895 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
896 break;
897 }
898 args.v6.ucTransmitterID = encoder_id;
899 args.v6.ucEncoderMode = encoder_mode;
900 args.v6.ucPpll = pll_id;
901 break;
902 default:
903 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
904 return;
905 }
906 break;
907 default:
908 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
909 return;
910 }
911
912 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
913 }
914
atombios_crtc_set_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)915 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
916 {
917 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
918 struct drm_device *dev = crtc->dev;
919 struct radeon_device *rdev = dev->dev_private;
920 struct drm_encoder *encoder = NULL;
921 struct radeon_encoder *radeon_encoder = NULL;
922 u32 pll_clock = mode->clock;
923 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
924 struct radeon_pll *pll;
925 u32 adjusted_clock;
926 int encoder_mode = 0;
927 struct radeon_atom_ss ss;
928 bool ss_enabled = false;
929 int bpc = 8;
930
931 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
932 if (encoder->crtc == crtc) {
933 radeon_encoder = to_radeon_encoder(encoder);
934 encoder_mode = atombios_get_encoder_mode(encoder);
935 break;
936 }
937 }
938
939 if (!radeon_encoder)
940 return;
941
942 switch (radeon_crtc->pll_id) {
943 case ATOM_PPLL1:
944 pll = &rdev->clock.p1pll;
945 break;
946 case ATOM_PPLL2:
947 pll = &rdev->clock.p2pll;
948 break;
949 case ATOM_DCPLL:
950 case ATOM_PPLL_INVALID:
951 default:
952 pll = &rdev->clock.dcpll;
953 break;
954 }
955
956 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
957 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
958 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
959 struct drm_connector *connector =
960 radeon_get_connector_for_encoder(encoder);
961 struct radeon_connector *radeon_connector =
962 to_radeon_connector(connector);
963 struct radeon_connector_atom_dig *dig_connector =
964 radeon_connector->con_priv;
965 int dp_clock;
966
967 /* if (connector->display_info.bpc)
968 bpc = connector->display_info.bpc; */
969
970 switch (encoder_mode) {
971 case ATOM_ENCODER_MODE_DP_MST:
972 case ATOM_ENCODER_MODE_DP:
973 /* DP/eDP */
974 dp_clock = dig_connector->dp_clock / 10;
975 if (ASIC_IS_DCE4(rdev))
976 ss_enabled =
977 radeon_atombios_get_asic_ss_info(rdev, &ss,
978 ASIC_INTERNAL_SS_ON_DP,
979 dp_clock);
980 else {
981 if (dp_clock == 16200) {
982 ss_enabled =
983 radeon_atombios_get_ppll_ss_info(rdev, &ss,
984 ATOM_DP_SS_ID2);
985 if (!ss_enabled)
986 ss_enabled =
987 radeon_atombios_get_ppll_ss_info(rdev, &ss,
988 ATOM_DP_SS_ID1);
989 } else
990 ss_enabled =
991 radeon_atombios_get_ppll_ss_info(rdev, &ss,
992 ATOM_DP_SS_ID1);
993 }
994 break;
995 case ATOM_ENCODER_MODE_LVDS:
996 if (ASIC_IS_DCE4(rdev))
997 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
998 dig->lcd_ss_id,
999 mode->clock / 10);
1000 else
1001 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
1002 dig->lcd_ss_id);
1003 break;
1004 case ATOM_ENCODER_MODE_DVI:
1005 if (ASIC_IS_DCE4(rdev))
1006 ss_enabled =
1007 radeon_atombios_get_asic_ss_info(rdev, &ss,
1008 ASIC_INTERNAL_SS_ON_TMDS,
1009 mode->clock / 10);
1010 break;
1011 case ATOM_ENCODER_MODE_HDMI:
1012 if (ASIC_IS_DCE4(rdev))
1013 ss_enabled =
1014 radeon_atombios_get_asic_ss_info(rdev, &ss,
1015 ASIC_INTERNAL_SS_ON_HDMI,
1016 mode->clock / 10);
1017 break;
1018 default:
1019 break;
1020 }
1021 }
1022
1023 /* adjust pixel clock as needed */
1024 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
1025
1026 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1027 /* TV seems to prefer the legacy algo on some boards */
1028 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1029 &ref_div, &post_div);
1030 else if (ASIC_IS_AVIVO(rdev))
1031 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1032 &ref_div, &post_div);
1033 else
1034 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1035 &ref_div, &post_div);
1036
1037 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1038
1039 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1040 encoder_mode, radeon_encoder->encoder_id, mode->clock,
1041 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
1042
1043 if (ss_enabled) {
1044 /* calculate ss amount and step size */
1045 if (ASIC_IS_DCE4(rdev)) {
1046 u32 step_size;
1047 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1048 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1049 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1050 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1051 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1052 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1053 (125 * 25 * pll->reference_freq / 100);
1054 else
1055 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1056 (125 * 25 * pll->reference_freq / 100);
1057 ss.step = step_size;
1058 }
1059
1060 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1061 }
1062 }
1063
dce4_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)1064 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1065 struct drm_framebuffer *fb,
1066 int x, int y, int atomic)
1067 {
1068 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1069 struct drm_device *dev = crtc->dev;
1070 struct radeon_device *rdev = dev->dev_private;
1071 struct radeon_framebuffer *radeon_fb;
1072 struct drm_framebuffer *target_fb;
1073 struct drm_gem_object *obj;
1074 struct radeon_bo *rbo;
1075 uint64_t fb_location;
1076 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1077 unsigned bankw, bankh, mtaspect, tile_split;
1078 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1079 u32 tmp, viewport_w, viewport_h;
1080 int r;
1081
1082 /* no fb bound */
1083 if (!atomic && !crtc->fb) {
1084 DRM_DEBUG_KMS("No FB bound\n");
1085 return 0;
1086 }
1087
1088 if (atomic) {
1089 radeon_fb = to_radeon_framebuffer(fb);
1090 target_fb = fb;
1091 }
1092 else {
1093 radeon_fb = to_radeon_framebuffer(crtc->fb);
1094 target_fb = crtc->fb;
1095 }
1096
1097 /* If atomic, assume fb object is pinned & idle & fenced and
1098 * just update base pointers
1099 */
1100 obj = radeon_fb->obj;
1101 rbo = gem_to_radeon_bo(obj);
1102 r = radeon_bo_reserve(rbo, false);
1103 if (unlikely(r != 0))
1104 return r;
1105
1106 if (atomic)
1107 fb_location = radeon_bo_gpu_offset(rbo);
1108 else {
1109 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1110 if (unlikely(r != 0)) {
1111 radeon_bo_unreserve(rbo);
1112 return -EINVAL;
1113 }
1114 }
1115
1116 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1117 radeon_bo_unreserve(rbo);
1118
1119 switch (target_fb->bits_per_pixel) {
1120 case 8:
1121 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1122 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1123 break;
1124 case 15:
1125 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1126 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1127 break;
1128 case 16:
1129 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1130 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1131 #ifdef __BIG_ENDIAN
1132 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1133 #endif
1134 break;
1135 case 24:
1136 case 32:
1137 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1138 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1139 #ifdef __BIG_ENDIAN
1140 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1141 #endif
1142 break;
1143 default:
1144 DRM_ERROR("Unsupported screen depth %d\n",
1145 target_fb->bits_per_pixel);
1146 return -EINVAL;
1147 }
1148
1149 if (tiling_flags & RADEON_TILING_MACRO) {
1150 if (rdev->family >= CHIP_CAYMAN)
1151 tmp = rdev->config.cayman.tile_config;
1152 else
1153 tmp = rdev->config.evergreen.tile_config;
1154
1155 switch ((tmp & 0xf0) >> 4) {
1156 case 0: /* 4 banks */
1157 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1158 break;
1159 case 1: /* 8 banks */
1160 default:
1161 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1162 break;
1163 case 2: /* 16 banks */
1164 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1165 break;
1166 }
1167
1168 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1169
1170 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1171 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1172 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1173 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1174 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1175 } else if (tiling_flags & RADEON_TILING_MICRO)
1176 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1177
1178 switch (radeon_crtc->crtc_id) {
1179 case 0:
1180 WREG32(AVIVO_D1VGA_CONTROL, 0);
1181 break;
1182 case 1:
1183 WREG32(AVIVO_D2VGA_CONTROL, 0);
1184 break;
1185 case 2:
1186 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1187 break;
1188 case 3:
1189 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1190 break;
1191 case 4:
1192 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1193 break;
1194 case 5:
1195 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1196 break;
1197 default:
1198 break;
1199 }
1200
1201 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1202 upper_32_bits(fb_location));
1203 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1204 upper_32_bits(fb_location));
1205 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1206 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1207 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1208 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1209 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1210 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1211
1212 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1213 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1214 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1215 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1216 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1217 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1218
1219 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1220 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1221 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1222
1223 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1224 target_fb->height);
1225 x &= ~3;
1226 y &= ~1;
1227 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1228 (x << 16) | y);
1229 viewport_w = crtc->mode.hdisplay;
1230 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1231 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1232 (viewport_w << 16) | viewport_h);
1233
1234 /* pageflip setup */
1235 /* make sure flip is at vb rather than hb */
1236 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1237 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1238 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1239
1240 /* set pageflip to happen anywhere in vblank interval */
1241 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1242
1243 if (!atomic && fb && fb != crtc->fb) {
1244 radeon_fb = to_radeon_framebuffer(fb);
1245 rbo = gem_to_radeon_bo(radeon_fb->obj);
1246 r = radeon_bo_reserve(rbo, false);
1247 if (unlikely(r != 0))
1248 return r;
1249 radeon_bo_unpin(rbo);
1250 radeon_bo_unreserve(rbo);
1251 }
1252
1253 /* Bytes per pixel may have changed */
1254 radeon_bandwidth_update(rdev);
1255
1256 return 0;
1257 }
1258
avivo_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)1259 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1260 struct drm_framebuffer *fb,
1261 int x, int y, int atomic)
1262 {
1263 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1264 struct drm_device *dev = crtc->dev;
1265 struct radeon_device *rdev = dev->dev_private;
1266 struct radeon_framebuffer *radeon_fb;
1267 struct drm_gem_object *obj;
1268 struct radeon_bo *rbo;
1269 struct drm_framebuffer *target_fb;
1270 uint64_t fb_location;
1271 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1272 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1273 u32 tmp, viewport_w, viewport_h;
1274 int r;
1275
1276 /* no fb bound */
1277 if (!atomic && !crtc->fb) {
1278 DRM_DEBUG_KMS("No FB bound\n");
1279 return 0;
1280 }
1281
1282 if (atomic) {
1283 radeon_fb = to_radeon_framebuffer(fb);
1284 target_fb = fb;
1285 }
1286 else {
1287 radeon_fb = to_radeon_framebuffer(crtc->fb);
1288 target_fb = crtc->fb;
1289 }
1290
1291 obj = radeon_fb->obj;
1292 rbo = gem_to_radeon_bo(obj);
1293 r = radeon_bo_reserve(rbo, false);
1294 if (unlikely(r != 0))
1295 return r;
1296
1297 /* If atomic, assume fb object is pinned & idle & fenced and
1298 * just update base pointers
1299 */
1300 if (atomic)
1301 fb_location = radeon_bo_gpu_offset(rbo);
1302 else {
1303 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1304 if (unlikely(r != 0)) {
1305 radeon_bo_unreserve(rbo);
1306 return -EINVAL;
1307 }
1308 }
1309 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1310 radeon_bo_unreserve(rbo);
1311
1312 switch (target_fb->bits_per_pixel) {
1313 case 8:
1314 fb_format =
1315 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1316 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1317 break;
1318 case 15:
1319 fb_format =
1320 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1321 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1322 break;
1323 case 16:
1324 fb_format =
1325 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1326 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1327 #ifdef __BIG_ENDIAN
1328 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1329 #endif
1330 break;
1331 case 24:
1332 case 32:
1333 fb_format =
1334 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1335 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1336 #ifdef __BIG_ENDIAN
1337 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1338 #endif
1339 break;
1340 default:
1341 DRM_ERROR("Unsupported screen depth %d\n",
1342 target_fb->bits_per_pixel);
1343 return -EINVAL;
1344 }
1345
1346 if (rdev->family >= CHIP_R600) {
1347 if (tiling_flags & RADEON_TILING_MACRO)
1348 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1349 else if (tiling_flags & RADEON_TILING_MICRO)
1350 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1351 } else {
1352 if (tiling_flags & RADEON_TILING_MACRO)
1353 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1354
1355 if (tiling_flags & RADEON_TILING_MICRO)
1356 fb_format |= AVIVO_D1GRPH_TILED;
1357 }
1358
1359 if (radeon_crtc->crtc_id == 0)
1360 WREG32(AVIVO_D1VGA_CONTROL, 0);
1361 else
1362 WREG32(AVIVO_D2VGA_CONTROL, 0);
1363
1364 if (rdev->family >= CHIP_RV770) {
1365 if (radeon_crtc->crtc_id) {
1366 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1367 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1368 } else {
1369 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1370 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1371 }
1372 }
1373 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1374 (u32) fb_location);
1375 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1376 radeon_crtc->crtc_offset, (u32) fb_location);
1377 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1378 if (rdev->family >= CHIP_R600)
1379 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1380
1381 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1382 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1383 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1384 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1385 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1386 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1387
1388 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1389 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1390 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1391
1392 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1393 target_fb->height);
1394 x &= ~3;
1395 y &= ~1;
1396 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1397 (x << 16) | y);
1398 viewport_w = crtc->mode.hdisplay;
1399 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1400 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1401 (viewport_w << 16) | viewport_h);
1402
1403 /* pageflip setup */
1404 /* make sure flip is at vb rather than hb */
1405 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1406 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1407 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1408
1409 /* set pageflip to happen anywhere in vblank interval */
1410 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1411
1412 if (!atomic && fb && fb != crtc->fb) {
1413 radeon_fb = to_radeon_framebuffer(fb);
1414 rbo = gem_to_radeon_bo(radeon_fb->obj);
1415 r = radeon_bo_reserve(rbo, false);
1416 if (unlikely(r != 0))
1417 return r;
1418 radeon_bo_unpin(rbo);
1419 radeon_bo_unreserve(rbo);
1420 }
1421
1422 /* Bytes per pixel may have changed */
1423 radeon_bandwidth_update(rdev);
1424
1425 return 0;
1426 }
1427
atombios_crtc_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)1428 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1429 struct drm_framebuffer *old_fb)
1430 {
1431 struct drm_device *dev = crtc->dev;
1432 struct radeon_device *rdev = dev->dev_private;
1433
1434 if (ASIC_IS_DCE4(rdev))
1435 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1436 else if (ASIC_IS_AVIVO(rdev))
1437 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1438 else
1439 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1440 }
1441
atombios_crtc_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)1442 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1443 struct drm_framebuffer *fb,
1444 int x, int y, enum mode_set_atomic state)
1445 {
1446 struct drm_device *dev = crtc->dev;
1447 struct radeon_device *rdev = dev->dev_private;
1448
1449 if (ASIC_IS_DCE4(rdev))
1450 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1451 else if (ASIC_IS_AVIVO(rdev))
1452 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1453 else
1454 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1455 }
1456
1457 /* properly set additional regs when using atombios */
radeon_legacy_atom_fixup(struct drm_crtc * crtc)1458 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1459 {
1460 struct drm_device *dev = crtc->dev;
1461 struct radeon_device *rdev = dev->dev_private;
1462 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1463 u32 disp_merge_cntl;
1464
1465 switch (radeon_crtc->crtc_id) {
1466 case 0:
1467 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1468 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1469 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1470 break;
1471 case 1:
1472 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1473 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1474 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1475 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1476 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1477 break;
1478 }
1479 }
1480
radeon_atom_pick_pll(struct drm_crtc * crtc)1481 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1482 {
1483 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1484 struct drm_device *dev = crtc->dev;
1485 struct radeon_device *rdev = dev->dev_private;
1486 struct drm_encoder *test_encoder;
1487 struct drm_crtc *test_crtc;
1488 uint32_t pll_in_use = 0;
1489
1490 if (ASIC_IS_DCE61(rdev)) {
1491 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1492 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1493 struct radeon_encoder *test_radeon_encoder =
1494 to_radeon_encoder(test_encoder);
1495 struct radeon_encoder_atom_dig *dig =
1496 test_radeon_encoder->enc_priv;
1497
1498 if ((test_radeon_encoder->encoder_id ==
1499 ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1500 (dig->linkb == false)) /* UNIPHY A uses PPLL2 */
1501 return ATOM_PPLL2;
1502 }
1503 }
1504 /* UNIPHY B/C/D/E/F */
1505 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1506 struct radeon_crtc *radeon_test_crtc;
1507
1508 if (crtc == test_crtc)
1509 continue;
1510
1511 radeon_test_crtc = to_radeon_crtc(test_crtc);
1512 if ((radeon_test_crtc->pll_id == ATOM_PPLL0) ||
1513 (radeon_test_crtc->pll_id == ATOM_PPLL1))
1514 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1515 }
1516 if (!(pll_in_use & 4))
1517 return ATOM_PPLL0;
1518 return ATOM_PPLL1;
1519 } else if (ASIC_IS_DCE4(rdev)) {
1520 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1521 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1522 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1523 * depending on the asic:
1524 * DCE4: PPLL or ext clock
1525 * DCE5: DCPLL or ext clock
1526 *
1527 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1528 * PPLL/DCPLL programming and only program the DP DTO for the
1529 * crtc virtual pixel clock.
1530 */
1531 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1532 if (rdev->clock.dp_extclk)
1533 return ATOM_PPLL_INVALID;
1534 else if (ASIC_IS_DCE6(rdev))
1535 return ATOM_PPLL0;
1536 else if (ASIC_IS_DCE5(rdev))
1537 return ATOM_DCPLL;
1538 }
1539 }
1540 }
1541
1542 /* otherwise, pick one of the plls */
1543 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1544 struct radeon_crtc *radeon_test_crtc;
1545
1546 if (crtc == test_crtc)
1547 continue;
1548
1549 radeon_test_crtc = to_radeon_crtc(test_crtc);
1550 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1551 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1552 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1553 }
1554 if (!(pll_in_use & 1))
1555 return ATOM_PPLL1;
1556 return ATOM_PPLL2;
1557 } else
1558 return radeon_crtc->crtc_id;
1559
1560 }
1561
radeon_atom_disp_eng_pll_init(struct radeon_device * rdev)1562 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1563 {
1564 /* always set DCPLL */
1565 if (ASIC_IS_DCE6(rdev))
1566 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1567 else if (ASIC_IS_DCE4(rdev)) {
1568 struct radeon_atom_ss ss;
1569 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1570 ASIC_INTERNAL_SS_ON_DCPLL,
1571 rdev->clock.default_dispclk);
1572 if (ss_enabled)
1573 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1574 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1575 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1576 if (ss_enabled)
1577 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1578 }
1579
1580 }
1581
atombios_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)1582 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1583 struct drm_display_mode *mode,
1584 struct drm_display_mode *adjusted_mode,
1585 int x, int y, struct drm_framebuffer *old_fb)
1586 {
1587 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1588 struct drm_device *dev = crtc->dev;
1589 struct radeon_device *rdev = dev->dev_private;
1590 struct drm_encoder *encoder;
1591 bool is_tvcv = false;
1592
1593 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1594 /* find tv std */
1595 if (encoder->crtc == crtc) {
1596 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1597 if (radeon_encoder->active_device &
1598 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1599 is_tvcv = true;
1600 }
1601 }
1602
1603 atombios_crtc_set_pll(crtc, adjusted_mode);
1604
1605 if (ASIC_IS_DCE4(rdev))
1606 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1607 else if (ASIC_IS_AVIVO(rdev)) {
1608 if (is_tvcv)
1609 atombios_crtc_set_timing(crtc, adjusted_mode);
1610 else
1611 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1612 } else {
1613 atombios_crtc_set_timing(crtc, adjusted_mode);
1614 if (radeon_crtc->crtc_id == 0)
1615 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1616 radeon_legacy_atom_fixup(crtc);
1617 }
1618 atombios_crtc_set_base(crtc, x, y, old_fb);
1619 atombios_overscan_setup(crtc, mode, adjusted_mode);
1620 atombios_scaler_setup(crtc);
1621 return 0;
1622 }
1623
atombios_crtc_mode_fixup(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1624 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1625 struct drm_display_mode *mode,
1626 struct drm_display_mode *adjusted_mode)
1627 {
1628 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1629 return false;
1630 return true;
1631 }
1632
atombios_crtc_prepare(struct drm_crtc * crtc)1633 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1634 {
1635 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1636 struct drm_device *dev = crtc->dev;
1637 struct radeon_device *rdev = dev->dev_private;
1638
1639 radeon_crtc->in_mode_set = true;
1640 /* pick pll */
1641 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1642
1643 /* disable crtc pair power gating before programming */
1644 if (ASIC_IS_DCE6(rdev))
1645 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1646
1647 atombios_lock_crtc(crtc, ATOM_ENABLE);
1648 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1649 }
1650
atombios_crtc_commit(struct drm_crtc * crtc)1651 static void atombios_crtc_commit(struct drm_crtc *crtc)
1652 {
1653 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1654
1655 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1656 atombios_lock_crtc(crtc, ATOM_DISABLE);
1657 radeon_crtc->in_mode_set = false;
1658 }
1659
atombios_crtc_disable(struct drm_crtc * crtc)1660 static void atombios_crtc_disable(struct drm_crtc *crtc)
1661 {
1662 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1663 struct drm_device *dev = crtc->dev;
1664 struct radeon_device *rdev = dev->dev_private;
1665 struct radeon_atom_ss ss;
1666 int i;
1667
1668 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1669 if (ASIC_IS_DCE6(rdev))
1670 atombios_powergate_crtc(crtc, ATOM_ENABLE);
1671
1672 for (i = 0; i < rdev->num_crtc; i++) {
1673 if (rdev->mode_info.crtcs[i] &&
1674 rdev->mode_info.crtcs[i]->enabled &&
1675 i != radeon_crtc->crtc_id &&
1676 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1677 /* one other crtc is using this pll don't turn
1678 * off the pll
1679 */
1680 goto done;
1681 }
1682 }
1683
1684 switch (radeon_crtc->pll_id) {
1685 case ATOM_PPLL1:
1686 case ATOM_PPLL2:
1687 /* disable the ppll */
1688 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1689 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1690 break;
1691 case ATOM_PPLL0:
1692 /* disable the ppll */
1693 if (ASIC_IS_DCE61(rdev))
1694 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1695 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1696 break;
1697 default:
1698 break;
1699 }
1700 done:
1701 radeon_crtc->pll_id = -1;
1702 }
1703
1704 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1705 .dpms = atombios_crtc_dpms,
1706 .mode_fixup = atombios_crtc_mode_fixup,
1707 .mode_set = atombios_crtc_mode_set,
1708 .mode_set_base = atombios_crtc_set_base,
1709 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1710 .prepare = atombios_crtc_prepare,
1711 .commit = atombios_crtc_commit,
1712 .load_lut = radeon_crtc_load_lut,
1713 .disable = atombios_crtc_disable,
1714 };
1715
radeon_atombios_init_crtc(struct drm_device * dev,struct radeon_crtc * radeon_crtc)1716 void radeon_atombios_init_crtc(struct drm_device *dev,
1717 struct radeon_crtc *radeon_crtc)
1718 {
1719 struct radeon_device *rdev = dev->dev_private;
1720
1721 if (ASIC_IS_DCE4(rdev)) {
1722 switch (radeon_crtc->crtc_id) {
1723 case 0:
1724 default:
1725 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1726 break;
1727 case 1:
1728 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1729 break;
1730 case 2:
1731 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1732 break;
1733 case 3:
1734 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1735 break;
1736 case 4:
1737 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1738 break;
1739 case 5:
1740 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1741 break;
1742 }
1743 } else {
1744 if (radeon_crtc->crtc_id == 1)
1745 radeon_crtc->crtc_offset =
1746 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1747 else
1748 radeon_crtc->crtc_offset = 0;
1749 }
1750 radeon_crtc->pll_id = -1;
1751 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1752 }
1753