1 /*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38
radeon_encoder_is_digital(struct drm_encoder * encoder)39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
40 {
41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42 switch (radeon_encoder->encoder_id) {
43 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49 case ENCODER_OBJECT_ID_INTERNAL_DDI:
50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
54 return true;
55 default:
56 return false;
57 }
58 }
59
radeon_atom_mode_fixup(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)60 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
61 struct drm_display_mode *mode,
62 struct drm_display_mode *adjusted_mode)
63 {
64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65 struct drm_device *dev = encoder->dev;
66 struct radeon_device *rdev = dev->dev_private;
67
68 /* set the active encoder to connector routing */
69 radeon_encoder_set_active_device(encoder);
70 drm_mode_set_crtcinfo(adjusted_mode, 0);
71
72 /* hw bug */
73 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
74 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
75 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
76
77 /* get the native mode for LVDS */
78 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
79 radeon_panel_mode_fixup(encoder, adjusted_mode);
80
81 /* get the native mode for TV */
82 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
83 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
84 if (tv_dac) {
85 if (tv_dac->tv_std == TV_STD_NTSC ||
86 tv_dac->tv_std == TV_STD_NTSC_J ||
87 tv_dac->tv_std == TV_STD_PAL_M)
88 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
89 else
90 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
91 }
92 }
93
94 if (ASIC_IS_DCE3(rdev) &&
95 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
96 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
97 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
98 radeon_dp_set_link_config(connector, adjusted_mode);
99 }
100
101 return true;
102 }
103
104 static void
atombios_dac_setup(struct drm_encoder * encoder,int action)105 atombios_dac_setup(struct drm_encoder *encoder, int action)
106 {
107 struct drm_device *dev = encoder->dev;
108 struct radeon_device *rdev = dev->dev_private;
109 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
110 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
111 int index = 0;
112 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
113
114 memset(&args, 0, sizeof(args));
115
116 switch (radeon_encoder->encoder_id) {
117 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
118 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
119 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
120 break;
121 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
122 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
123 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
124 break;
125 }
126
127 args.ucAction = action;
128
129 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
130 args.ucDacStandard = ATOM_DAC1_PS2;
131 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
132 args.ucDacStandard = ATOM_DAC1_CV;
133 else {
134 switch (dac_info->tv_std) {
135 case TV_STD_PAL:
136 case TV_STD_PAL_M:
137 case TV_STD_SCART_PAL:
138 case TV_STD_SECAM:
139 case TV_STD_PAL_CN:
140 args.ucDacStandard = ATOM_DAC1_PAL;
141 break;
142 case TV_STD_NTSC:
143 case TV_STD_NTSC_J:
144 case TV_STD_PAL_60:
145 default:
146 args.ucDacStandard = ATOM_DAC1_NTSC;
147 break;
148 }
149 }
150 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
151
152 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
153
154 }
155
156 static void
atombios_tv_setup(struct drm_encoder * encoder,int action)157 atombios_tv_setup(struct drm_encoder *encoder, int action)
158 {
159 struct drm_device *dev = encoder->dev;
160 struct radeon_device *rdev = dev->dev_private;
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 TV_ENCODER_CONTROL_PS_ALLOCATION args;
163 int index = 0;
164 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
165
166 memset(&args, 0, sizeof(args));
167
168 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
169
170 args.sTVEncoder.ucAction = action;
171
172 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
173 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
174 else {
175 switch (dac_info->tv_std) {
176 case TV_STD_NTSC:
177 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
178 break;
179 case TV_STD_PAL:
180 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
181 break;
182 case TV_STD_PAL_M:
183 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
184 break;
185 case TV_STD_PAL_60:
186 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
187 break;
188 case TV_STD_NTSC_J:
189 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
190 break;
191 case TV_STD_SCART_PAL:
192 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
193 break;
194 case TV_STD_SECAM:
195 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
196 break;
197 case TV_STD_PAL_CN:
198 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
199 break;
200 default:
201 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
202 break;
203 }
204 }
205
206 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
207
208 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
209
210 }
211
212 union dvo_encoder_control {
213 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
214 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
215 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
216 };
217
218 void
atombios_dvo_setup(struct drm_encoder * encoder,int action)219 atombios_dvo_setup(struct drm_encoder *encoder, int action)
220 {
221 struct drm_device *dev = encoder->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
224 union dvo_encoder_control args;
225 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
226 uint8_t frev, crev;
227
228 memset(&args, 0, sizeof(args));
229
230 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
231 return;
232
233 /* some R4xx chips have the wrong frev */
234 if (rdev->family <= CHIP_RV410)
235 frev = 1;
236
237 switch (frev) {
238 case 1:
239 switch (crev) {
240 case 1:
241 /* R4xx, R5xx */
242 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
243
244 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
245 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
246
247 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
248 break;
249 case 2:
250 /* RS600/690/740 */
251 args.dvo.sDVOEncoder.ucAction = action;
252 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
253 /* DFP1, CRT1, TV1 depending on the type of port */
254 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
255
256 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
257 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
258 break;
259 case 3:
260 /* R6xx */
261 args.dvo_v3.ucAction = action;
262 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
263 args.dvo_v3.ucDVOConfig = 0; /* XXX */
264 break;
265 default:
266 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
267 break;
268 }
269 break;
270 default:
271 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
272 break;
273 }
274
275 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
276 }
277
278 union lvds_encoder_control {
279 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
280 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
281 };
282
283 void
atombios_digital_setup(struct drm_encoder * encoder,int action)284 atombios_digital_setup(struct drm_encoder *encoder, int action)
285 {
286 struct drm_device *dev = encoder->dev;
287 struct radeon_device *rdev = dev->dev_private;
288 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
289 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
290 union lvds_encoder_control args;
291 int index = 0;
292 int hdmi_detected = 0;
293 uint8_t frev, crev;
294
295 if (!dig)
296 return;
297
298 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
299 hdmi_detected = 1;
300
301 memset(&args, 0, sizeof(args));
302
303 switch (radeon_encoder->encoder_id) {
304 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
305 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
306 break;
307 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
308 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
309 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
310 break;
311 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
312 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
313 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
314 else
315 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
316 break;
317 }
318
319 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
320 return;
321
322 switch (frev) {
323 case 1:
324 case 2:
325 switch (crev) {
326 case 1:
327 args.v1.ucMisc = 0;
328 args.v1.ucAction = action;
329 if (hdmi_detected)
330 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
331 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
332 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
333 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
334 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
335 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
336 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
337 } else {
338 if (dig->linkb)
339 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
340 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
341 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
342 /*if (pScrn->rgbBits == 8) */
343 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
344 }
345 break;
346 case 2:
347 case 3:
348 args.v2.ucMisc = 0;
349 args.v2.ucAction = action;
350 if (crev == 3) {
351 if (dig->coherent_mode)
352 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
353 }
354 if (hdmi_detected)
355 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
356 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
357 args.v2.ucTruncate = 0;
358 args.v2.ucSpatial = 0;
359 args.v2.ucTemporal = 0;
360 args.v2.ucFRC = 0;
361 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
362 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
363 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
364 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
365 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
366 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
367 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
368 }
369 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
370 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
371 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
372 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
373 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
374 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
375 }
376 } else {
377 if (dig->linkb)
378 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
379 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
380 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
381 }
382 break;
383 default:
384 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
385 break;
386 }
387 break;
388 default:
389 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
390 break;
391 }
392
393 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
394 }
395
396 int
atombios_get_encoder_mode(struct drm_encoder * encoder)397 atombios_get_encoder_mode(struct drm_encoder *encoder)
398 {
399 struct drm_device *dev = encoder->dev;
400 struct radeon_device *rdev = dev->dev_private;
401 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
402 struct drm_connector *connector;
403 struct radeon_connector *radeon_connector;
404 struct radeon_connector_atom_dig *dig_connector;
405
406 /* dp bridges are always DP */
407 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
408 return ATOM_ENCODER_MODE_DP;
409
410 /* DVO is always DVO */
411 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
412 return ATOM_ENCODER_MODE_DVO;
413
414 connector = radeon_get_connector_for_encoder(encoder);
415 /* if we don't have an active device yet, just use one of
416 * the connectors tied to the encoder.
417 */
418 if (!connector)
419 connector = radeon_get_connector_for_encoder_init(encoder);
420 radeon_connector = to_radeon_connector(connector);
421
422 switch (connector->connector_type) {
423 case DRM_MODE_CONNECTOR_DVII:
424 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
425 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
426 radeon_audio &&
427 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
428 return ATOM_ENCODER_MODE_HDMI;
429 else if (radeon_connector->use_digital)
430 return ATOM_ENCODER_MODE_DVI;
431 else
432 return ATOM_ENCODER_MODE_CRT;
433 break;
434 case DRM_MODE_CONNECTOR_DVID:
435 case DRM_MODE_CONNECTOR_HDMIA:
436 default:
437 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
438 radeon_audio &&
439 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
440 return ATOM_ENCODER_MODE_HDMI;
441 else
442 return ATOM_ENCODER_MODE_DVI;
443 break;
444 case DRM_MODE_CONNECTOR_LVDS:
445 return ATOM_ENCODER_MODE_LVDS;
446 break;
447 case DRM_MODE_CONNECTOR_DisplayPort:
448 dig_connector = radeon_connector->con_priv;
449 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
450 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
451 return ATOM_ENCODER_MODE_DP;
452 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
453 radeon_audio &&
454 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
455 return ATOM_ENCODER_MODE_HDMI;
456 else
457 return ATOM_ENCODER_MODE_DVI;
458 break;
459 case DRM_MODE_CONNECTOR_eDP:
460 return ATOM_ENCODER_MODE_DP;
461 case DRM_MODE_CONNECTOR_DVIA:
462 case DRM_MODE_CONNECTOR_VGA:
463 return ATOM_ENCODER_MODE_CRT;
464 break;
465 case DRM_MODE_CONNECTOR_Composite:
466 case DRM_MODE_CONNECTOR_SVIDEO:
467 case DRM_MODE_CONNECTOR_9PinDIN:
468 /* fix me */
469 return ATOM_ENCODER_MODE_TV;
470 /*return ATOM_ENCODER_MODE_CV;*/
471 break;
472 }
473 }
474
475 /*
476 * DIG Encoder/Transmitter Setup
477 *
478 * DCE 3.0/3.1
479 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
480 * Supports up to 3 digital outputs
481 * - 2 DIG encoder blocks.
482 * DIG1 can drive UNIPHY link A or link B
483 * DIG2 can drive UNIPHY link B or LVTMA
484 *
485 * DCE 3.2
486 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
487 * Supports up to 5 digital outputs
488 * - 2 DIG encoder blocks.
489 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
490 *
491 * DCE 4.0/5.0/6.0
492 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
493 * Supports up to 6 digital outputs
494 * - 6 DIG encoder blocks.
495 * - DIG to PHY mapping is hardcoded
496 * DIG1 drives UNIPHY0 link A, A+B
497 * DIG2 drives UNIPHY0 link B
498 * DIG3 drives UNIPHY1 link A, A+B
499 * DIG4 drives UNIPHY1 link B
500 * DIG5 drives UNIPHY2 link A, A+B
501 * DIG6 drives UNIPHY2 link B
502 *
503 * DCE 4.1
504 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
505 * Supports up to 6 digital outputs
506 * - 2 DIG encoder blocks.
507 * llano
508 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
509 * ontario
510 * DIG1 drives UNIPHY0/1/2 link A
511 * DIG2 drives UNIPHY0/1/2 link B
512 *
513 * Routing
514 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
515 * Examples:
516 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
517 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
518 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
519 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
520 */
521
522 union dig_encoder_control {
523 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
524 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
525 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
526 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
527 };
528
529 void
atombios_dig_encoder_setup(struct drm_encoder * encoder,int action,int panel_mode)530 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
531 {
532 struct drm_device *dev = encoder->dev;
533 struct radeon_device *rdev = dev->dev_private;
534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
535 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
536 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
537 union dig_encoder_control args;
538 int index = 0;
539 uint8_t frev, crev;
540 int dp_clock = 0;
541 int dp_lane_count = 0;
542 int hpd_id = RADEON_HPD_NONE;
543 int bpc = 8;
544
545 if (connector) {
546 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
547 struct radeon_connector_atom_dig *dig_connector =
548 radeon_connector->con_priv;
549
550 dp_clock = dig_connector->dp_clock;
551 dp_lane_count = dig_connector->dp_lane_count;
552 hpd_id = radeon_connector->hpd.hpd;
553 /* bpc = connector->display_info.bpc; */
554 }
555
556 /* no dig encoder assigned */
557 if (dig->dig_encoder == -1)
558 return;
559
560 memset(&args, 0, sizeof(args));
561
562 if (ASIC_IS_DCE4(rdev))
563 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
564 else {
565 if (dig->dig_encoder)
566 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
567 else
568 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
569 }
570
571 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
572 return;
573
574 switch (frev) {
575 case 1:
576 switch (crev) {
577 case 1:
578 args.v1.ucAction = action;
579 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
580 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
581 args.v3.ucPanelMode = panel_mode;
582 else
583 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
584
585 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
586 args.v1.ucLaneNum = dp_lane_count;
587 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
588 args.v1.ucLaneNum = 8;
589 else
590 args.v1.ucLaneNum = 4;
591
592 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
593 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
594 switch (radeon_encoder->encoder_id) {
595 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
596 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
597 break;
598 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
599 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
600 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
601 break;
602 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
603 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
604 break;
605 }
606 if (dig->linkb)
607 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
608 else
609 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
610 break;
611 case 2:
612 case 3:
613 args.v3.ucAction = action;
614 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
615 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
616 args.v3.ucPanelMode = panel_mode;
617 else
618 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
619
620 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
621 args.v3.ucLaneNum = dp_lane_count;
622 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
623 args.v3.ucLaneNum = 8;
624 else
625 args.v3.ucLaneNum = 4;
626
627 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
628 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
629 args.v3.acConfig.ucDigSel = dig->dig_encoder;
630 switch (bpc) {
631 case 0:
632 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
633 break;
634 case 6:
635 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
636 break;
637 case 8:
638 default:
639 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
640 break;
641 case 10:
642 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
643 break;
644 case 12:
645 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
646 break;
647 case 16:
648 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
649 break;
650 }
651 break;
652 case 4:
653 args.v4.ucAction = action;
654 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
655 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
656 args.v4.ucPanelMode = panel_mode;
657 else
658 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
659
660 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
661 args.v4.ucLaneNum = dp_lane_count;
662 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
663 args.v4.ucLaneNum = 8;
664 else
665 args.v4.ucLaneNum = 4;
666
667 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
668 if (dp_clock == 270000)
669 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
670 else if (dp_clock == 540000)
671 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
672 }
673 args.v4.acConfig.ucDigSel = dig->dig_encoder;
674 switch (bpc) {
675 case 0:
676 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
677 break;
678 case 6:
679 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
680 break;
681 case 8:
682 default:
683 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
684 break;
685 case 10:
686 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
687 break;
688 case 12:
689 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
690 break;
691 case 16:
692 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
693 break;
694 }
695 if (hpd_id == RADEON_HPD_NONE)
696 args.v4.ucHPD_ID = 0;
697 else
698 args.v4.ucHPD_ID = hpd_id + 1;
699 break;
700 default:
701 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
702 break;
703 }
704 break;
705 default:
706 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
707 break;
708 }
709
710 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
711
712 }
713
714 union dig_transmitter_control {
715 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
716 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
717 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
718 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
719 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
720 };
721
722 void
atombios_dig_transmitter_setup(struct drm_encoder * encoder,int action,uint8_t lane_num,uint8_t lane_set)723 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
724 {
725 struct drm_device *dev = encoder->dev;
726 struct radeon_device *rdev = dev->dev_private;
727 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
728 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
729 struct drm_connector *connector;
730 union dig_transmitter_control args;
731 int index = 0;
732 uint8_t frev, crev;
733 bool is_dp = false;
734 int pll_id = 0;
735 int dp_clock = 0;
736 int dp_lane_count = 0;
737 int connector_object_id = 0;
738 int igp_lane_info = 0;
739 int dig_encoder = dig->dig_encoder;
740 int hpd_id = RADEON_HPD_NONE;
741
742 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
743 connector = radeon_get_connector_for_encoder_init(encoder);
744 /* just needed to avoid bailing in the encoder check. the encoder
745 * isn't used for init
746 */
747 dig_encoder = 0;
748 } else
749 connector = radeon_get_connector_for_encoder(encoder);
750
751 if (connector) {
752 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
753 struct radeon_connector_atom_dig *dig_connector =
754 radeon_connector->con_priv;
755
756 hpd_id = radeon_connector->hpd.hpd;
757 dp_clock = dig_connector->dp_clock;
758 dp_lane_count = dig_connector->dp_lane_count;
759 connector_object_id =
760 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
761 igp_lane_info = dig_connector->igp_lane_info;
762 }
763
764 if (encoder->crtc) {
765 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
766 pll_id = radeon_crtc->pll_id;
767 }
768
769 /* no dig encoder assigned */
770 if (dig_encoder == -1)
771 return;
772
773 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
774 is_dp = true;
775
776 memset(&args, 0, sizeof(args));
777
778 switch (radeon_encoder->encoder_id) {
779 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
780 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
781 break;
782 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
783 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
784 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
785 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
786 break;
787 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
788 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
789 break;
790 }
791
792 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
793 return;
794
795 switch (frev) {
796 case 1:
797 switch (crev) {
798 case 1:
799 args.v1.ucAction = action;
800 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
801 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
802 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
803 args.v1.asMode.ucLaneSel = lane_num;
804 args.v1.asMode.ucLaneSet = lane_set;
805 } else {
806 if (is_dp)
807 args.v1.usPixelClock =
808 cpu_to_le16(dp_clock / 10);
809 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
810 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
811 else
812 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
813 }
814
815 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
816
817 if (dig_encoder)
818 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
819 else
820 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
821
822 if ((rdev->flags & RADEON_IS_IGP) &&
823 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
824 if (is_dp ||
825 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
826 if (igp_lane_info & 0x1)
827 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
828 else if (igp_lane_info & 0x2)
829 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
830 else if (igp_lane_info & 0x4)
831 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
832 else if (igp_lane_info & 0x8)
833 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
834 } else {
835 if (igp_lane_info & 0x3)
836 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
837 else if (igp_lane_info & 0xc)
838 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
839 }
840 }
841
842 if (dig->linkb)
843 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
844 else
845 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
846
847 if (is_dp)
848 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
849 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
850 if (dig->coherent_mode)
851 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
852 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
853 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
854 }
855 break;
856 case 2:
857 args.v2.ucAction = action;
858 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
859 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
860 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
861 args.v2.asMode.ucLaneSel = lane_num;
862 args.v2.asMode.ucLaneSet = lane_set;
863 } else {
864 if (is_dp)
865 args.v2.usPixelClock =
866 cpu_to_le16(dp_clock / 10);
867 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
868 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
869 else
870 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
871 }
872
873 args.v2.acConfig.ucEncoderSel = dig_encoder;
874 if (dig->linkb)
875 args.v2.acConfig.ucLinkSel = 1;
876
877 switch (radeon_encoder->encoder_id) {
878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
879 args.v2.acConfig.ucTransmitterSel = 0;
880 break;
881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
882 args.v2.acConfig.ucTransmitterSel = 1;
883 break;
884 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
885 args.v2.acConfig.ucTransmitterSel = 2;
886 break;
887 }
888
889 if (is_dp) {
890 args.v2.acConfig.fCoherentMode = 1;
891 args.v2.acConfig.fDPConnector = 1;
892 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
893 if (dig->coherent_mode)
894 args.v2.acConfig.fCoherentMode = 1;
895 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
896 args.v2.acConfig.fDualLinkConnector = 1;
897 }
898 break;
899 case 3:
900 args.v3.ucAction = action;
901 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
902 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
903 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
904 args.v3.asMode.ucLaneSel = lane_num;
905 args.v3.asMode.ucLaneSet = lane_set;
906 } else {
907 if (is_dp)
908 args.v3.usPixelClock =
909 cpu_to_le16(dp_clock / 10);
910 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
911 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
912 else
913 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
914 }
915
916 if (is_dp)
917 args.v3.ucLaneNum = dp_lane_count;
918 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
919 args.v3.ucLaneNum = 8;
920 else
921 args.v3.ucLaneNum = 4;
922
923 if (dig->linkb)
924 args.v3.acConfig.ucLinkSel = 1;
925 if (dig_encoder & 1)
926 args.v3.acConfig.ucEncoderSel = 1;
927
928 /* Select the PLL for the PHY
929 * DP PHY should be clocked from external src if there is
930 * one.
931 */
932 /* On DCE4, if there is an external clock, it generates the DP ref clock */
933 if (is_dp && rdev->clock.dp_extclk)
934 args.v3.acConfig.ucRefClkSource = 2; /* external src */
935 else
936 args.v3.acConfig.ucRefClkSource = pll_id;
937
938 switch (radeon_encoder->encoder_id) {
939 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
940 args.v3.acConfig.ucTransmitterSel = 0;
941 break;
942 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
943 args.v3.acConfig.ucTransmitterSel = 1;
944 break;
945 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
946 args.v3.acConfig.ucTransmitterSel = 2;
947 break;
948 }
949
950 if (is_dp)
951 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
952 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
953 if (dig->coherent_mode)
954 args.v3.acConfig.fCoherentMode = 1;
955 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
956 args.v3.acConfig.fDualLinkConnector = 1;
957 }
958 break;
959 case 4:
960 args.v4.ucAction = action;
961 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
962 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
963 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
964 args.v4.asMode.ucLaneSel = lane_num;
965 args.v4.asMode.ucLaneSet = lane_set;
966 } else {
967 if (is_dp)
968 args.v4.usPixelClock =
969 cpu_to_le16(dp_clock / 10);
970 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
971 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
972 else
973 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
974 }
975
976 if (is_dp)
977 args.v4.ucLaneNum = dp_lane_count;
978 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
979 args.v4.ucLaneNum = 8;
980 else
981 args.v4.ucLaneNum = 4;
982
983 if (dig->linkb)
984 args.v4.acConfig.ucLinkSel = 1;
985 if (dig_encoder & 1)
986 args.v4.acConfig.ucEncoderSel = 1;
987
988 /* Select the PLL for the PHY
989 * DP PHY should be clocked from external src if there is
990 * one.
991 */
992 /* On DCE5 DCPLL usually generates the DP ref clock */
993 if (is_dp) {
994 if (rdev->clock.dp_extclk)
995 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
996 else
997 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
998 } else
999 args.v4.acConfig.ucRefClkSource = pll_id;
1000
1001 switch (radeon_encoder->encoder_id) {
1002 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1003 args.v4.acConfig.ucTransmitterSel = 0;
1004 break;
1005 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1006 args.v4.acConfig.ucTransmitterSel = 1;
1007 break;
1008 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1009 args.v4.acConfig.ucTransmitterSel = 2;
1010 break;
1011 }
1012
1013 if (is_dp)
1014 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1015 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1016 if (dig->coherent_mode)
1017 args.v4.acConfig.fCoherentMode = 1;
1018 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1019 args.v4.acConfig.fDualLinkConnector = 1;
1020 }
1021 break;
1022 case 5:
1023 args.v5.ucAction = action;
1024 if (is_dp)
1025 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1026 else
1027 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1028
1029 switch (radeon_encoder->encoder_id) {
1030 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1031 if (dig->linkb)
1032 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1033 else
1034 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1035 break;
1036 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1037 if (dig->linkb)
1038 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1039 else
1040 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1041 break;
1042 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1043 if (dig->linkb)
1044 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1045 else
1046 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1047 break;
1048 }
1049 if (is_dp)
1050 args.v5.ucLaneNum = dp_lane_count;
1051 else if (radeon_encoder->pixel_clock > 165000)
1052 args.v5.ucLaneNum = 8;
1053 else
1054 args.v5.ucLaneNum = 4;
1055 args.v5.ucConnObjId = connector_object_id;
1056 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1057
1058 if (is_dp && rdev->clock.dp_extclk)
1059 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1060 else
1061 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1062
1063 if (is_dp)
1064 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1065 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1066 if (dig->coherent_mode)
1067 args.v5.asConfig.ucCoherentMode = 1;
1068 }
1069 if (hpd_id == RADEON_HPD_NONE)
1070 args.v5.asConfig.ucHPDSel = 0;
1071 else
1072 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1073 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1074 args.v5.ucDPLaneSet = lane_set;
1075 break;
1076 default:
1077 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1078 break;
1079 }
1080 break;
1081 default:
1082 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1083 break;
1084 }
1085
1086 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1087 }
1088
1089 bool
atombios_set_edp_panel_power(struct drm_connector * connector,int action)1090 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1091 {
1092 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1093 struct drm_device *dev = radeon_connector->base.dev;
1094 struct radeon_device *rdev = dev->dev_private;
1095 union dig_transmitter_control args;
1096 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1097 uint8_t frev, crev;
1098
1099 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1100 goto done;
1101
1102 if (!ASIC_IS_DCE4(rdev))
1103 goto done;
1104
1105 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1106 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1107 goto done;
1108
1109 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1110 goto done;
1111
1112 memset(&args, 0, sizeof(args));
1113
1114 args.v1.ucAction = action;
1115
1116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1117
1118 /* wait for the panel to power up */
1119 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1120 int i;
1121
1122 for (i = 0; i < 300; i++) {
1123 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1124 return true;
1125 mdelay(1);
1126 }
1127 return false;
1128 }
1129 done:
1130 return true;
1131 }
1132
1133 union external_encoder_control {
1134 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1135 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1136 };
1137
1138 static void
atombios_external_encoder_setup(struct drm_encoder * encoder,struct drm_encoder * ext_encoder,int action)1139 atombios_external_encoder_setup(struct drm_encoder *encoder,
1140 struct drm_encoder *ext_encoder,
1141 int action)
1142 {
1143 struct drm_device *dev = encoder->dev;
1144 struct radeon_device *rdev = dev->dev_private;
1145 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1146 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1147 union external_encoder_control args;
1148 struct drm_connector *connector;
1149 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1150 u8 frev, crev;
1151 int dp_clock = 0;
1152 int dp_lane_count = 0;
1153 int connector_object_id = 0;
1154 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1155 int bpc = 8;
1156
1157 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1158 connector = radeon_get_connector_for_encoder_init(encoder);
1159 else
1160 connector = radeon_get_connector_for_encoder(encoder);
1161
1162 if (connector) {
1163 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1164 struct radeon_connector_atom_dig *dig_connector =
1165 radeon_connector->con_priv;
1166
1167 dp_clock = dig_connector->dp_clock;
1168 dp_lane_count = dig_connector->dp_lane_count;
1169 connector_object_id =
1170 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1171 /* bpc = connector->display_info.bpc; */
1172 }
1173
1174 memset(&args, 0, sizeof(args));
1175
1176 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1177 return;
1178
1179 switch (frev) {
1180 case 1:
1181 /* no params on frev 1 */
1182 break;
1183 case 2:
1184 switch (crev) {
1185 case 1:
1186 case 2:
1187 args.v1.sDigEncoder.ucAction = action;
1188 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1189 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1190
1191 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1192 if (dp_clock == 270000)
1193 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1194 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1195 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1196 args.v1.sDigEncoder.ucLaneNum = 8;
1197 else
1198 args.v1.sDigEncoder.ucLaneNum = 4;
1199 break;
1200 case 3:
1201 args.v3.sExtEncoder.ucAction = action;
1202 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1203 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1204 else
1205 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1206 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1207
1208 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1209 if (dp_clock == 270000)
1210 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1211 else if (dp_clock == 540000)
1212 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1213 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1214 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1215 args.v3.sExtEncoder.ucLaneNum = 8;
1216 else
1217 args.v3.sExtEncoder.ucLaneNum = 4;
1218 switch (ext_enum) {
1219 case GRAPH_OBJECT_ENUM_ID1:
1220 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1221 break;
1222 case GRAPH_OBJECT_ENUM_ID2:
1223 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1224 break;
1225 case GRAPH_OBJECT_ENUM_ID3:
1226 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1227 break;
1228 }
1229 switch (bpc) {
1230 case 0:
1231 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1232 break;
1233 case 6:
1234 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1235 break;
1236 case 8:
1237 default:
1238 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1239 break;
1240 case 10:
1241 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1242 break;
1243 case 12:
1244 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1245 break;
1246 case 16:
1247 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1248 break;
1249 }
1250 break;
1251 default:
1252 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1253 return;
1254 }
1255 break;
1256 default:
1257 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1258 return;
1259 }
1260 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1261 }
1262
1263 static void
atombios_yuv_setup(struct drm_encoder * encoder,bool enable)1264 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1265 {
1266 struct drm_device *dev = encoder->dev;
1267 struct radeon_device *rdev = dev->dev_private;
1268 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1270 ENABLE_YUV_PS_ALLOCATION args;
1271 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1272 uint32_t temp, reg;
1273
1274 memset(&args, 0, sizeof(args));
1275
1276 if (rdev->family >= CHIP_R600)
1277 reg = R600_BIOS_3_SCRATCH;
1278 else
1279 reg = RADEON_BIOS_3_SCRATCH;
1280
1281 /* XXX: fix up scratch reg handling */
1282 temp = RREG32(reg);
1283 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1284 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1285 (radeon_crtc->crtc_id << 18)));
1286 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1287 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1288 else
1289 WREG32(reg, 0);
1290
1291 if (enable)
1292 args.ucEnable = ATOM_ENABLE;
1293 args.ucCRTC = radeon_crtc->crtc_id;
1294
1295 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1296
1297 WREG32(reg, temp);
1298 }
1299
1300 static void
radeon_atom_encoder_dpms_avivo(struct drm_encoder * encoder,int mode)1301 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1302 {
1303 struct drm_device *dev = encoder->dev;
1304 struct radeon_device *rdev = dev->dev_private;
1305 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1306 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1307 int index = 0;
1308
1309 memset(&args, 0, sizeof(args));
1310
1311 switch (radeon_encoder->encoder_id) {
1312 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1314 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1315 break;
1316 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1317 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1318 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1319 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1320 break;
1321 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1322 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1323 break;
1324 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1325 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1326 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1327 else
1328 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1329 break;
1330 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1331 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1332 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1333 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1334 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1335 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1336 else
1337 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1338 break;
1339 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1340 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1341 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1342 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1343 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1344 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1345 else
1346 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1347 break;
1348 default:
1349 return;
1350 }
1351
1352 switch (mode) {
1353 case DRM_MODE_DPMS_ON:
1354 args.ucAction = ATOM_ENABLE;
1355 /* workaround for DVOOutputControl on some RS690 systems */
1356 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1357 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1358 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1359 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1360 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1361 } else
1362 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1363 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1364 args.ucAction = ATOM_LCD_BLON;
1365 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1366 }
1367 break;
1368 case DRM_MODE_DPMS_STANDBY:
1369 case DRM_MODE_DPMS_SUSPEND:
1370 case DRM_MODE_DPMS_OFF:
1371 args.ucAction = ATOM_DISABLE;
1372 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1373 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1374 args.ucAction = ATOM_LCD_BLOFF;
1375 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1376 }
1377 break;
1378 }
1379 }
1380
1381 static void
radeon_atom_encoder_dpms_dig(struct drm_encoder * encoder,int mode)1382 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1383 {
1384 struct drm_device *dev = encoder->dev;
1385 struct radeon_device *rdev = dev->dev_private;
1386 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1387 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1388 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1389 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1390 struct radeon_connector *radeon_connector = NULL;
1391 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1392
1393 if (connector) {
1394 radeon_connector = to_radeon_connector(connector);
1395 radeon_dig_connector = radeon_connector->con_priv;
1396 }
1397
1398 switch (mode) {
1399 case DRM_MODE_DPMS_ON:
1400 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1401 if (!connector)
1402 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1403 else
1404 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1405
1406 /* setup and enable the encoder */
1407 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1408 atombios_dig_encoder_setup(encoder,
1409 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1410 dig->panel_mode);
1411 if (ext_encoder) {
1412 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1413 atombios_external_encoder_setup(encoder, ext_encoder,
1414 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1415 }
1416 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1417 } else if (ASIC_IS_DCE4(rdev)) {
1418 /* setup and enable the encoder */
1419 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1420 /* enable the transmitter */
1421 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1422 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1423 } else {
1424 /* setup and enable the encoder and transmitter */
1425 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1426 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1427 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1428 /* some dce3.x boards have a bug in their transmitter control table.
1429 * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1430 * does the same thing and more.
1431 */
1432 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1433 (rdev->family != CHIP_RS880))
1434 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1435 }
1436 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1437 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1438 atombios_set_edp_panel_power(connector,
1439 ATOM_TRANSMITTER_ACTION_POWER_ON);
1440 radeon_dig_connector->edp_on = true;
1441 }
1442 radeon_dp_link_train(encoder, connector);
1443 if (ASIC_IS_DCE4(rdev))
1444 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1445 }
1446 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1447 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1448 break;
1449 case DRM_MODE_DPMS_STANDBY:
1450 case DRM_MODE_DPMS_SUSPEND:
1451 case DRM_MODE_DPMS_OFF:
1452 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1453 /* disable the transmitter */
1454 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1455 } else if (ASIC_IS_DCE4(rdev)) {
1456 /* disable the transmitter */
1457 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1458 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1459 } else {
1460 /* disable the encoder and transmitter */
1461 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1462 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1463 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1464 }
1465 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1466 if (ASIC_IS_DCE4(rdev))
1467 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1468 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1469 atombios_set_edp_panel_power(connector,
1470 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1471 radeon_dig_connector->edp_on = false;
1472 }
1473 }
1474 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1475 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1476 break;
1477 }
1478 }
1479
1480 static void
radeon_atom_encoder_dpms_ext(struct drm_encoder * encoder,struct drm_encoder * ext_encoder,int mode)1481 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1482 struct drm_encoder *ext_encoder,
1483 int mode)
1484 {
1485 struct drm_device *dev = encoder->dev;
1486 struct radeon_device *rdev = dev->dev_private;
1487
1488 switch (mode) {
1489 case DRM_MODE_DPMS_ON:
1490 default:
1491 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1492 atombios_external_encoder_setup(encoder, ext_encoder,
1493 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1494 atombios_external_encoder_setup(encoder, ext_encoder,
1495 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1496 } else
1497 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1498 break;
1499 case DRM_MODE_DPMS_STANDBY:
1500 case DRM_MODE_DPMS_SUSPEND:
1501 case DRM_MODE_DPMS_OFF:
1502 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1503 atombios_external_encoder_setup(encoder, ext_encoder,
1504 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1505 atombios_external_encoder_setup(encoder, ext_encoder,
1506 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1507 } else
1508 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1509 break;
1510 }
1511 }
1512
1513 static void
radeon_atom_encoder_dpms(struct drm_encoder * encoder,int mode)1514 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1515 {
1516 struct drm_device *dev = encoder->dev;
1517 struct radeon_device *rdev = dev->dev_private;
1518 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1519 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1520
1521 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1522 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1523 radeon_encoder->active_device);
1524 switch (radeon_encoder->encoder_id) {
1525 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1526 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1527 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1528 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1529 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1530 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1531 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1532 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1533 radeon_atom_encoder_dpms_avivo(encoder, mode);
1534 break;
1535 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1536 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1537 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1538 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1539 radeon_atom_encoder_dpms_dig(encoder, mode);
1540 break;
1541 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1542 if (ASIC_IS_DCE5(rdev)) {
1543 switch (mode) {
1544 case DRM_MODE_DPMS_ON:
1545 atombios_dvo_setup(encoder, ATOM_ENABLE);
1546 break;
1547 case DRM_MODE_DPMS_STANDBY:
1548 case DRM_MODE_DPMS_SUSPEND:
1549 case DRM_MODE_DPMS_OFF:
1550 atombios_dvo_setup(encoder, ATOM_DISABLE);
1551 break;
1552 }
1553 } else if (ASIC_IS_DCE3(rdev))
1554 radeon_atom_encoder_dpms_dig(encoder, mode);
1555 else
1556 radeon_atom_encoder_dpms_avivo(encoder, mode);
1557 break;
1558 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1559 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1560 if (ASIC_IS_DCE5(rdev)) {
1561 switch (mode) {
1562 case DRM_MODE_DPMS_ON:
1563 atombios_dac_setup(encoder, ATOM_ENABLE);
1564 break;
1565 case DRM_MODE_DPMS_STANDBY:
1566 case DRM_MODE_DPMS_SUSPEND:
1567 case DRM_MODE_DPMS_OFF:
1568 atombios_dac_setup(encoder, ATOM_DISABLE);
1569 break;
1570 }
1571 } else
1572 radeon_atom_encoder_dpms_avivo(encoder, mode);
1573 break;
1574 default:
1575 return;
1576 }
1577
1578 if (ext_encoder)
1579 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1580
1581 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1582
1583 }
1584
1585 union crtc_source_param {
1586 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1587 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1588 };
1589
1590 static void
atombios_set_encoder_crtc_source(struct drm_encoder * encoder)1591 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1592 {
1593 struct drm_device *dev = encoder->dev;
1594 struct radeon_device *rdev = dev->dev_private;
1595 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1596 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1597 union crtc_source_param args;
1598 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1599 uint8_t frev, crev;
1600 struct radeon_encoder_atom_dig *dig;
1601
1602 memset(&args, 0, sizeof(args));
1603
1604 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1605 return;
1606
1607 switch (frev) {
1608 case 1:
1609 switch (crev) {
1610 case 1:
1611 default:
1612 if (ASIC_IS_AVIVO(rdev))
1613 args.v1.ucCRTC = radeon_crtc->crtc_id;
1614 else {
1615 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1616 args.v1.ucCRTC = radeon_crtc->crtc_id;
1617 } else {
1618 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1619 }
1620 }
1621 switch (radeon_encoder->encoder_id) {
1622 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1623 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1624 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1625 break;
1626 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1627 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1628 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1629 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1630 else
1631 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1632 break;
1633 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1634 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1635 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1636 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1637 break;
1638 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1639 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1640 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1641 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1642 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1643 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1644 else
1645 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1646 break;
1647 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1648 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1649 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1650 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1651 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1652 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1653 else
1654 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1655 break;
1656 }
1657 break;
1658 case 2:
1659 args.v2.ucCRTC = radeon_crtc->crtc_id;
1660 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1661 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1662
1663 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1664 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1665 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1666 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1667 else
1668 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1669 } else
1670 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1671 switch (radeon_encoder->encoder_id) {
1672 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1673 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1674 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1675 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1676 dig = radeon_encoder->enc_priv;
1677 switch (dig->dig_encoder) {
1678 case 0:
1679 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1680 break;
1681 case 1:
1682 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1683 break;
1684 case 2:
1685 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1686 break;
1687 case 3:
1688 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1689 break;
1690 case 4:
1691 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1692 break;
1693 case 5:
1694 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1695 break;
1696 }
1697 break;
1698 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1699 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1700 break;
1701 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1702 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1703 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1704 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1705 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1706 else
1707 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1708 break;
1709 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1710 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1711 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1712 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1713 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1714 else
1715 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1716 break;
1717 }
1718 break;
1719 }
1720 break;
1721 default:
1722 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1723 return;
1724 }
1725
1726 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1727
1728 /* update scratch regs with new routing */
1729 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1730 }
1731
1732 static void
atombios_apply_encoder_quirks(struct drm_encoder * encoder,struct drm_display_mode * mode)1733 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1734 struct drm_display_mode *mode)
1735 {
1736 struct drm_device *dev = encoder->dev;
1737 struct radeon_device *rdev = dev->dev_private;
1738 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1739 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1740
1741 /* Funky macbooks */
1742 if ((dev->pdev->device == 0x71C5) &&
1743 (dev->pdev->subsystem_vendor == 0x106b) &&
1744 (dev->pdev->subsystem_device == 0x0080)) {
1745 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1746 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1747
1748 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1749 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1750
1751 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1752 }
1753 }
1754
1755 /* set scaler clears this on some chips */
1756 if (ASIC_IS_AVIVO(rdev) &&
1757 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1758 if (ASIC_IS_DCE4(rdev)) {
1759 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1760 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1761 EVERGREEN_INTERLEAVE_EN);
1762 else
1763 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1764 } else {
1765 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1766 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1767 AVIVO_D1MODE_INTERLEAVE_EN);
1768 else
1769 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1770 }
1771 }
1772 }
1773
radeon_atom_pick_dig_encoder(struct drm_encoder * encoder)1774 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1775 {
1776 struct drm_device *dev = encoder->dev;
1777 struct radeon_device *rdev = dev->dev_private;
1778 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1779 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1780 struct drm_encoder *test_encoder;
1781 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1782 uint32_t dig_enc_in_use = 0;
1783
1784 if (ASIC_IS_DCE6(rdev)) {
1785 /* DCE6 */
1786 switch (radeon_encoder->encoder_id) {
1787 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1788 if (dig->linkb)
1789 return 1;
1790 else
1791 return 0;
1792 break;
1793 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1794 if (dig->linkb)
1795 return 3;
1796 else
1797 return 2;
1798 break;
1799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1800 if (dig->linkb)
1801 return 5;
1802 else
1803 return 4;
1804 break;
1805 }
1806 } else if (ASIC_IS_DCE4(rdev)) {
1807 /* DCE4/5 */
1808 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
1809 /* ontario follows DCE4 */
1810 if (rdev->family == CHIP_PALM) {
1811 if (dig->linkb)
1812 return 1;
1813 else
1814 return 0;
1815 } else
1816 /* llano follows DCE3.2 */
1817 return radeon_crtc->crtc_id;
1818 } else {
1819 switch (radeon_encoder->encoder_id) {
1820 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1821 if (dig->linkb)
1822 return 1;
1823 else
1824 return 0;
1825 break;
1826 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1827 if (dig->linkb)
1828 return 3;
1829 else
1830 return 2;
1831 break;
1832 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1833 if (dig->linkb)
1834 return 5;
1835 else
1836 return 4;
1837 break;
1838 }
1839 }
1840 }
1841
1842 /* on DCE32 and encoder can driver any block so just crtc id */
1843 if (ASIC_IS_DCE32(rdev)) {
1844 return radeon_crtc->crtc_id;
1845 }
1846
1847 /* on DCE3 - LVTMA can only be driven by DIGB */
1848 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1849 struct radeon_encoder *radeon_test_encoder;
1850
1851 if (encoder == test_encoder)
1852 continue;
1853
1854 if (!radeon_encoder_is_digital(test_encoder))
1855 continue;
1856
1857 radeon_test_encoder = to_radeon_encoder(test_encoder);
1858 dig = radeon_test_encoder->enc_priv;
1859
1860 if (dig->dig_encoder >= 0)
1861 dig_enc_in_use |= (1 << dig->dig_encoder);
1862 }
1863
1864 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1865 if (dig_enc_in_use & 0x2)
1866 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1867 return 1;
1868 }
1869 if (!(dig_enc_in_use & 1))
1870 return 0;
1871 return 1;
1872 }
1873
1874 /* This only needs to be called once at startup */
1875 void
radeon_atom_encoder_init(struct radeon_device * rdev)1876 radeon_atom_encoder_init(struct radeon_device *rdev)
1877 {
1878 struct drm_device *dev = rdev->ddev;
1879 struct drm_encoder *encoder;
1880
1881 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1882 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1883 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1884
1885 switch (radeon_encoder->encoder_id) {
1886 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1887 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1888 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1889 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1890 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1891 break;
1892 default:
1893 break;
1894 }
1895
1896 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
1897 atombios_external_encoder_setup(encoder, ext_encoder,
1898 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1899 }
1900 }
1901
1902 static void
radeon_atom_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1903 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1904 struct drm_display_mode *mode,
1905 struct drm_display_mode *adjusted_mode)
1906 {
1907 struct drm_device *dev = encoder->dev;
1908 struct radeon_device *rdev = dev->dev_private;
1909 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1910
1911 radeon_encoder->pixel_clock = adjusted_mode->clock;
1912
1913 /* need to call this here rather than in prepare() since we need some crtc info */
1914 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1915
1916 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1917 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1918 atombios_yuv_setup(encoder, true);
1919 else
1920 atombios_yuv_setup(encoder, false);
1921 }
1922
1923 switch (radeon_encoder->encoder_id) {
1924 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1925 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1926 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1927 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1928 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1929 break;
1930 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1931 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1932 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1933 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1934 /* handled in dpms */
1935 break;
1936 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1937 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1938 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1939 atombios_dvo_setup(encoder, ATOM_ENABLE);
1940 break;
1941 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1942 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1943 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1944 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1945 atombios_dac_setup(encoder, ATOM_ENABLE);
1946 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1947 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1948 atombios_tv_setup(encoder, ATOM_ENABLE);
1949 else
1950 atombios_tv_setup(encoder, ATOM_DISABLE);
1951 }
1952 break;
1953 }
1954
1955 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1956
1957 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1958 r600_hdmi_enable(encoder);
1959 r600_hdmi_setmode(encoder, adjusted_mode);
1960 }
1961 }
1962
1963 static bool
atombios_dac_load_detect(struct drm_encoder * encoder,struct drm_connector * connector)1964 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1965 {
1966 struct drm_device *dev = encoder->dev;
1967 struct radeon_device *rdev = dev->dev_private;
1968 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1969 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1970
1971 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1972 ATOM_DEVICE_CV_SUPPORT |
1973 ATOM_DEVICE_CRT_SUPPORT)) {
1974 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1975 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1976 uint8_t frev, crev;
1977
1978 memset(&args, 0, sizeof(args));
1979
1980 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1981 return false;
1982
1983 args.sDacload.ucMisc = 0;
1984
1985 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1986 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1987 args.sDacload.ucDacType = ATOM_DAC_A;
1988 else
1989 args.sDacload.ucDacType = ATOM_DAC_B;
1990
1991 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1992 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1993 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1994 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1995 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1996 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1997 if (crev >= 3)
1998 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1999 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2000 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2001 if (crev >= 3)
2002 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2003 }
2004
2005 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2006
2007 return true;
2008 } else
2009 return false;
2010 }
2011
2012 static enum drm_connector_status
radeon_atom_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)2013 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2014 {
2015 struct drm_device *dev = encoder->dev;
2016 struct radeon_device *rdev = dev->dev_private;
2017 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2018 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2019 uint32_t bios_0_scratch;
2020
2021 if (!atombios_dac_load_detect(encoder, connector)) {
2022 DRM_DEBUG_KMS("detect returned false \n");
2023 return connector_status_unknown;
2024 }
2025
2026 if (rdev->family >= CHIP_R600)
2027 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2028 else
2029 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2030
2031 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2032 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2033 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2034 return connector_status_connected;
2035 }
2036 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2037 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2038 return connector_status_connected;
2039 }
2040 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2041 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2042 return connector_status_connected;
2043 }
2044 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2045 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2046 return connector_status_connected; /* CTV */
2047 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2048 return connector_status_connected; /* STV */
2049 }
2050 return connector_status_disconnected;
2051 }
2052
2053 static enum drm_connector_status
radeon_atom_dig_detect(struct drm_encoder * encoder,struct drm_connector * connector)2054 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2055 {
2056 struct drm_device *dev = encoder->dev;
2057 struct radeon_device *rdev = dev->dev_private;
2058 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2059 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2060 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2061 u32 bios_0_scratch;
2062
2063 if (!ASIC_IS_DCE4(rdev))
2064 return connector_status_unknown;
2065
2066 if (!ext_encoder)
2067 return connector_status_unknown;
2068
2069 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2070 return connector_status_unknown;
2071
2072 /* load detect on the dp bridge */
2073 atombios_external_encoder_setup(encoder, ext_encoder,
2074 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2075
2076 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2077
2078 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2079 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2080 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2081 return connector_status_connected;
2082 }
2083 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2084 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2085 return connector_status_connected;
2086 }
2087 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2088 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2089 return connector_status_connected;
2090 }
2091 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2092 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2093 return connector_status_connected; /* CTV */
2094 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2095 return connector_status_connected; /* STV */
2096 }
2097 return connector_status_disconnected;
2098 }
2099
2100 void
radeon_atom_ext_encoder_setup_ddc(struct drm_encoder * encoder)2101 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2102 {
2103 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2104
2105 if (ext_encoder)
2106 /* ddc_setup on the dp bridge */
2107 atombios_external_encoder_setup(encoder, ext_encoder,
2108 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2109
2110 }
2111
radeon_atom_encoder_prepare(struct drm_encoder * encoder)2112 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2113 {
2114 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2115 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2116
2117 if ((radeon_encoder->active_device &
2118 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2119 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2120 ENCODER_OBJECT_ID_NONE)) {
2121 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2122 if (dig)
2123 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2124 }
2125
2126 radeon_atom_output_lock(encoder, true);
2127
2128 if (connector) {
2129 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2130
2131 /* select the clock/data port if it uses a router */
2132 if (radeon_connector->router.cd_valid)
2133 radeon_router_select_cd_port(radeon_connector);
2134
2135 /* turn eDP panel on for mode set */
2136 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2137 atombios_set_edp_panel_power(connector,
2138 ATOM_TRANSMITTER_ACTION_POWER_ON);
2139 }
2140
2141 /* this is needed for the pll/ss setup to work correctly in some cases */
2142 atombios_set_encoder_crtc_source(encoder);
2143 }
2144
radeon_atom_encoder_commit(struct drm_encoder * encoder)2145 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2146 {
2147 /* need to call this here as we need the crtc set up */
2148 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2149 radeon_atom_output_lock(encoder, false);
2150 }
2151
radeon_atom_encoder_disable(struct drm_encoder * encoder)2152 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2153 {
2154 struct drm_device *dev = encoder->dev;
2155 struct radeon_device *rdev = dev->dev_private;
2156 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2157 struct radeon_encoder_atom_dig *dig;
2158
2159 /* check for pre-DCE3 cards with shared encoders;
2160 * can't really use the links individually, so don't disable
2161 * the encoder if it's in use by another connector
2162 */
2163 if (!ASIC_IS_DCE3(rdev)) {
2164 struct drm_encoder *other_encoder;
2165 struct radeon_encoder *other_radeon_encoder;
2166
2167 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2168 other_radeon_encoder = to_radeon_encoder(other_encoder);
2169 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2170 drm_helper_encoder_in_use(other_encoder))
2171 goto disable_done;
2172 }
2173 }
2174
2175 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2176
2177 switch (radeon_encoder->encoder_id) {
2178 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2179 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2180 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2181 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2182 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2183 break;
2184 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2185 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2186 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2187 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2188 /* handled in dpms */
2189 break;
2190 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2191 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2192 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2193 atombios_dvo_setup(encoder, ATOM_DISABLE);
2194 break;
2195 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2196 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2197 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2198 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2199 atombios_dac_setup(encoder, ATOM_DISABLE);
2200 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2201 atombios_tv_setup(encoder, ATOM_DISABLE);
2202 break;
2203 }
2204
2205 disable_done:
2206 if (radeon_encoder_is_digital(encoder)) {
2207 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2208 r600_hdmi_disable(encoder);
2209 dig = radeon_encoder->enc_priv;
2210 dig->dig_encoder = -1;
2211 }
2212 radeon_encoder->active_device = 0;
2213 }
2214
2215 /* these are handled by the primary encoders */
radeon_atom_ext_prepare(struct drm_encoder * encoder)2216 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2217 {
2218
2219 }
2220
radeon_atom_ext_commit(struct drm_encoder * encoder)2221 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2222 {
2223
2224 }
2225
2226 static void
radeon_atom_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2227 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2228 struct drm_display_mode *mode,
2229 struct drm_display_mode *adjusted_mode)
2230 {
2231
2232 }
2233
radeon_atom_ext_disable(struct drm_encoder * encoder)2234 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2235 {
2236
2237 }
2238
2239 static void
radeon_atom_ext_dpms(struct drm_encoder * encoder,int mode)2240 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2241 {
2242
2243 }
2244
radeon_atom_ext_mode_fixup(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2245 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2246 struct drm_display_mode *mode,
2247 struct drm_display_mode *adjusted_mode)
2248 {
2249 return true;
2250 }
2251
2252 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2253 .dpms = radeon_atom_ext_dpms,
2254 .mode_fixup = radeon_atom_ext_mode_fixup,
2255 .prepare = radeon_atom_ext_prepare,
2256 .mode_set = radeon_atom_ext_mode_set,
2257 .commit = radeon_atom_ext_commit,
2258 .disable = radeon_atom_ext_disable,
2259 /* no detect for TMDS/LVDS yet */
2260 };
2261
2262 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2263 .dpms = radeon_atom_encoder_dpms,
2264 .mode_fixup = radeon_atom_mode_fixup,
2265 .prepare = radeon_atom_encoder_prepare,
2266 .mode_set = radeon_atom_encoder_mode_set,
2267 .commit = radeon_atom_encoder_commit,
2268 .disable = radeon_atom_encoder_disable,
2269 .detect = radeon_atom_dig_detect,
2270 };
2271
2272 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2273 .dpms = radeon_atom_encoder_dpms,
2274 .mode_fixup = radeon_atom_mode_fixup,
2275 .prepare = radeon_atom_encoder_prepare,
2276 .mode_set = radeon_atom_encoder_mode_set,
2277 .commit = radeon_atom_encoder_commit,
2278 .detect = radeon_atom_dac_detect,
2279 };
2280
radeon_enc_destroy(struct drm_encoder * encoder)2281 void radeon_enc_destroy(struct drm_encoder *encoder)
2282 {
2283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2284 kfree(radeon_encoder->enc_priv);
2285 drm_encoder_cleanup(encoder);
2286 kfree(radeon_encoder);
2287 }
2288
2289 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2290 .destroy = radeon_enc_destroy,
2291 };
2292
2293 struct radeon_encoder_atom_dac *
radeon_atombios_set_dac_info(struct radeon_encoder * radeon_encoder)2294 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2295 {
2296 struct drm_device *dev = radeon_encoder->base.dev;
2297 struct radeon_device *rdev = dev->dev_private;
2298 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2299
2300 if (!dac)
2301 return NULL;
2302
2303 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2304 return dac;
2305 }
2306
2307 struct radeon_encoder_atom_dig *
radeon_atombios_set_dig_info(struct radeon_encoder * radeon_encoder)2308 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2309 {
2310 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2311 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2312
2313 if (!dig)
2314 return NULL;
2315
2316 /* coherent mode by default */
2317 dig->coherent_mode = true;
2318 dig->dig_encoder = -1;
2319
2320 if (encoder_enum == 2)
2321 dig->linkb = true;
2322 else
2323 dig->linkb = false;
2324
2325 return dig;
2326 }
2327
2328 void
radeon_add_atom_encoder(struct drm_device * dev,uint32_t encoder_enum,uint32_t supported_device,u16 caps)2329 radeon_add_atom_encoder(struct drm_device *dev,
2330 uint32_t encoder_enum,
2331 uint32_t supported_device,
2332 u16 caps)
2333 {
2334 struct radeon_device *rdev = dev->dev_private;
2335 struct drm_encoder *encoder;
2336 struct radeon_encoder *radeon_encoder;
2337
2338 /* see if we already added it */
2339 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2340 radeon_encoder = to_radeon_encoder(encoder);
2341 if (radeon_encoder->encoder_enum == encoder_enum) {
2342 radeon_encoder->devices |= supported_device;
2343 return;
2344 }
2345
2346 }
2347
2348 /* add a new one */
2349 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2350 if (!radeon_encoder)
2351 return;
2352
2353 encoder = &radeon_encoder->base;
2354 switch (rdev->num_crtc) {
2355 case 1:
2356 encoder->possible_crtcs = 0x1;
2357 break;
2358 case 2:
2359 default:
2360 encoder->possible_crtcs = 0x3;
2361 break;
2362 case 4:
2363 encoder->possible_crtcs = 0xf;
2364 break;
2365 case 6:
2366 encoder->possible_crtcs = 0x3f;
2367 break;
2368 }
2369
2370 radeon_encoder->enc_priv = NULL;
2371
2372 radeon_encoder->encoder_enum = encoder_enum;
2373 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2374 radeon_encoder->devices = supported_device;
2375 radeon_encoder->rmx_type = RMX_OFF;
2376 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2377 radeon_encoder->is_ext_encoder = false;
2378 radeon_encoder->caps = caps;
2379
2380 switch (radeon_encoder->encoder_id) {
2381 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2382 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2383 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2384 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2385 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2386 radeon_encoder->rmx_type = RMX_FULL;
2387 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2388 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2389 } else {
2390 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2391 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2392 }
2393 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2394 break;
2395 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2396 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2397 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2398 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2399 break;
2400 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2401 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2402 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2403 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2404 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2405 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2406 break;
2407 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2408 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2409 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2410 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2411 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2412 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2413 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2414 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2415 radeon_encoder->rmx_type = RMX_FULL;
2416 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2417 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2418 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2419 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2420 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2421 } else {
2422 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2423 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2424 }
2425 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2426 break;
2427 case ENCODER_OBJECT_ID_SI170B:
2428 case ENCODER_OBJECT_ID_CH7303:
2429 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2430 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2431 case ENCODER_OBJECT_ID_TITFP513:
2432 case ENCODER_OBJECT_ID_VT1623:
2433 case ENCODER_OBJECT_ID_HDMI_SI1930:
2434 case ENCODER_OBJECT_ID_TRAVIS:
2435 case ENCODER_OBJECT_ID_NUTMEG:
2436 /* these are handled by the primary encoders */
2437 radeon_encoder->is_ext_encoder = true;
2438 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2439 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2440 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2441 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2442 else
2443 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2444 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2445 break;
2446 }
2447 }
2448