1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
11
12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33 */
34
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
43 #include <linux/io.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
47
48 #include "b43.h"
49 #include "main.h"
50 #include "debugfs.h"
51 #include "phy_common.h"
52 #include "phy_g.h"
53 #include "phy_n.h"
54 #include "dma.h"
55 #include "pio.h"
56 #include "sysfs.h"
57 #include "xmit.h"
58 #include "lo.h"
59 #include "pcmcia.h"
60 #include "sdio.h"
61 #include <linux/mmc/sdio_func.h>
62
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
70
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
78
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
107
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
115
116 #ifdef CONFIG_B43_BCMA
117 static const struct bcma_device_id b43_bcma_tbl[] = {
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
119 #ifdef CONFIG_B43_BCMA_EXTRA
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
122 #endif
123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
124 BCMA_CORETABLE_END
125 };
126 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
127 #endif
128
129 #ifdef CONFIG_B43_SSB
130 static const struct ssb_device_id b43_ssb_tbl[] = {
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
141 SSB_DEVTABLE_END
142 };
143 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
144 #endif
145
146 /* Channel and ratetables are shared for all devices.
147 * They can't be const, because ieee80211 puts some precalculated
148 * data in there. This data is the same for all devices, so we don't
149 * get concurrency issues */
150 #define RATETAB_ENT(_rateid, _flags) \
151 { \
152 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
153 .hw_value = (_rateid), \
154 .flags = (_flags), \
155 }
156
157 /*
158 * NOTE: When changing this, sync with xmit.c's
159 * b43_plcp_get_bitrate_idx_* functions!
160 */
161 static struct ieee80211_rate __b43_ratetable[] = {
162 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
163 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
164 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
165 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
166 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
172 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
174 };
175
176 #define b43_a_ratetable (__b43_ratetable + 4)
177 #define b43_a_ratetable_size 8
178 #define b43_b_ratetable (__b43_ratetable + 0)
179 #define b43_b_ratetable_size 4
180 #define b43_g_ratetable (__b43_ratetable + 0)
181 #define b43_g_ratetable_size 12
182
183 #define CHAN4G(_channel, _freq, _flags) { \
184 .band = IEEE80211_BAND_2GHZ, \
185 .center_freq = (_freq), \
186 .hw_value = (_channel), \
187 .flags = (_flags), \
188 .max_antenna_gain = 0, \
189 .max_power = 30, \
190 }
191 static struct ieee80211_channel b43_2ghz_chantable[] = {
192 CHAN4G(1, 2412, 0),
193 CHAN4G(2, 2417, 0),
194 CHAN4G(3, 2422, 0),
195 CHAN4G(4, 2427, 0),
196 CHAN4G(5, 2432, 0),
197 CHAN4G(6, 2437, 0),
198 CHAN4G(7, 2442, 0),
199 CHAN4G(8, 2447, 0),
200 CHAN4G(9, 2452, 0),
201 CHAN4G(10, 2457, 0),
202 CHAN4G(11, 2462, 0),
203 CHAN4G(12, 2467, 0),
204 CHAN4G(13, 2472, 0),
205 CHAN4G(14, 2484, 0),
206 };
207 #undef CHAN4G
208
209 #define CHAN5G(_channel, _flags) { \
210 .band = IEEE80211_BAND_5GHZ, \
211 .center_freq = 5000 + (5 * (_channel)), \
212 .hw_value = (_channel), \
213 .flags = (_flags), \
214 .max_antenna_gain = 0, \
215 .max_power = 30, \
216 }
217 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
218 CHAN5G(32, 0), CHAN5G(34, 0),
219 CHAN5G(36, 0), CHAN5G(38, 0),
220 CHAN5G(40, 0), CHAN5G(42, 0),
221 CHAN5G(44, 0), CHAN5G(46, 0),
222 CHAN5G(48, 0), CHAN5G(50, 0),
223 CHAN5G(52, 0), CHAN5G(54, 0),
224 CHAN5G(56, 0), CHAN5G(58, 0),
225 CHAN5G(60, 0), CHAN5G(62, 0),
226 CHAN5G(64, 0), CHAN5G(66, 0),
227 CHAN5G(68, 0), CHAN5G(70, 0),
228 CHAN5G(72, 0), CHAN5G(74, 0),
229 CHAN5G(76, 0), CHAN5G(78, 0),
230 CHAN5G(80, 0), CHAN5G(82, 0),
231 CHAN5G(84, 0), CHAN5G(86, 0),
232 CHAN5G(88, 0), CHAN5G(90, 0),
233 CHAN5G(92, 0), CHAN5G(94, 0),
234 CHAN5G(96, 0), CHAN5G(98, 0),
235 CHAN5G(100, 0), CHAN5G(102, 0),
236 CHAN5G(104, 0), CHAN5G(106, 0),
237 CHAN5G(108, 0), CHAN5G(110, 0),
238 CHAN5G(112, 0), CHAN5G(114, 0),
239 CHAN5G(116, 0), CHAN5G(118, 0),
240 CHAN5G(120, 0), CHAN5G(122, 0),
241 CHAN5G(124, 0), CHAN5G(126, 0),
242 CHAN5G(128, 0), CHAN5G(130, 0),
243 CHAN5G(132, 0), CHAN5G(134, 0),
244 CHAN5G(136, 0), CHAN5G(138, 0),
245 CHAN5G(140, 0), CHAN5G(142, 0),
246 CHAN5G(144, 0), CHAN5G(145, 0),
247 CHAN5G(146, 0), CHAN5G(147, 0),
248 CHAN5G(148, 0), CHAN5G(149, 0),
249 CHAN5G(150, 0), CHAN5G(151, 0),
250 CHAN5G(152, 0), CHAN5G(153, 0),
251 CHAN5G(154, 0), CHAN5G(155, 0),
252 CHAN5G(156, 0), CHAN5G(157, 0),
253 CHAN5G(158, 0), CHAN5G(159, 0),
254 CHAN5G(160, 0), CHAN5G(161, 0),
255 CHAN5G(162, 0), CHAN5G(163, 0),
256 CHAN5G(164, 0), CHAN5G(165, 0),
257 CHAN5G(166, 0), CHAN5G(168, 0),
258 CHAN5G(170, 0), CHAN5G(172, 0),
259 CHAN5G(174, 0), CHAN5G(176, 0),
260 CHAN5G(178, 0), CHAN5G(180, 0),
261 CHAN5G(182, 0), CHAN5G(184, 0),
262 CHAN5G(186, 0), CHAN5G(188, 0),
263 CHAN5G(190, 0), CHAN5G(192, 0),
264 CHAN5G(194, 0), CHAN5G(196, 0),
265 CHAN5G(198, 0), CHAN5G(200, 0),
266 CHAN5G(202, 0), CHAN5G(204, 0),
267 CHAN5G(206, 0), CHAN5G(208, 0),
268 CHAN5G(210, 0), CHAN5G(212, 0),
269 CHAN5G(214, 0), CHAN5G(216, 0),
270 CHAN5G(218, 0), CHAN5G(220, 0),
271 CHAN5G(222, 0), CHAN5G(224, 0),
272 CHAN5G(226, 0), CHAN5G(228, 0),
273 };
274
275 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
276 CHAN5G(34, 0), CHAN5G(36, 0),
277 CHAN5G(38, 0), CHAN5G(40, 0),
278 CHAN5G(42, 0), CHAN5G(44, 0),
279 CHAN5G(46, 0), CHAN5G(48, 0),
280 CHAN5G(52, 0), CHAN5G(56, 0),
281 CHAN5G(60, 0), CHAN5G(64, 0),
282 CHAN5G(100, 0), CHAN5G(104, 0),
283 CHAN5G(108, 0), CHAN5G(112, 0),
284 CHAN5G(116, 0), CHAN5G(120, 0),
285 CHAN5G(124, 0), CHAN5G(128, 0),
286 CHAN5G(132, 0), CHAN5G(136, 0),
287 CHAN5G(140, 0), CHAN5G(149, 0),
288 CHAN5G(153, 0), CHAN5G(157, 0),
289 CHAN5G(161, 0), CHAN5G(165, 0),
290 CHAN5G(184, 0), CHAN5G(188, 0),
291 CHAN5G(192, 0), CHAN5G(196, 0),
292 CHAN5G(200, 0), CHAN5G(204, 0),
293 CHAN5G(208, 0), CHAN5G(212, 0),
294 CHAN5G(216, 0),
295 };
296 #undef CHAN5G
297
298 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
299 .band = IEEE80211_BAND_5GHZ,
300 .channels = b43_5ghz_nphy_chantable,
301 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
302 .bitrates = b43_a_ratetable,
303 .n_bitrates = b43_a_ratetable_size,
304 };
305
306 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
307 .band = IEEE80211_BAND_5GHZ,
308 .channels = b43_5ghz_aphy_chantable,
309 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
310 .bitrates = b43_a_ratetable,
311 .n_bitrates = b43_a_ratetable_size,
312 };
313
314 static struct ieee80211_supported_band b43_band_2GHz = {
315 .band = IEEE80211_BAND_2GHZ,
316 .channels = b43_2ghz_chantable,
317 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
318 .bitrates = b43_g_ratetable,
319 .n_bitrates = b43_g_ratetable_size,
320 };
321
322 static void b43_wireless_core_exit(struct b43_wldev *dev);
323 static int b43_wireless_core_init(struct b43_wldev *dev);
324 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
325 static int b43_wireless_core_start(struct b43_wldev *dev);
326 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
327 struct ieee80211_vif *vif,
328 struct ieee80211_bss_conf *conf,
329 u32 changed);
330
b43_ratelimit(struct b43_wl * wl)331 static int b43_ratelimit(struct b43_wl *wl)
332 {
333 if (!wl || !wl->current_dev)
334 return 1;
335 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
336 return 1;
337 /* We are up and running.
338 * Ratelimit the messages to avoid DoS over the net. */
339 return net_ratelimit();
340 }
341
b43info(struct b43_wl * wl,const char * fmt,...)342 void b43info(struct b43_wl *wl, const char *fmt, ...)
343 {
344 struct va_format vaf;
345 va_list args;
346
347 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
348 return;
349 if (!b43_ratelimit(wl))
350 return;
351
352 va_start(args, fmt);
353
354 vaf.fmt = fmt;
355 vaf.va = &args;
356
357 printk(KERN_INFO "b43-%s: %pV",
358 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
359
360 va_end(args);
361 }
362
b43err(struct b43_wl * wl,const char * fmt,...)363 void b43err(struct b43_wl *wl, const char *fmt, ...)
364 {
365 struct va_format vaf;
366 va_list args;
367
368 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
369 return;
370 if (!b43_ratelimit(wl))
371 return;
372
373 va_start(args, fmt);
374
375 vaf.fmt = fmt;
376 vaf.va = &args;
377
378 printk(KERN_ERR "b43-%s ERROR: %pV",
379 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
380
381 va_end(args);
382 }
383
b43warn(struct b43_wl * wl,const char * fmt,...)384 void b43warn(struct b43_wl *wl, const char *fmt, ...)
385 {
386 struct va_format vaf;
387 va_list args;
388
389 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
390 return;
391 if (!b43_ratelimit(wl))
392 return;
393
394 va_start(args, fmt);
395
396 vaf.fmt = fmt;
397 vaf.va = &args;
398
399 printk(KERN_WARNING "b43-%s warning: %pV",
400 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
401
402 va_end(args);
403 }
404
b43dbg(struct b43_wl * wl,const char * fmt,...)405 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
406 {
407 struct va_format vaf;
408 va_list args;
409
410 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
411 return;
412
413 va_start(args, fmt);
414
415 vaf.fmt = fmt;
416 vaf.va = &args;
417
418 printk(KERN_DEBUG "b43-%s debug: %pV",
419 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
420
421 va_end(args);
422 }
423
b43_ram_write(struct b43_wldev * dev,u16 offset,u32 val)424 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
425 {
426 u32 macctl;
427
428 B43_WARN_ON(offset % 4 != 0);
429
430 macctl = b43_read32(dev, B43_MMIO_MACCTL);
431 if (macctl & B43_MACCTL_BE)
432 val = swab32(val);
433
434 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
435 mmiowb();
436 b43_write32(dev, B43_MMIO_RAM_DATA, val);
437 }
438
b43_shm_control_word(struct b43_wldev * dev,u16 routing,u16 offset)439 static inline void b43_shm_control_word(struct b43_wldev *dev,
440 u16 routing, u16 offset)
441 {
442 u32 control;
443
444 /* "offset" is the WORD offset. */
445 control = routing;
446 control <<= 16;
447 control |= offset;
448 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
449 }
450
b43_shm_read32(struct b43_wldev * dev,u16 routing,u16 offset)451 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
452 {
453 u32 ret;
454
455 if (routing == B43_SHM_SHARED) {
456 B43_WARN_ON(offset & 0x0001);
457 if (offset & 0x0003) {
458 /* Unaligned access */
459 b43_shm_control_word(dev, routing, offset >> 2);
460 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
461 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
462 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
463
464 goto out;
465 }
466 offset >>= 2;
467 }
468 b43_shm_control_word(dev, routing, offset);
469 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
470 out:
471 return ret;
472 }
473
b43_shm_read16(struct b43_wldev * dev,u16 routing,u16 offset)474 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
475 {
476 u16 ret;
477
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
484
485 goto out;
486 }
487 offset >>= 2;
488 }
489 b43_shm_control_word(dev, routing, offset);
490 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
491 out:
492 return ret;
493 }
494
b43_shm_write32(struct b43_wldev * dev,u16 routing,u16 offset,u32 value)495 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
496 {
497 if (routing == B43_SHM_SHARED) {
498 B43_WARN_ON(offset & 0x0001);
499 if (offset & 0x0003) {
500 /* Unaligned access */
501 b43_shm_control_word(dev, routing, offset >> 2);
502 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
503 value & 0xFFFF);
504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
505 b43_write16(dev, B43_MMIO_SHM_DATA,
506 (value >> 16) & 0xFFFF);
507 return;
508 }
509 offset >>= 2;
510 }
511 b43_shm_control_word(dev, routing, offset);
512 b43_write32(dev, B43_MMIO_SHM_DATA, value);
513 }
514
b43_shm_write16(struct b43_wldev * dev,u16 routing,u16 offset,u16 value)515 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
516 {
517 if (routing == B43_SHM_SHARED) {
518 B43_WARN_ON(offset & 0x0001);
519 if (offset & 0x0003) {
520 /* Unaligned access */
521 b43_shm_control_word(dev, routing, offset >> 2);
522 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
523 return;
524 }
525 offset >>= 2;
526 }
527 b43_shm_control_word(dev, routing, offset);
528 b43_write16(dev, B43_MMIO_SHM_DATA, value);
529 }
530
531 /* Read HostFlags */
b43_hf_read(struct b43_wldev * dev)532 u64 b43_hf_read(struct b43_wldev *dev)
533 {
534 u64 ret;
535
536 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
537 ret <<= 16;
538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
539 ret <<= 16;
540 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
541
542 return ret;
543 }
544
545 /* Write HostFlags */
b43_hf_write(struct b43_wldev * dev,u64 value)546 void b43_hf_write(struct b43_wldev *dev, u64 value)
547 {
548 u16 lo, mi, hi;
549
550 lo = (value & 0x00000000FFFFULL);
551 mi = (value & 0x0000FFFF0000ULL) >> 16;
552 hi = (value & 0xFFFF00000000ULL) >> 32;
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
554 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
555 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
556 }
557
558 /* Read the firmware capabilities bitmask (Opensource firmware only) */
b43_fwcapa_read(struct b43_wldev * dev)559 static u16 b43_fwcapa_read(struct b43_wldev *dev)
560 {
561 B43_WARN_ON(!dev->fw.opensource);
562 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
563 }
564
b43_tsf_read(struct b43_wldev * dev,u64 * tsf)565 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
566 {
567 u32 low, high;
568
569 B43_WARN_ON(dev->dev->core_rev < 3);
570
571 /* The hardware guarantees us an atomic read, if we
572 * read the low register first. */
573 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
574 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
575
576 *tsf = high;
577 *tsf <<= 32;
578 *tsf |= low;
579 }
580
b43_time_lock(struct b43_wldev * dev)581 static void b43_time_lock(struct b43_wldev *dev)
582 {
583 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
586 }
587
b43_time_unlock(struct b43_wldev * dev)588 static void b43_time_unlock(struct b43_wldev *dev)
589 {
590 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
591 /* Commit the write */
592 b43_read32(dev, B43_MMIO_MACCTL);
593 }
594
b43_tsf_write_locked(struct b43_wldev * dev,u64 tsf)595 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
596 {
597 u32 low, high;
598
599 B43_WARN_ON(dev->dev->core_rev < 3);
600
601 low = tsf;
602 high = (tsf >> 32);
603 /* The hardware guarantees us an atomic write, if we
604 * write the low register first. */
605 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
606 mmiowb();
607 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
608 mmiowb();
609 }
610
b43_tsf_write(struct b43_wldev * dev,u64 tsf)611 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
612 {
613 b43_time_lock(dev);
614 b43_tsf_write_locked(dev, tsf);
615 b43_time_unlock(dev);
616 }
617
618 static
b43_macfilter_set(struct b43_wldev * dev,u16 offset,const u8 * mac)619 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
620 {
621 static const u8 zero_addr[ETH_ALEN] = { 0 };
622 u16 data;
623
624 if (!mac)
625 mac = zero_addr;
626
627 offset |= 0x0020;
628 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
629
630 data = mac[0];
631 data |= mac[1] << 8;
632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
633 data = mac[2];
634 data |= mac[3] << 8;
635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
636 data = mac[4];
637 data |= mac[5] << 8;
638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
639 }
640
b43_write_mac_bssid_templates(struct b43_wldev * dev)641 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
642 {
643 const u8 *mac;
644 const u8 *bssid;
645 u8 mac_bssid[ETH_ALEN * 2];
646 int i;
647 u32 tmp;
648
649 bssid = dev->wl->bssid;
650 mac = dev->wl->mac_addr;
651
652 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
653
654 memcpy(mac_bssid, mac, ETH_ALEN);
655 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
656
657 /* Write our MAC address and BSSID to template ram */
658 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
659 tmp = (u32) (mac_bssid[i + 0]);
660 tmp |= (u32) (mac_bssid[i + 1]) << 8;
661 tmp |= (u32) (mac_bssid[i + 2]) << 16;
662 tmp |= (u32) (mac_bssid[i + 3]) << 24;
663 b43_ram_write(dev, 0x20 + i, tmp);
664 }
665 }
666
b43_upload_card_macaddress(struct b43_wldev * dev)667 static void b43_upload_card_macaddress(struct b43_wldev *dev)
668 {
669 b43_write_mac_bssid_templates(dev);
670 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
671 }
672
b43_set_slot_time(struct b43_wldev * dev,u16 slot_time)673 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
674 {
675 /* slot_time is in usec. */
676 /* This test used to exit for all but a G PHY. */
677 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
678 return;
679 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
680 /* Shared memory location 0x0010 is the slot time and should be
681 * set to slot_time; however, this register is initially 0 and changing
682 * the value adversely affects the transmit rate for BCM4311
683 * devices. Until this behavior is unterstood, delete this step
684 *
685 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
686 */
687 }
688
b43_short_slot_timing_enable(struct b43_wldev * dev)689 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
690 {
691 b43_set_slot_time(dev, 9);
692 }
693
b43_short_slot_timing_disable(struct b43_wldev * dev)694 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
695 {
696 b43_set_slot_time(dev, 20);
697 }
698
699 /* DummyTransmission function, as documented on
700 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
701 */
b43_dummy_transmission(struct b43_wldev * dev,bool ofdm,bool pa_on)702 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
703 {
704 struct b43_phy *phy = &dev->phy;
705 unsigned int i, max_loop;
706 u16 value;
707 u32 buffer[5] = {
708 0x00000000,
709 0x00D40000,
710 0x00000000,
711 0x01000000,
712 0x00000000,
713 };
714
715 if (ofdm) {
716 max_loop = 0x1E;
717 buffer[0] = 0x000201CC;
718 } else {
719 max_loop = 0xFA;
720 buffer[0] = 0x000B846E;
721 }
722
723 for (i = 0; i < 5; i++)
724 b43_ram_write(dev, i * 4, buffer[i]);
725
726 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
727
728 if (dev->dev->core_rev < 11)
729 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
730 else
731 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
732
733 value = (ofdm ? 0x41 : 0x40);
734 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
735 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
736 phy->type == B43_PHYTYPE_LCN)
737 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
738
739 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
740 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
741
742 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
743 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
744 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
745 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
746
747 if (!pa_on && phy->type == B43_PHYTYPE_N)
748 ; /*b43_nphy_pa_override(dev, false) */
749
750 switch (phy->type) {
751 case B43_PHYTYPE_N:
752 case B43_PHYTYPE_LCN:
753 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
754 break;
755 case B43_PHYTYPE_LP:
756 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
757 break;
758 default:
759 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
760 }
761 b43_read16(dev, B43_MMIO_TXE0_AUX);
762
763 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
764 b43_radio_write16(dev, 0x0051, 0x0017);
765 for (i = 0x00; i < max_loop; i++) {
766 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
767 if (value & 0x0080)
768 break;
769 udelay(10);
770 }
771 for (i = 0x00; i < 0x0A; i++) {
772 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
773 if (value & 0x0400)
774 break;
775 udelay(10);
776 }
777 for (i = 0x00; i < 0x19; i++) {
778 value = b43_read16(dev, B43_MMIO_IFSSTAT);
779 if (!(value & 0x0100))
780 break;
781 udelay(10);
782 }
783 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
784 b43_radio_write16(dev, 0x0051, 0x0037);
785 }
786
key_write(struct b43_wldev * dev,u8 index,u8 algorithm,const u8 * key)787 static void key_write(struct b43_wldev *dev,
788 u8 index, u8 algorithm, const u8 *key)
789 {
790 unsigned int i;
791 u32 offset;
792 u16 value;
793 u16 kidx;
794
795 /* Key index/algo block */
796 kidx = b43_kidx_to_fw(dev, index);
797 value = ((kidx << 4) | algorithm);
798 b43_shm_write16(dev, B43_SHM_SHARED,
799 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
800
801 /* Write the key to the Key Table Pointer offset */
802 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
803 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
804 value = key[i];
805 value |= (u16) (key[i + 1]) << 8;
806 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
807 }
808 }
809
keymac_write(struct b43_wldev * dev,u8 index,const u8 * addr)810 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
811 {
812 u32 addrtmp[2] = { 0, 0, };
813 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
814
815 if (b43_new_kidx_api(dev))
816 pairwise_keys_start = B43_NR_GROUP_KEYS;
817
818 B43_WARN_ON(index < pairwise_keys_start);
819 /* We have four default TX keys and possibly four default RX keys.
820 * Physical mac 0 is mapped to physical key 4 or 8, depending
821 * on the firmware version.
822 * So we must adjust the index here.
823 */
824 index -= pairwise_keys_start;
825 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
826
827 if (addr) {
828 addrtmp[0] = addr[0];
829 addrtmp[0] |= ((u32) (addr[1]) << 8);
830 addrtmp[0] |= ((u32) (addr[2]) << 16);
831 addrtmp[0] |= ((u32) (addr[3]) << 24);
832 addrtmp[1] = addr[4];
833 addrtmp[1] |= ((u32) (addr[5]) << 8);
834 }
835
836 /* Receive match transmitter address (RCMTA) mechanism */
837 b43_shm_write32(dev, B43_SHM_RCMTA,
838 (index * 2) + 0, addrtmp[0]);
839 b43_shm_write16(dev, B43_SHM_RCMTA,
840 (index * 2) + 1, addrtmp[1]);
841 }
842
843 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
844 * When a packet is received, the iv32 is checked.
845 * - if it doesn't the packet is returned without modification (and software
846 * decryption can be done). That's what happen when iv16 wrap.
847 * - if it does, the rc4 key is computed, and decryption is tried.
848 * Either it will success and B43_RX_MAC_DEC is returned,
849 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
850 * and the packet is not usable (it got modified by the ucode).
851 * So in order to never have B43_RX_MAC_DECERR, we should provide
852 * a iv32 and phase1key that match. Because we drop packets in case of
853 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
854 * packets will be lost without higher layer knowing (ie no resync possible
855 * until next wrap).
856 *
857 * NOTE : this should support 50 key like RCMTA because
858 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
859 */
rx_tkip_phase1_write(struct b43_wldev * dev,u8 index,u32 iv32,u16 * phase1key)860 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
861 u16 *phase1key)
862 {
863 unsigned int i;
864 u32 offset;
865 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
866
867 if (!modparam_hwtkip)
868 return;
869
870 if (b43_new_kidx_api(dev))
871 pairwise_keys_start = B43_NR_GROUP_KEYS;
872
873 B43_WARN_ON(index < pairwise_keys_start);
874 /* We have four default TX keys and possibly four default RX keys.
875 * Physical mac 0 is mapped to physical key 4 or 8, depending
876 * on the firmware version.
877 * So we must adjust the index here.
878 */
879 index -= pairwise_keys_start;
880 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
881
882 if (b43_debug(dev, B43_DBG_KEYS)) {
883 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
884 index, iv32);
885 }
886 /* Write the key to the RX tkip shared mem */
887 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
888 for (i = 0; i < 10; i += 2) {
889 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
890 phase1key ? phase1key[i / 2] : 0);
891 }
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
893 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
894 }
895
b43_op_update_tkip_key(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_key_conf * keyconf,struct ieee80211_sta * sta,u32 iv32,u16 * phase1key)896 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
897 struct ieee80211_vif *vif,
898 struct ieee80211_key_conf *keyconf,
899 struct ieee80211_sta *sta,
900 u32 iv32, u16 *phase1key)
901 {
902 struct b43_wl *wl = hw_to_b43_wl(hw);
903 struct b43_wldev *dev;
904 int index = keyconf->hw_key_idx;
905
906 if (B43_WARN_ON(!modparam_hwtkip))
907 return;
908
909 /* This is only called from the RX path through mac80211, where
910 * our mutex is already locked. */
911 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
912 dev = wl->current_dev;
913 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
914
915 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
916
917 rx_tkip_phase1_write(dev, index, iv32, phase1key);
918 /* only pairwise TKIP keys are supported right now */
919 if (WARN_ON(!sta))
920 return;
921 keymac_write(dev, index, sta->addr);
922 }
923
do_key_write(struct b43_wldev * dev,u8 index,u8 algorithm,const u8 * key,size_t key_len,const u8 * mac_addr)924 static void do_key_write(struct b43_wldev *dev,
925 u8 index, u8 algorithm,
926 const u8 *key, size_t key_len, const u8 *mac_addr)
927 {
928 u8 buf[B43_SEC_KEYSIZE] = { 0, };
929 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
930
931 if (b43_new_kidx_api(dev))
932 pairwise_keys_start = B43_NR_GROUP_KEYS;
933
934 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
935 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
936
937 if (index >= pairwise_keys_start)
938 keymac_write(dev, index, NULL); /* First zero out mac. */
939 if (algorithm == B43_SEC_ALGO_TKIP) {
940 /*
941 * We should provide an initial iv32, phase1key pair.
942 * We could start with iv32=0 and compute the corresponding
943 * phase1key, but this means calling ieee80211_get_tkip_key
944 * with a fake skb (or export other tkip function).
945 * Because we are lazy we hope iv32 won't start with
946 * 0xffffffff and let's b43_op_update_tkip_key provide a
947 * correct pair.
948 */
949 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
950 } else if (index >= pairwise_keys_start) /* clear it */
951 rx_tkip_phase1_write(dev, index, 0, NULL);
952 if (key)
953 memcpy(buf, key, key_len);
954 key_write(dev, index, algorithm, buf);
955 if (index >= pairwise_keys_start)
956 keymac_write(dev, index, mac_addr);
957
958 dev->key[index].algorithm = algorithm;
959 }
960
b43_key_write(struct b43_wldev * dev,int index,u8 algorithm,const u8 * key,size_t key_len,const u8 * mac_addr,struct ieee80211_key_conf * keyconf)961 static int b43_key_write(struct b43_wldev *dev,
962 int index, u8 algorithm,
963 const u8 *key, size_t key_len,
964 const u8 *mac_addr,
965 struct ieee80211_key_conf *keyconf)
966 {
967 int i;
968 int pairwise_keys_start;
969
970 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
971 * - Temporal Encryption Key (128 bits)
972 * - Temporal Authenticator Tx MIC Key (64 bits)
973 * - Temporal Authenticator Rx MIC Key (64 bits)
974 *
975 * Hardware only store TEK
976 */
977 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
978 key_len = 16;
979 if (key_len > B43_SEC_KEYSIZE)
980 return -EINVAL;
981 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
982 /* Check that we don't already have this key. */
983 B43_WARN_ON(dev->key[i].keyconf == keyconf);
984 }
985 if (index < 0) {
986 /* Pairwise key. Get an empty slot for the key. */
987 if (b43_new_kidx_api(dev))
988 pairwise_keys_start = B43_NR_GROUP_KEYS;
989 else
990 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
991 for (i = pairwise_keys_start;
992 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
993 i++) {
994 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
995 if (!dev->key[i].keyconf) {
996 /* found empty */
997 index = i;
998 break;
999 }
1000 }
1001 if (index < 0) {
1002 b43warn(dev->wl, "Out of hardware key memory\n");
1003 return -ENOSPC;
1004 }
1005 } else
1006 B43_WARN_ON(index > 3);
1007
1008 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1009 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1010 /* Default RX key */
1011 B43_WARN_ON(mac_addr);
1012 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1013 }
1014 keyconf->hw_key_idx = index;
1015 dev->key[index].keyconf = keyconf;
1016
1017 return 0;
1018 }
1019
b43_key_clear(struct b43_wldev * dev,int index)1020 static int b43_key_clear(struct b43_wldev *dev, int index)
1021 {
1022 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1023 return -EINVAL;
1024 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1025 NULL, B43_SEC_KEYSIZE, NULL);
1026 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1027 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1028 NULL, B43_SEC_KEYSIZE, NULL);
1029 }
1030 dev->key[index].keyconf = NULL;
1031
1032 return 0;
1033 }
1034
b43_clear_keys(struct b43_wldev * dev)1035 static void b43_clear_keys(struct b43_wldev *dev)
1036 {
1037 int i, count;
1038
1039 if (b43_new_kidx_api(dev))
1040 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1041 else
1042 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1043 for (i = 0; i < count; i++)
1044 b43_key_clear(dev, i);
1045 }
1046
b43_dump_keymemory(struct b43_wldev * dev)1047 static void b43_dump_keymemory(struct b43_wldev *dev)
1048 {
1049 unsigned int i, index, count, offset, pairwise_keys_start;
1050 u8 mac[ETH_ALEN];
1051 u16 algo;
1052 u32 rcmta0;
1053 u16 rcmta1;
1054 u64 hf;
1055 struct b43_key *key;
1056
1057 if (!b43_debug(dev, B43_DBG_KEYS))
1058 return;
1059
1060 hf = b43_hf_read(dev);
1061 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1062 !!(hf & B43_HF_USEDEFKEYS));
1063 if (b43_new_kidx_api(dev)) {
1064 pairwise_keys_start = B43_NR_GROUP_KEYS;
1065 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1066 } else {
1067 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1068 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1069 }
1070 for (index = 0; index < count; index++) {
1071 key = &(dev->key[index]);
1072 printk(KERN_DEBUG "Key slot %02u: %s",
1073 index, (key->keyconf == NULL) ? " " : "*");
1074 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1075 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1076 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1077 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1078 }
1079
1080 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1081 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1082 printk(" Algo: %04X/%02X", algo, key->algorithm);
1083
1084 if (index >= pairwise_keys_start) {
1085 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1086 printk(" TKIP: ");
1087 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1088 for (i = 0; i < 14; i += 2) {
1089 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1090 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1091 }
1092 }
1093 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1094 ((index - pairwise_keys_start) * 2) + 0);
1095 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1096 ((index - pairwise_keys_start) * 2) + 1);
1097 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1098 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1099 printk(" MAC: %pM", mac);
1100 } else
1101 printk(" DEFAULT KEY");
1102 printk("\n");
1103 }
1104 }
1105
b43_power_saving_ctl_bits(struct b43_wldev * dev,unsigned int ps_flags)1106 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1107 {
1108 u32 macctl;
1109 u16 ucstat;
1110 bool hwps;
1111 bool awake;
1112 int i;
1113
1114 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1115 (ps_flags & B43_PS_DISABLED));
1116 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1117
1118 if (ps_flags & B43_PS_ENABLED) {
1119 hwps = true;
1120 } else if (ps_flags & B43_PS_DISABLED) {
1121 hwps = false;
1122 } else {
1123 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1124 // and thus is not an AP and we are associated, set bit 25
1125 }
1126 if (ps_flags & B43_PS_AWAKE) {
1127 awake = true;
1128 } else if (ps_flags & B43_PS_ASLEEP) {
1129 awake = false;
1130 } else {
1131 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1132 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1133 // successful, set bit26
1134 }
1135
1136 /* FIXME: For now we force awake-on and hwps-off */
1137 hwps = false;
1138 awake = true;
1139
1140 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1141 if (hwps)
1142 macctl |= B43_MACCTL_HWPS;
1143 else
1144 macctl &= ~B43_MACCTL_HWPS;
1145 if (awake)
1146 macctl |= B43_MACCTL_AWAKE;
1147 else
1148 macctl &= ~B43_MACCTL_AWAKE;
1149 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1150 /* Commit write */
1151 b43_read32(dev, B43_MMIO_MACCTL);
1152 if (awake && dev->dev->core_rev >= 5) {
1153 /* Wait for the microcode to wake up. */
1154 for (i = 0; i < 100; i++) {
1155 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1156 B43_SHM_SH_UCODESTAT);
1157 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1158 break;
1159 udelay(10);
1160 }
1161 }
1162 }
1163
1164 #ifdef CONFIG_B43_BCMA
b43_bcma_phy_reset(struct b43_wldev * dev)1165 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1166 {
1167 u32 flags;
1168
1169 /* Put PHY into reset */
1170 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1171 flags |= B43_BCMA_IOCTL_PHY_RESET;
1172 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1173 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1174 udelay(2);
1175
1176 /* Take PHY out of reset */
1177 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1178 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1179 flags |= BCMA_IOCTL_FGC;
1180 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1181 udelay(1);
1182
1183 /* Do not force clock anymore */
1184 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1185 flags &= ~BCMA_IOCTL_FGC;
1186 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1187 udelay(1);
1188 }
1189
b43_bcma_wireless_core_reset(struct b43_wldev * dev,bool gmode)1190 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1191 {
1192 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1193 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1194 b43_bcma_phy_reset(dev);
1195 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
1196 }
1197 #endif
1198
b43_ssb_wireless_core_reset(struct b43_wldev * dev,bool gmode)1199 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1200 {
1201 struct ssb_device *sdev = dev->dev->sdev;
1202 u32 tmslow;
1203 u32 flags = 0;
1204
1205 if (gmode)
1206 flags |= B43_TMSLOW_GMODE;
1207 flags |= B43_TMSLOW_PHYCLKEN;
1208 flags |= B43_TMSLOW_PHYRESET;
1209 if (dev->phy.type == B43_PHYTYPE_N)
1210 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1211 b43_device_enable(dev, flags);
1212 msleep(2); /* Wait for the PLL to turn on. */
1213
1214 /* Now take the PHY out of Reset again */
1215 tmslow = ssb_read32(sdev, SSB_TMSLOW);
1216 tmslow |= SSB_TMSLOW_FGC;
1217 tmslow &= ~B43_TMSLOW_PHYRESET;
1218 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1219 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1220 msleep(1);
1221 tmslow &= ~SSB_TMSLOW_FGC;
1222 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1223 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1224 msleep(1);
1225 }
1226
b43_wireless_core_reset(struct b43_wldev * dev,bool gmode)1227 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1228 {
1229 u32 macctl;
1230
1231 switch (dev->dev->bus_type) {
1232 #ifdef CONFIG_B43_BCMA
1233 case B43_BUS_BCMA:
1234 b43_bcma_wireless_core_reset(dev, gmode);
1235 break;
1236 #endif
1237 #ifdef CONFIG_B43_SSB
1238 case B43_BUS_SSB:
1239 b43_ssb_wireless_core_reset(dev, gmode);
1240 break;
1241 #endif
1242 }
1243
1244 /* Turn Analog ON, but only if we already know the PHY-type.
1245 * This protects against very early setup where we don't know the
1246 * PHY-type, yet. wireless_core_reset will be called once again later,
1247 * when we know the PHY-type. */
1248 if (dev->phy.ops)
1249 dev->phy.ops->switch_analog(dev, 1);
1250
1251 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1252 macctl &= ~B43_MACCTL_GMODE;
1253 if (gmode)
1254 macctl |= B43_MACCTL_GMODE;
1255 macctl |= B43_MACCTL_IHR_ENABLED;
1256 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1257 }
1258
handle_irq_transmit_status(struct b43_wldev * dev)1259 static void handle_irq_transmit_status(struct b43_wldev *dev)
1260 {
1261 u32 v0, v1;
1262 u16 tmp;
1263 struct b43_txstatus stat;
1264
1265 while (1) {
1266 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1267 if (!(v0 & 0x00000001))
1268 break;
1269 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1270
1271 stat.cookie = (v0 >> 16);
1272 stat.seq = (v1 & 0x0000FFFF);
1273 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1274 tmp = (v0 & 0x0000FFFF);
1275 stat.frame_count = ((tmp & 0xF000) >> 12);
1276 stat.rts_count = ((tmp & 0x0F00) >> 8);
1277 stat.supp_reason = ((tmp & 0x001C) >> 2);
1278 stat.pm_indicated = !!(tmp & 0x0080);
1279 stat.intermediate = !!(tmp & 0x0040);
1280 stat.for_ampdu = !!(tmp & 0x0020);
1281 stat.acked = !!(tmp & 0x0002);
1282
1283 b43_handle_txstatus(dev, &stat);
1284 }
1285 }
1286
drain_txstatus_queue(struct b43_wldev * dev)1287 static void drain_txstatus_queue(struct b43_wldev *dev)
1288 {
1289 u32 dummy;
1290
1291 if (dev->dev->core_rev < 5)
1292 return;
1293 /* Read all entries from the microcode TXstatus FIFO
1294 * and throw them away.
1295 */
1296 while (1) {
1297 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1298 if (!(dummy & 0x00000001))
1299 break;
1300 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1301 }
1302 }
1303
b43_jssi_read(struct b43_wldev * dev)1304 static u32 b43_jssi_read(struct b43_wldev *dev)
1305 {
1306 u32 val = 0;
1307
1308 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1309 val <<= 16;
1310 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1311
1312 return val;
1313 }
1314
b43_jssi_write(struct b43_wldev * dev,u32 jssi)1315 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1316 {
1317 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1318 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1319 }
1320
b43_generate_noise_sample(struct b43_wldev * dev)1321 static void b43_generate_noise_sample(struct b43_wldev *dev)
1322 {
1323 b43_jssi_write(dev, 0x7F7F7F7F);
1324 b43_write32(dev, B43_MMIO_MACCMD,
1325 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1326 }
1327
b43_calculate_link_quality(struct b43_wldev * dev)1328 static void b43_calculate_link_quality(struct b43_wldev *dev)
1329 {
1330 /* Top half of Link Quality calculation. */
1331
1332 if (dev->phy.type != B43_PHYTYPE_G)
1333 return;
1334 if (dev->noisecalc.calculation_running)
1335 return;
1336 dev->noisecalc.calculation_running = true;
1337 dev->noisecalc.nr_samples = 0;
1338
1339 b43_generate_noise_sample(dev);
1340 }
1341
handle_irq_noise(struct b43_wldev * dev)1342 static void handle_irq_noise(struct b43_wldev *dev)
1343 {
1344 struct b43_phy_g *phy = dev->phy.g;
1345 u16 tmp;
1346 u8 noise[4];
1347 u8 i, j;
1348 s32 average;
1349
1350 /* Bottom half of Link Quality calculation. */
1351
1352 if (dev->phy.type != B43_PHYTYPE_G)
1353 return;
1354
1355 /* Possible race condition: It might be possible that the user
1356 * changed to a different channel in the meantime since we
1357 * started the calculation. We ignore that fact, since it's
1358 * not really that much of a problem. The background noise is
1359 * an estimation only anyway. Slightly wrong results will get damped
1360 * by the averaging of the 8 sample rounds. Additionally the
1361 * value is shortlived. So it will be replaced by the next noise
1362 * calculation round soon. */
1363
1364 B43_WARN_ON(!dev->noisecalc.calculation_running);
1365 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1366 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1367 noise[2] == 0x7F || noise[3] == 0x7F)
1368 goto generate_new;
1369
1370 /* Get the noise samples. */
1371 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1372 i = dev->noisecalc.nr_samples;
1373 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1375 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1376 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1377 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1378 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1379 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1380 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1381 dev->noisecalc.nr_samples++;
1382 if (dev->noisecalc.nr_samples == 8) {
1383 /* Calculate the Link Quality by the noise samples. */
1384 average = 0;
1385 for (i = 0; i < 8; i++) {
1386 for (j = 0; j < 4; j++)
1387 average += dev->noisecalc.samples[i][j];
1388 }
1389 average /= (8 * 4);
1390 average *= 125;
1391 average += 64;
1392 average /= 128;
1393 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1394 tmp = (tmp / 128) & 0x1F;
1395 if (tmp >= 8)
1396 average += 2;
1397 else
1398 average -= 25;
1399 if (tmp == 8)
1400 average -= 72;
1401 else
1402 average -= 48;
1403
1404 dev->stats.link_noise = average;
1405 dev->noisecalc.calculation_running = false;
1406 return;
1407 }
1408 generate_new:
1409 b43_generate_noise_sample(dev);
1410 }
1411
handle_irq_tbtt_indication(struct b43_wldev * dev)1412 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1413 {
1414 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1415 ///TODO: PS TBTT
1416 } else {
1417 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1418 b43_power_saving_ctl_bits(dev, 0);
1419 }
1420 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1421 dev->dfq_valid = true;
1422 }
1423
handle_irq_atim_end(struct b43_wldev * dev)1424 static void handle_irq_atim_end(struct b43_wldev *dev)
1425 {
1426 if (dev->dfq_valid) {
1427 b43_write32(dev, B43_MMIO_MACCMD,
1428 b43_read32(dev, B43_MMIO_MACCMD)
1429 | B43_MACCMD_DFQ_VALID);
1430 dev->dfq_valid = false;
1431 }
1432 }
1433
handle_irq_pmq(struct b43_wldev * dev)1434 static void handle_irq_pmq(struct b43_wldev *dev)
1435 {
1436 u32 tmp;
1437
1438 //TODO: AP mode.
1439
1440 while (1) {
1441 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1442 if (!(tmp & 0x00000008))
1443 break;
1444 }
1445 /* 16bit write is odd, but correct. */
1446 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1447 }
1448
b43_write_template_common(struct b43_wldev * dev,const u8 * data,u16 size,u16 ram_offset,u16 shm_size_offset,u8 rate)1449 static void b43_write_template_common(struct b43_wldev *dev,
1450 const u8 *data, u16 size,
1451 u16 ram_offset,
1452 u16 shm_size_offset, u8 rate)
1453 {
1454 u32 i, tmp;
1455 struct b43_plcp_hdr4 plcp;
1456
1457 plcp.data = 0;
1458 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1459 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1460 ram_offset += sizeof(u32);
1461 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1462 * So leave the first two bytes of the next write blank.
1463 */
1464 tmp = (u32) (data[0]) << 16;
1465 tmp |= (u32) (data[1]) << 24;
1466 b43_ram_write(dev, ram_offset, tmp);
1467 ram_offset += sizeof(u32);
1468 for (i = 2; i < size; i += sizeof(u32)) {
1469 tmp = (u32) (data[i + 0]);
1470 if (i + 1 < size)
1471 tmp |= (u32) (data[i + 1]) << 8;
1472 if (i + 2 < size)
1473 tmp |= (u32) (data[i + 2]) << 16;
1474 if (i + 3 < size)
1475 tmp |= (u32) (data[i + 3]) << 24;
1476 b43_ram_write(dev, ram_offset + i - 2, tmp);
1477 }
1478 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1479 size + sizeof(struct b43_plcp_hdr6));
1480 }
1481
1482 /* Check if the use of the antenna that ieee80211 told us to
1483 * use is possible. This will fall back to DEFAULT.
1484 * "antenna_nr" is the antenna identifier we got from ieee80211. */
b43_ieee80211_antenna_sanitize(struct b43_wldev * dev,u8 antenna_nr)1485 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1486 u8 antenna_nr)
1487 {
1488 u8 antenna_mask;
1489
1490 if (antenna_nr == 0) {
1491 /* Zero means "use default antenna". That's always OK. */
1492 return 0;
1493 }
1494
1495 /* Get the mask of available antennas. */
1496 if (dev->phy.gmode)
1497 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1498 else
1499 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1500
1501 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1502 /* This antenna is not available. Fall back to default. */
1503 return 0;
1504 }
1505
1506 return antenna_nr;
1507 }
1508
1509 /* Convert a b43 antenna number value to the PHY TX control value. */
b43_antenna_to_phyctl(int antenna)1510 static u16 b43_antenna_to_phyctl(int antenna)
1511 {
1512 switch (antenna) {
1513 case B43_ANTENNA0:
1514 return B43_TXH_PHY_ANT0;
1515 case B43_ANTENNA1:
1516 return B43_TXH_PHY_ANT1;
1517 case B43_ANTENNA2:
1518 return B43_TXH_PHY_ANT2;
1519 case B43_ANTENNA3:
1520 return B43_TXH_PHY_ANT3;
1521 case B43_ANTENNA_AUTO0:
1522 case B43_ANTENNA_AUTO1:
1523 return B43_TXH_PHY_ANT01AUTO;
1524 }
1525 B43_WARN_ON(1);
1526 return 0;
1527 }
1528
b43_write_beacon_template(struct b43_wldev * dev,u16 ram_offset,u16 shm_size_offset)1529 static void b43_write_beacon_template(struct b43_wldev *dev,
1530 u16 ram_offset,
1531 u16 shm_size_offset)
1532 {
1533 unsigned int i, len, variable_len;
1534 const struct ieee80211_mgmt *bcn;
1535 const u8 *ie;
1536 bool tim_found = false;
1537 unsigned int rate;
1538 u16 ctl;
1539 int antenna;
1540 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1541
1542 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1543 len = min((size_t) dev->wl->current_beacon->len,
1544 0x200 - sizeof(struct b43_plcp_hdr6));
1545 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1546
1547 b43_write_template_common(dev, (const u8 *)bcn,
1548 len, ram_offset, shm_size_offset, rate);
1549
1550 /* Write the PHY TX control parameters. */
1551 antenna = B43_ANTENNA_DEFAULT;
1552 antenna = b43_antenna_to_phyctl(antenna);
1553 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1554 /* We can't send beacons with short preamble. Would get PHY errors. */
1555 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1556 ctl &= ~B43_TXH_PHY_ANT;
1557 ctl &= ~B43_TXH_PHY_ENC;
1558 ctl |= antenna;
1559 if (b43_is_cck_rate(rate))
1560 ctl |= B43_TXH_PHY_ENC_CCK;
1561 else
1562 ctl |= B43_TXH_PHY_ENC_OFDM;
1563 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1564
1565 /* Find the position of the TIM and the DTIM_period value
1566 * and write them to SHM. */
1567 ie = bcn->u.beacon.variable;
1568 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1569 for (i = 0; i < variable_len - 2; ) {
1570 uint8_t ie_id, ie_len;
1571
1572 ie_id = ie[i];
1573 ie_len = ie[i + 1];
1574 if (ie_id == 5) {
1575 u16 tim_position;
1576 u16 dtim_period;
1577 /* This is the TIM Information Element */
1578
1579 /* Check whether the ie_len is in the beacon data range. */
1580 if (variable_len < ie_len + 2 + i)
1581 break;
1582 /* A valid TIM is at least 4 bytes long. */
1583 if (ie_len < 4)
1584 break;
1585 tim_found = true;
1586
1587 tim_position = sizeof(struct b43_plcp_hdr6);
1588 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1589 tim_position += i;
1590
1591 dtim_period = ie[i + 3];
1592
1593 b43_shm_write16(dev, B43_SHM_SHARED,
1594 B43_SHM_SH_TIMBPOS, tim_position);
1595 b43_shm_write16(dev, B43_SHM_SHARED,
1596 B43_SHM_SH_DTIMPER, dtim_period);
1597 break;
1598 }
1599 i += ie_len + 2;
1600 }
1601 if (!tim_found) {
1602 /*
1603 * If ucode wants to modify TIM do it behind the beacon, this
1604 * will happen, for example, when doing mesh networking.
1605 */
1606 b43_shm_write16(dev, B43_SHM_SHARED,
1607 B43_SHM_SH_TIMBPOS,
1608 len + sizeof(struct b43_plcp_hdr6));
1609 b43_shm_write16(dev, B43_SHM_SHARED,
1610 B43_SHM_SH_DTIMPER, 0);
1611 }
1612 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1613 }
1614
b43_upload_beacon0(struct b43_wldev * dev)1615 static void b43_upload_beacon0(struct b43_wldev *dev)
1616 {
1617 struct b43_wl *wl = dev->wl;
1618
1619 if (wl->beacon0_uploaded)
1620 return;
1621 b43_write_beacon_template(dev, 0x68, 0x18);
1622 wl->beacon0_uploaded = true;
1623 }
1624
b43_upload_beacon1(struct b43_wldev * dev)1625 static void b43_upload_beacon1(struct b43_wldev *dev)
1626 {
1627 struct b43_wl *wl = dev->wl;
1628
1629 if (wl->beacon1_uploaded)
1630 return;
1631 b43_write_beacon_template(dev, 0x468, 0x1A);
1632 wl->beacon1_uploaded = true;
1633 }
1634
handle_irq_beacon(struct b43_wldev * dev)1635 static void handle_irq_beacon(struct b43_wldev *dev)
1636 {
1637 struct b43_wl *wl = dev->wl;
1638 u32 cmd, beacon0_valid, beacon1_valid;
1639
1640 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1641 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1642 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1643 return;
1644
1645 /* This is the bottom half of the asynchronous beacon update. */
1646
1647 /* Ignore interrupt in the future. */
1648 dev->irq_mask &= ~B43_IRQ_BEACON;
1649
1650 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1651 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1652 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1653
1654 /* Schedule interrupt manually, if busy. */
1655 if (beacon0_valid && beacon1_valid) {
1656 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1657 dev->irq_mask |= B43_IRQ_BEACON;
1658 return;
1659 }
1660
1661 if (unlikely(wl->beacon_templates_virgin)) {
1662 /* We never uploaded a beacon before.
1663 * Upload both templates now, but only mark one valid. */
1664 wl->beacon_templates_virgin = false;
1665 b43_upload_beacon0(dev);
1666 b43_upload_beacon1(dev);
1667 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1668 cmd |= B43_MACCMD_BEACON0_VALID;
1669 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1670 } else {
1671 if (!beacon0_valid) {
1672 b43_upload_beacon0(dev);
1673 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1674 cmd |= B43_MACCMD_BEACON0_VALID;
1675 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1676 } else if (!beacon1_valid) {
1677 b43_upload_beacon1(dev);
1678 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1679 cmd |= B43_MACCMD_BEACON1_VALID;
1680 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1681 }
1682 }
1683 }
1684
b43_do_beacon_update_trigger_work(struct b43_wldev * dev)1685 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1686 {
1687 u32 old_irq_mask = dev->irq_mask;
1688
1689 /* update beacon right away or defer to irq */
1690 handle_irq_beacon(dev);
1691 if (old_irq_mask != dev->irq_mask) {
1692 /* The handler updated the IRQ mask. */
1693 B43_WARN_ON(!dev->irq_mask);
1694 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1695 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1696 } else {
1697 /* Device interrupts are currently disabled. That means
1698 * we just ran the hardirq handler and scheduled the
1699 * IRQ thread. The thread will write the IRQ mask when
1700 * it finished, so there's nothing to do here. Writing
1701 * the mask _here_ would incorrectly re-enable IRQs. */
1702 }
1703 }
1704 }
1705
b43_beacon_update_trigger_work(struct work_struct * work)1706 static void b43_beacon_update_trigger_work(struct work_struct *work)
1707 {
1708 struct b43_wl *wl = container_of(work, struct b43_wl,
1709 beacon_update_trigger);
1710 struct b43_wldev *dev;
1711
1712 mutex_lock(&wl->mutex);
1713 dev = wl->current_dev;
1714 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1715 if (b43_bus_host_is_sdio(dev->dev)) {
1716 /* wl->mutex is enough. */
1717 b43_do_beacon_update_trigger_work(dev);
1718 mmiowb();
1719 } else {
1720 spin_lock_irq(&wl->hardirq_lock);
1721 b43_do_beacon_update_trigger_work(dev);
1722 mmiowb();
1723 spin_unlock_irq(&wl->hardirq_lock);
1724 }
1725 }
1726 mutex_unlock(&wl->mutex);
1727 }
1728
1729 /* Asynchronously update the packet templates in template RAM.
1730 * Locking: Requires wl->mutex to be locked. */
b43_update_templates(struct b43_wl * wl)1731 static void b43_update_templates(struct b43_wl *wl)
1732 {
1733 struct sk_buff *beacon;
1734
1735 /* This is the top half of the ansynchronous beacon update.
1736 * The bottom half is the beacon IRQ.
1737 * Beacon update must be asynchronous to avoid sending an
1738 * invalid beacon. This can happen for example, if the firmware
1739 * transmits a beacon while we are updating it. */
1740
1741 /* We could modify the existing beacon and set the aid bit in
1742 * the TIM field, but that would probably require resizing and
1743 * moving of data within the beacon template.
1744 * Simply request a new beacon and let mac80211 do the hard work. */
1745 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1746 if (unlikely(!beacon))
1747 return;
1748
1749 if (wl->current_beacon)
1750 dev_kfree_skb_any(wl->current_beacon);
1751 wl->current_beacon = beacon;
1752 wl->beacon0_uploaded = false;
1753 wl->beacon1_uploaded = false;
1754 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1755 }
1756
b43_set_beacon_int(struct b43_wldev * dev,u16 beacon_int)1757 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1758 {
1759 b43_time_lock(dev);
1760 if (dev->dev->core_rev >= 3) {
1761 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1762 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1763 } else {
1764 b43_write16(dev, 0x606, (beacon_int >> 6));
1765 b43_write16(dev, 0x610, beacon_int);
1766 }
1767 b43_time_unlock(dev);
1768 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1769 }
1770
b43_handle_firmware_panic(struct b43_wldev * dev)1771 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1772 {
1773 u16 reason;
1774
1775 /* Read the register that contains the reason code for the panic. */
1776 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1777 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1778
1779 switch (reason) {
1780 default:
1781 b43dbg(dev->wl, "The panic reason is unknown.\n");
1782 /* fallthrough */
1783 case B43_FWPANIC_DIE:
1784 /* Do not restart the controller or firmware.
1785 * The device is nonfunctional from now on.
1786 * Restarting would result in this panic to trigger again,
1787 * so we avoid that recursion. */
1788 break;
1789 case B43_FWPANIC_RESTART:
1790 b43_controller_restart(dev, "Microcode panic");
1791 break;
1792 }
1793 }
1794
handle_irq_ucode_debug(struct b43_wldev * dev)1795 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1796 {
1797 unsigned int i, cnt;
1798 u16 reason, marker_id, marker_line;
1799 __le16 *buf;
1800
1801 /* The proprietary firmware doesn't have this IRQ. */
1802 if (!dev->fw.opensource)
1803 return;
1804
1805 /* Read the register that contains the reason code for this IRQ. */
1806 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1807
1808 switch (reason) {
1809 case B43_DEBUGIRQ_PANIC:
1810 b43_handle_firmware_panic(dev);
1811 break;
1812 case B43_DEBUGIRQ_DUMP_SHM:
1813 if (!B43_DEBUG)
1814 break; /* Only with driver debugging enabled. */
1815 buf = kmalloc(4096, GFP_ATOMIC);
1816 if (!buf) {
1817 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1818 goto out;
1819 }
1820 for (i = 0; i < 4096; i += 2) {
1821 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1822 buf[i / 2] = cpu_to_le16(tmp);
1823 }
1824 b43info(dev->wl, "Shared memory dump:\n");
1825 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1826 16, 2, buf, 4096, 1);
1827 kfree(buf);
1828 break;
1829 case B43_DEBUGIRQ_DUMP_REGS:
1830 if (!B43_DEBUG)
1831 break; /* Only with driver debugging enabled. */
1832 b43info(dev->wl, "Microcode register dump:\n");
1833 for (i = 0, cnt = 0; i < 64; i++) {
1834 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1835 if (cnt == 0)
1836 printk(KERN_INFO);
1837 printk("r%02u: 0x%04X ", i, tmp);
1838 cnt++;
1839 if (cnt == 6) {
1840 printk("\n");
1841 cnt = 0;
1842 }
1843 }
1844 printk("\n");
1845 break;
1846 case B43_DEBUGIRQ_MARKER:
1847 if (!B43_DEBUG)
1848 break; /* Only with driver debugging enabled. */
1849 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1850 B43_MARKER_ID_REG);
1851 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1852 B43_MARKER_LINE_REG);
1853 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1854 "at line number %u\n",
1855 marker_id, marker_line);
1856 break;
1857 default:
1858 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1859 reason);
1860 }
1861 out:
1862 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1863 b43_shm_write16(dev, B43_SHM_SCRATCH,
1864 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1865 }
1866
b43_do_interrupt_thread(struct b43_wldev * dev)1867 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1868 {
1869 u32 reason;
1870 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1871 u32 merged_dma_reason = 0;
1872 int i;
1873
1874 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1875 return;
1876
1877 reason = dev->irq_reason;
1878 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1879 dma_reason[i] = dev->dma_reason[i];
1880 merged_dma_reason |= dma_reason[i];
1881 }
1882
1883 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1884 b43err(dev->wl, "MAC transmission error\n");
1885
1886 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1887 b43err(dev->wl, "PHY transmission error\n");
1888 rmb();
1889 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1890 atomic_set(&dev->phy.txerr_cnt,
1891 B43_PHY_TX_BADNESS_LIMIT);
1892 b43err(dev->wl, "Too many PHY TX errors, "
1893 "restarting the controller\n");
1894 b43_controller_restart(dev, "PHY TX errors");
1895 }
1896 }
1897
1898 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
1899 b43err(dev->wl,
1900 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1901 dma_reason[0], dma_reason[1],
1902 dma_reason[2], dma_reason[3],
1903 dma_reason[4], dma_reason[5]);
1904 b43err(dev->wl, "This device does not support DMA "
1905 "on your system. It will now be switched to PIO.\n");
1906 /* Fall back to PIO transfers if we get fatal DMA errors! */
1907 dev->use_pio = true;
1908 b43_controller_restart(dev, "DMA error");
1909 return;
1910 }
1911
1912 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1913 handle_irq_ucode_debug(dev);
1914 if (reason & B43_IRQ_TBTT_INDI)
1915 handle_irq_tbtt_indication(dev);
1916 if (reason & B43_IRQ_ATIM_END)
1917 handle_irq_atim_end(dev);
1918 if (reason & B43_IRQ_BEACON)
1919 handle_irq_beacon(dev);
1920 if (reason & B43_IRQ_PMQ)
1921 handle_irq_pmq(dev);
1922 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1923 ;/* TODO */
1924 if (reason & B43_IRQ_NOISESAMPLE_OK)
1925 handle_irq_noise(dev);
1926
1927 /* Check the DMA reason registers for received data. */
1928 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
1929 if (B43_DEBUG)
1930 b43warn(dev->wl, "RX descriptor underrun\n");
1931 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
1932 }
1933 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1934 if (b43_using_pio_transfers(dev))
1935 b43_pio_rx(dev->pio.rx_queue);
1936 else
1937 b43_dma_rx(dev->dma.rx_ring);
1938 }
1939 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1940 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1941 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1942 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1943 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1944
1945 if (reason & B43_IRQ_TX_OK)
1946 handle_irq_transmit_status(dev);
1947
1948 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1949 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1950
1951 #if B43_DEBUG
1952 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1953 dev->irq_count++;
1954 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1955 if (reason & (1 << i))
1956 dev->irq_bit_count[i]++;
1957 }
1958 }
1959 #endif
1960 }
1961
1962 /* Interrupt thread handler. Handles device interrupts in thread context. */
b43_interrupt_thread_handler(int irq,void * dev_id)1963 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1964 {
1965 struct b43_wldev *dev = dev_id;
1966
1967 mutex_lock(&dev->wl->mutex);
1968 b43_do_interrupt_thread(dev);
1969 mmiowb();
1970 mutex_unlock(&dev->wl->mutex);
1971
1972 return IRQ_HANDLED;
1973 }
1974
b43_do_interrupt(struct b43_wldev * dev)1975 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1976 {
1977 u32 reason;
1978
1979 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1980 * On SDIO, this runs under wl->mutex. */
1981
1982 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1983 if (reason == 0xffffffff) /* shared IRQ */
1984 return IRQ_NONE;
1985 reason &= dev->irq_mask;
1986 if (!reason)
1987 return IRQ_NONE;
1988
1989 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1990 & 0x0001FC00;
1991 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1992 & 0x0000DC00;
1993 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1994 & 0x0000DC00;
1995 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1996 & 0x0001DC00;
1997 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1998 & 0x0000DC00;
1999 /* Unused ring
2000 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2001 & 0x0000DC00;
2002 */
2003
2004 /* ACK the interrupt. */
2005 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2006 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2007 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2008 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2009 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2010 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2011 /* Unused ring
2012 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2013 */
2014
2015 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2016 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2017 /* Save the reason bitmasks for the IRQ thread handler. */
2018 dev->irq_reason = reason;
2019
2020 return IRQ_WAKE_THREAD;
2021 }
2022
2023 /* Interrupt handler top-half. This runs with interrupts disabled. */
b43_interrupt_handler(int irq,void * dev_id)2024 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2025 {
2026 struct b43_wldev *dev = dev_id;
2027 irqreturn_t ret;
2028
2029 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2030 return IRQ_NONE;
2031
2032 spin_lock(&dev->wl->hardirq_lock);
2033 ret = b43_do_interrupt(dev);
2034 mmiowb();
2035 spin_unlock(&dev->wl->hardirq_lock);
2036
2037 return ret;
2038 }
2039
2040 /* SDIO interrupt handler. This runs in process context. */
b43_sdio_interrupt_handler(struct b43_wldev * dev)2041 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2042 {
2043 struct b43_wl *wl = dev->wl;
2044 irqreturn_t ret;
2045
2046 mutex_lock(&wl->mutex);
2047
2048 ret = b43_do_interrupt(dev);
2049 if (ret == IRQ_WAKE_THREAD)
2050 b43_do_interrupt_thread(dev);
2051
2052 mutex_unlock(&wl->mutex);
2053 }
2054
b43_do_release_fw(struct b43_firmware_file * fw)2055 void b43_do_release_fw(struct b43_firmware_file *fw)
2056 {
2057 release_firmware(fw->data);
2058 fw->data = NULL;
2059 fw->filename = NULL;
2060 }
2061
b43_release_firmware(struct b43_wldev * dev)2062 static void b43_release_firmware(struct b43_wldev *dev)
2063 {
2064 b43_do_release_fw(&dev->fw.ucode);
2065 b43_do_release_fw(&dev->fw.pcm);
2066 b43_do_release_fw(&dev->fw.initvals);
2067 b43_do_release_fw(&dev->fw.initvals_band);
2068 }
2069
b43_print_fw_helptext(struct b43_wl * wl,bool error)2070 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2071 {
2072 const char text[] =
2073 "You must go to " \
2074 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2075 "and download the correct firmware for this driver version. " \
2076 "Please carefully read all instructions on this website.\n";
2077
2078 if (error)
2079 b43err(wl, text);
2080 else
2081 b43warn(wl, text);
2082 }
2083
b43_fw_cb(const struct firmware * firmware,void * context)2084 static void b43_fw_cb(const struct firmware *firmware, void *context)
2085 {
2086 struct b43_request_fw_context *ctx = context;
2087
2088 ctx->blob = firmware;
2089 complete(&ctx->fw_load_complete);
2090 }
2091
b43_do_request_fw(struct b43_request_fw_context * ctx,const char * name,struct b43_firmware_file * fw,bool async)2092 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2093 const char *name,
2094 struct b43_firmware_file *fw, bool async)
2095 {
2096 struct b43_fw_header *hdr;
2097 u32 size;
2098 int err;
2099
2100 if (!name) {
2101 /* Don't fetch anything. Free possibly cached firmware. */
2102 /* FIXME: We should probably keep it anyway, to save some headache
2103 * on suspend/resume with multiband devices. */
2104 b43_do_release_fw(fw);
2105 return 0;
2106 }
2107 if (fw->filename) {
2108 if ((fw->type == ctx->req_type) &&
2109 (strcmp(fw->filename, name) == 0))
2110 return 0; /* Already have this fw. */
2111 /* Free the cached firmware first. */
2112 /* FIXME: We should probably do this later after we successfully
2113 * got the new fw. This could reduce headache with multiband devices.
2114 * We could also redesign this to cache the firmware for all possible
2115 * bands all the time. */
2116 b43_do_release_fw(fw);
2117 }
2118
2119 switch (ctx->req_type) {
2120 case B43_FWTYPE_PROPRIETARY:
2121 snprintf(ctx->fwname, sizeof(ctx->fwname),
2122 "b43%s/%s.fw",
2123 modparam_fwpostfix, name);
2124 break;
2125 case B43_FWTYPE_OPENSOURCE:
2126 snprintf(ctx->fwname, sizeof(ctx->fwname),
2127 "b43-open%s/%s.fw",
2128 modparam_fwpostfix, name);
2129 break;
2130 default:
2131 B43_WARN_ON(1);
2132 return -ENOSYS;
2133 }
2134 if (async) {
2135 /* do this part asynchronously */
2136 init_completion(&ctx->fw_load_complete);
2137 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2138 ctx->dev->dev->dev, GFP_KERNEL,
2139 ctx, b43_fw_cb);
2140 if (err < 0) {
2141 pr_err("Unable to load firmware\n");
2142 return err;
2143 }
2144 /* stall here until fw ready */
2145 wait_for_completion(&ctx->fw_load_complete);
2146 if (ctx->blob)
2147 goto fw_ready;
2148 /* On some ARM systems, the async request will fail, but the next sync
2149 * request works. For this reason, we dall through here
2150 */
2151 }
2152 err = request_firmware(&ctx->blob, ctx->fwname,
2153 ctx->dev->dev->dev);
2154 if (err == -ENOENT) {
2155 snprintf(ctx->errors[ctx->req_type],
2156 sizeof(ctx->errors[ctx->req_type]),
2157 "Firmware file \"%s\" not found\n",
2158 ctx->fwname);
2159 return err;
2160 } else if (err) {
2161 snprintf(ctx->errors[ctx->req_type],
2162 sizeof(ctx->errors[ctx->req_type]),
2163 "Firmware file \"%s\" request failed (err=%d)\n",
2164 ctx->fwname, err);
2165 return err;
2166 }
2167 fw_ready:
2168 if (ctx->blob->size < sizeof(struct b43_fw_header))
2169 goto err_format;
2170 hdr = (struct b43_fw_header *)(ctx->blob->data);
2171 switch (hdr->type) {
2172 case B43_FW_TYPE_UCODE:
2173 case B43_FW_TYPE_PCM:
2174 size = be32_to_cpu(hdr->size);
2175 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
2176 goto err_format;
2177 /* fallthrough */
2178 case B43_FW_TYPE_IV:
2179 if (hdr->ver != 1)
2180 goto err_format;
2181 break;
2182 default:
2183 goto err_format;
2184 }
2185
2186 fw->data = ctx->blob;
2187 fw->filename = name;
2188 fw->type = ctx->req_type;
2189
2190 return 0;
2191
2192 err_format:
2193 snprintf(ctx->errors[ctx->req_type],
2194 sizeof(ctx->errors[ctx->req_type]),
2195 "Firmware file \"%s\" format error.\n", ctx->fwname);
2196 release_firmware(ctx->blob);
2197
2198 return -EPROTO;
2199 }
2200
b43_try_request_fw(struct b43_request_fw_context * ctx)2201 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2202 {
2203 struct b43_wldev *dev = ctx->dev;
2204 struct b43_firmware *fw = &ctx->dev->fw;
2205 const u8 rev = ctx->dev->dev->core_rev;
2206 const char *filename;
2207 u32 tmshigh;
2208 int err;
2209
2210 /* Files for HT and LCN were found by trying one by one */
2211
2212 /* Get microcode */
2213 if ((rev >= 5) && (rev <= 10)) {
2214 filename = "ucode5";
2215 } else if ((rev >= 11) && (rev <= 12)) {
2216 filename = "ucode11";
2217 } else if (rev == 13) {
2218 filename = "ucode13";
2219 } else if (rev == 14) {
2220 filename = "ucode14";
2221 } else if (rev == 15) {
2222 filename = "ucode15";
2223 } else {
2224 switch (dev->phy.type) {
2225 case B43_PHYTYPE_N:
2226 if (rev >= 16)
2227 filename = "ucode16_mimo";
2228 else
2229 goto err_no_ucode;
2230 break;
2231 case B43_PHYTYPE_HT:
2232 if (rev == 29)
2233 filename = "ucode29_mimo";
2234 else
2235 goto err_no_ucode;
2236 break;
2237 case B43_PHYTYPE_LCN:
2238 if (rev == 24)
2239 filename = "ucode24_mimo";
2240 else
2241 goto err_no_ucode;
2242 break;
2243 default:
2244 goto err_no_ucode;
2245 }
2246 }
2247 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
2248 if (err)
2249 goto err_load;
2250
2251 /* Get PCM code */
2252 if ((rev >= 5) && (rev <= 10))
2253 filename = "pcm5";
2254 else if (rev >= 11)
2255 filename = NULL;
2256 else
2257 goto err_no_pcm;
2258 fw->pcm_request_failed = false;
2259 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
2260 if (err == -ENOENT) {
2261 /* We did not find a PCM file? Not fatal, but
2262 * core rev <= 10 must do without hwcrypto then. */
2263 fw->pcm_request_failed = true;
2264 } else if (err)
2265 goto err_load;
2266
2267 /* Get initvals */
2268 switch (dev->phy.type) {
2269 case B43_PHYTYPE_A:
2270 if ((rev >= 5) && (rev <= 10)) {
2271 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2272 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2273 filename = "a0g1initvals5";
2274 else
2275 filename = "a0g0initvals5";
2276 } else
2277 goto err_no_initvals;
2278 break;
2279 case B43_PHYTYPE_G:
2280 if ((rev >= 5) && (rev <= 10))
2281 filename = "b0g0initvals5";
2282 else if (rev >= 13)
2283 filename = "b0g0initvals13";
2284 else
2285 goto err_no_initvals;
2286 break;
2287 case B43_PHYTYPE_N:
2288 if (rev >= 16)
2289 filename = "n0initvals16";
2290 else if ((rev >= 11) && (rev <= 12))
2291 filename = "n0initvals11";
2292 else
2293 goto err_no_initvals;
2294 break;
2295 case B43_PHYTYPE_LP:
2296 if (rev == 13)
2297 filename = "lp0initvals13";
2298 else if (rev == 14)
2299 filename = "lp0initvals14";
2300 else if (rev >= 15)
2301 filename = "lp0initvals15";
2302 else
2303 goto err_no_initvals;
2304 break;
2305 case B43_PHYTYPE_HT:
2306 if (rev == 29)
2307 filename = "ht0initvals29";
2308 else
2309 goto err_no_initvals;
2310 break;
2311 case B43_PHYTYPE_LCN:
2312 if (rev == 24)
2313 filename = "lcn0initvals24";
2314 else
2315 goto err_no_initvals;
2316 break;
2317 default:
2318 goto err_no_initvals;
2319 }
2320 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
2321 if (err)
2322 goto err_load;
2323
2324 /* Get bandswitch initvals */
2325 switch (dev->phy.type) {
2326 case B43_PHYTYPE_A:
2327 if ((rev >= 5) && (rev <= 10)) {
2328 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2329 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2330 filename = "a0g1bsinitvals5";
2331 else
2332 filename = "a0g0bsinitvals5";
2333 } else if (rev >= 11)
2334 filename = NULL;
2335 else
2336 goto err_no_initvals;
2337 break;
2338 case B43_PHYTYPE_G:
2339 if ((rev >= 5) && (rev <= 10))
2340 filename = "b0g0bsinitvals5";
2341 else if (rev >= 11)
2342 filename = NULL;
2343 else
2344 goto err_no_initvals;
2345 break;
2346 case B43_PHYTYPE_N:
2347 if (rev >= 16)
2348 filename = "n0bsinitvals16";
2349 else if ((rev >= 11) && (rev <= 12))
2350 filename = "n0bsinitvals11";
2351 else
2352 goto err_no_initvals;
2353 break;
2354 case B43_PHYTYPE_LP:
2355 if (rev == 13)
2356 filename = "lp0bsinitvals13";
2357 else if (rev == 14)
2358 filename = "lp0bsinitvals14";
2359 else if (rev >= 15)
2360 filename = "lp0bsinitvals15";
2361 else
2362 goto err_no_initvals;
2363 break;
2364 case B43_PHYTYPE_HT:
2365 if (rev == 29)
2366 filename = "ht0bsinitvals29";
2367 else
2368 goto err_no_initvals;
2369 break;
2370 case B43_PHYTYPE_LCN:
2371 if (rev == 24)
2372 filename = "lcn0bsinitvals24";
2373 else
2374 goto err_no_initvals;
2375 break;
2376 default:
2377 goto err_no_initvals;
2378 }
2379 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
2380 if (err)
2381 goto err_load;
2382
2383 return 0;
2384
2385 err_no_ucode:
2386 err = ctx->fatal_failure = -EOPNOTSUPP;
2387 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2388 "is required for your device (wl-core rev %u)\n", rev);
2389 goto error;
2390
2391 err_no_pcm:
2392 err = ctx->fatal_failure = -EOPNOTSUPP;
2393 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2394 "is required for your device (wl-core rev %u)\n", rev);
2395 goto error;
2396
2397 err_no_initvals:
2398 err = ctx->fatal_failure = -EOPNOTSUPP;
2399 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2400 "is required for your device (wl-core rev %u)\n", rev);
2401 goto error;
2402
2403 err_load:
2404 /* We failed to load this firmware image. The error message
2405 * already is in ctx->errors. Return and let our caller decide
2406 * what to do. */
2407 goto error;
2408
2409 error:
2410 b43_release_firmware(dev);
2411 return err;
2412 }
2413
2414 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2415 static void b43_one_core_detach(struct b43_bus_dev *dev);
2416
b43_request_firmware(struct work_struct * work)2417 static void b43_request_firmware(struct work_struct *work)
2418 {
2419 struct b43_wl *wl = container_of(work,
2420 struct b43_wl, firmware_load);
2421 struct b43_wldev *dev = wl->current_dev;
2422 struct b43_request_fw_context *ctx;
2423 unsigned int i;
2424 int err;
2425 const char *errmsg;
2426
2427 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2428 if (!ctx)
2429 return;
2430 ctx->dev = dev;
2431
2432 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2433 err = b43_try_request_fw(ctx);
2434 if (!err)
2435 goto start_ieee80211; /* Successfully loaded it. */
2436 /* Was fw version known? */
2437 if (ctx->fatal_failure)
2438 goto out;
2439
2440 /* proprietary fw not found, try open source */
2441 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2442 err = b43_try_request_fw(ctx);
2443 if (!err)
2444 goto start_ieee80211; /* Successfully loaded it. */
2445 if(ctx->fatal_failure)
2446 goto out;
2447
2448 /* Could not find a usable firmware. Print the errors. */
2449 for (i = 0; i < B43_NR_FWTYPES; i++) {
2450 errmsg = ctx->errors[i];
2451 if (strlen(errmsg))
2452 b43err(dev->wl, "%s", errmsg);
2453 }
2454 b43_print_fw_helptext(dev->wl, 1);
2455 goto out;
2456
2457 start_ieee80211:
2458 err = ieee80211_register_hw(wl->hw);
2459 if (err)
2460 goto err_one_core_detach;
2461 b43_leds_register(wl->current_dev);
2462 goto out;
2463
2464 err_one_core_detach:
2465 b43_one_core_detach(dev->dev);
2466
2467 out:
2468 kfree(ctx);
2469 }
2470
b43_upload_microcode(struct b43_wldev * dev)2471 static int b43_upload_microcode(struct b43_wldev *dev)
2472 {
2473 struct wiphy *wiphy = dev->wl->hw->wiphy;
2474 const size_t hdr_len = sizeof(struct b43_fw_header);
2475 const __be32 *data;
2476 unsigned int i, len;
2477 u16 fwrev, fwpatch, fwdate, fwtime;
2478 u32 tmp, macctl;
2479 int err = 0;
2480
2481 /* Jump the microcode PSM to offset 0 */
2482 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2483 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2484 macctl |= B43_MACCTL_PSM_JMP0;
2485 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2486 /* Zero out all microcode PSM registers and shared memory. */
2487 for (i = 0; i < 64; i++)
2488 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2489 for (i = 0; i < 4096; i += 2)
2490 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2491
2492 /* Upload Microcode. */
2493 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2494 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2495 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2496 for (i = 0; i < len; i++) {
2497 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2498 udelay(10);
2499 }
2500
2501 if (dev->fw.pcm.data) {
2502 /* Upload PCM data. */
2503 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2504 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2505 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2506 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2507 /* No need for autoinc bit in SHM_HW */
2508 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2509 for (i = 0; i < len; i++) {
2510 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2511 udelay(10);
2512 }
2513 }
2514
2515 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2516
2517 /* Start the microcode PSM */
2518 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2519 B43_MACCTL_PSM_RUN);
2520
2521 /* Wait for the microcode to load and respond */
2522 i = 0;
2523 while (1) {
2524 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2525 if (tmp == B43_IRQ_MAC_SUSPENDED)
2526 break;
2527 i++;
2528 if (i >= 20) {
2529 b43err(dev->wl, "Microcode not responding\n");
2530 b43_print_fw_helptext(dev->wl, 1);
2531 err = -ENODEV;
2532 goto error;
2533 }
2534 msleep(50);
2535 }
2536 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2537
2538 /* Get and check the revisions. */
2539 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2540 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2541 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2542 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2543
2544 if (fwrev <= 0x128) {
2545 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2546 "binary drivers older than version 4.x is unsupported. "
2547 "You must upgrade your firmware files.\n");
2548 b43_print_fw_helptext(dev->wl, 1);
2549 err = -EOPNOTSUPP;
2550 goto error;
2551 }
2552 dev->fw.rev = fwrev;
2553 dev->fw.patch = fwpatch;
2554 if (dev->fw.rev >= 598)
2555 dev->fw.hdr_format = B43_FW_HDR_598;
2556 else if (dev->fw.rev >= 410)
2557 dev->fw.hdr_format = B43_FW_HDR_410;
2558 else
2559 dev->fw.hdr_format = B43_FW_HDR_351;
2560 dev->fw.opensource = (fwdate == 0xFFFF);
2561
2562 /* Default to use-all-queues. */
2563 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2564 dev->qos_enabled = !!modparam_qos;
2565 /* Default to firmware/hardware crypto acceleration. */
2566 dev->hwcrypto_enabled = true;
2567
2568 if (dev->fw.opensource) {
2569 u16 fwcapa;
2570
2571 /* Patchlevel info is encoded in the "time" field. */
2572 dev->fw.patch = fwtime;
2573 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2574 dev->fw.rev, dev->fw.patch);
2575
2576 fwcapa = b43_fwcapa_read(dev);
2577 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2578 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2579 /* Disable hardware crypto and fall back to software crypto. */
2580 dev->hwcrypto_enabled = false;
2581 }
2582 if (!(fwcapa & B43_FWCAPA_QOS)) {
2583 b43info(dev->wl, "QoS not supported by firmware\n");
2584 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2585 * ieee80211_unregister to make sure the networking core can
2586 * properly free possible resources. */
2587 dev->wl->hw->queues = 1;
2588 dev->qos_enabled = false;
2589 }
2590 } else {
2591 b43info(dev->wl, "Loading firmware version %u.%u "
2592 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2593 fwrev, fwpatch,
2594 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2595 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2596 if (dev->fw.pcm_request_failed) {
2597 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2598 "Hardware accelerated cryptography is disabled.\n");
2599 b43_print_fw_helptext(dev->wl, 0);
2600 }
2601 }
2602
2603 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2604 dev->fw.rev, dev->fw.patch);
2605 wiphy->hw_version = dev->dev->core_id;
2606
2607 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2608 /* We're over the deadline, but we keep support for old fw
2609 * until it turns out to be in major conflict with something new. */
2610 b43warn(dev->wl, "You are using an old firmware image. "
2611 "Support for old firmware will be removed soon "
2612 "(official deadline was July 2008).\n");
2613 b43_print_fw_helptext(dev->wl, 0);
2614 }
2615
2616 return 0;
2617
2618 error:
2619 /* Stop the microcode PSM. */
2620 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2621 B43_MACCTL_PSM_JMP0);
2622
2623 return err;
2624 }
2625
b43_write_initvals(struct b43_wldev * dev,const struct b43_iv * ivals,size_t count,size_t array_size)2626 static int b43_write_initvals(struct b43_wldev *dev,
2627 const struct b43_iv *ivals,
2628 size_t count,
2629 size_t array_size)
2630 {
2631 const struct b43_iv *iv;
2632 u16 offset;
2633 size_t i;
2634 bool bit32;
2635
2636 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2637 iv = ivals;
2638 for (i = 0; i < count; i++) {
2639 if (array_size < sizeof(iv->offset_size))
2640 goto err_format;
2641 array_size -= sizeof(iv->offset_size);
2642 offset = be16_to_cpu(iv->offset_size);
2643 bit32 = !!(offset & B43_IV_32BIT);
2644 offset &= B43_IV_OFFSET_MASK;
2645 if (offset >= 0x1000)
2646 goto err_format;
2647 if (bit32) {
2648 u32 value;
2649
2650 if (array_size < sizeof(iv->data.d32))
2651 goto err_format;
2652 array_size -= sizeof(iv->data.d32);
2653
2654 value = get_unaligned_be32(&iv->data.d32);
2655 b43_write32(dev, offset, value);
2656
2657 iv = (const struct b43_iv *)((const uint8_t *)iv +
2658 sizeof(__be16) +
2659 sizeof(__be32));
2660 } else {
2661 u16 value;
2662
2663 if (array_size < sizeof(iv->data.d16))
2664 goto err_format;
2665 array_size -= sizeof(iv->data.d16);
2666
2667 value = be16_to_cpu(iv->data.d16);
2668 b43_write16(dev, offset, value);
2669
2670 iv = (const struct b43_iv *)((const uint8_t *)iv +
2671 sizeof(__be16) +
2672 sizeof(__be16));
2673 }
2674 }
2675 if (array_size)
2676 goto err_format;
2677
2678 return 0;
2679
2680 err_format:
2681 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2682 b43_print_fw_helptext(dev->wl, 1);
2683
2684 return -EPROTO;
2685 }
2686
b43_upload_initvals(struct b43_wldev * dev)2687 static int b43_upload_initvals(struct b43_wldev *dev)
2688 {
2689 const size_t hdr_len = sizeof(struct b43_fw_header);
2690 const struct b43_fw_header *hdr;
2691 struct b43_firmware *fw = &dev->fw;
2692 const struct b43_iv *ivals;
2693 size_t count;
2694 int err;
2695
2696 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2697 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2698 count = be32_to_cpu(hdr->size);
2699 err = b43_write_initvals(dev, ivals, count,
2700 fw->initvals.data->size - hdr_len);
2701 if (err)
2702 goto out;
2703 if (fw->initvals_band.data) {
2704 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2705 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2706 count = be32_to_cpu(hdr->size);
2707 err = b43_write_initvals(dev, ivals, count,
2708 fw->initvals_band.data->size - hdr_len);
2709 if (err)
2710 goto out;
2711 }
2712 out:
2713
2714 return err;
2715 }
2716
2717 /* Initialize the GPIOs
2718 * http://bcm-specs.sipsolutions.net/GPIO
2719 */
b43_ssb_gpio_dev(struct b43_wldev * dev)2720 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2721 {
2722 struct ssb_bus *bus = dev->dev->sdev->bus;
2723
2724 #ifdef CONFIG_SSB_DRIVER_PCICORE
2725 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2726 #else
2727 return bus->chipco.dev;
2728 #endif
2729 }
2730
b43_gpio_init(struct b43_wldev * dev)2731 static int b43_gpio_init(struct b43_wldev *dev)
2732 {
2733 struct ssb_device *gpiodev;
2734 u32 mask, set;
2735
2736 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2737 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2738
2739 mask = 0x0000001F;
2740 set = 0x0000000F;
2741 if (dev->dev->chip_id == 0x4301) {
2742 mask |= 0x0060;
2743 set |= 0x0060;
2744 }
2745 if (dev->dev->chip_id == 0x5354)
2746 set &= 0xff02;
2747 if (0 /* FIXME: conditional unknown */ ) {
2748 b43_write16(dev, B43_MMIO_GPIO_MASK,
2749 b43_read16(dev, B43_MMIO_GPIO_MASK)
2750 | 0x0100);
2751 mask |= 0x0180;
2752 set |= 0x0180;
2753 }
2754 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2755 b43_write16(dev, B43_MMIO_GPIO_MASK,
2756 b43_read16(dev, B43_MMIO_GPIO_MASK)
2757 | 0x0200);
2758 mask |= 0x0200;
2759 set |= 0x0200;
2760 }
2761 if (dev->dev->core_rev >= 2)
2762 mask |= 0x0010; /* FIXME: This is redundant. */
2763
2764 switch (dev->dev->bus_type) {
2765 #ifdef CONFIG_B43_BCMA
2766 case B43_BUS_BCMA:
2767 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2768 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2769 BCMA_CC_GPIOCTL) & mask) | set);
2770 break;
2771 #endif
2772 #ifdef CONFIG_B43_SSB
2773 case B43_BUS_SSB:
2774 gpiodev = b43_ssb_gpio_dev(dev);
2775 if (gpiodev)
2776 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2777 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2778 & mask) | set);
2779 break;
2780 #endif
2781 }
2782
2783 return 0;
2784 }
2785
2786 /* Turn off all GPIO stuff. Call this on module unload, for example. */
b43_gpio_cleanup(struct b43_wldev * dev)2787 static void b43_gpio_cleanup(struct b43_wldev *dev)
2788 {
2789 struct ssb_device *gpiodev;
2790
2791 switch (dev->dev->bus_type) {
2792 #ifdef CONFIG_B43_BCMA
2793 case B43_BUS_BCMA:
2794 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2795 0);
2796 break;
2797 #endif
2798 #ifdef CONFIG_B43_SSB
2799 case B43_BUS_SSB:
2800 gpiodev = b43_ssb_gpio_dev(dev);
2801 if (gpiodev)
2802 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2803 break;
2804 #endif
2805 }
2806 }
2807
2808 /* http://bcm-specs.sipsolutions.net/EnableMac */
b43_mac_enable(struct b43_wldev * dev)2809 void b43_mac_enable(struct b43_wldev *dev)
2810 {
2811 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2812 u16 fwstate;
2813
2814 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2815 B43_SHM_SH_UCODESTAT);
2816 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2817 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2818 b43err(dev->wl, "b43_mac_enable(): The firmware "
2819 "should be suspended, but current state is %u\n",
2820 fwstate);
2821 }
2822 }
2823
2824 dev->mac_suspended--;
2825 B43_WARN_ON(dev->mac_suspended < 0);
2826 if (dev->mac_suspended == 0) {
2827 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2828 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2829 B43_IRQ_MAC_SUSPENDED);
2830 /* Commit writes */
2831 b43_read32(dev, B43_MMIO_MACCTL);
2832 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2833 b43_power_saving_ctl_bits(dev, 0);
2834 }
2835 }
2836
2837 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
b43_mac_suspend(struct b43_wldev * dev)2838 void b43_mac_suspend(struct b43_wldev *dev)
2839 {
2840 int i;
2841 u32 tmp;
2842
2843 might_sleep();
2844 B43_WARN_ON(dev->mac_suspended < 0);
2845
2846 if (dev->mac_suspended == 0) {
2847 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2848 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2849 /* force pci to flush the write */
2850 b43_read32(dev, B43_MMIO_MACCTL);
2851 for (i = 35; i; i--) {
2852 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2853 if (tmp & B43_IRQ_MAC_SUSPENDED)
2854 goto out;
2855 udelay(10);
2856 }
2857 /* Hm, it seems this will take some time. Use msleep(). */
2858 for (i = 40; i; i--) {
2859 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2860 if (tmp & B43_IRQ_MAC_SUSPENDED)
2861 goto out;
2862 msleep(1);
2863 }
2864 b43err(dev->wl, "MAC suspend failed\n");
2865 }
2866 out:
2867 dev->mac_suspended++;
2868 }
2869
2870 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
b43_mac_phy_clock_set(struct b43_wldev * dev,bool on)2871 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2872 {
2873 u32 tmp;
2874
2875 switch (dev->dev->bus_type) {
2876 #ifdef CONFIG_B43_BCMA
2877 case B43_BUS_BCMA:
2878 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2879 if (on)
2880 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2881 else
2882 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2883 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2884 break;
2885 #endif
2886 #ifdef CONFIG_B43_SSB
2887 case B43_BUS_SSB:
2888 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2889 if (on)
2890 tmp |= B43_TMSLOW_MACPHYCLKEN;
2891 else
2892 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2893 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2894 break;
2895 #endif
2896 }
2897 }
2898
b43_adjust_opmode(struct b43_wldev * dev)2899 static void b43_adjust_opmode(struct b43_wldev *dev)
2900 {
2901 struct b43_wl *wl = dev->wl;
2902 u32 ctl;
2903 u16 cfp_pretbtt;
2904
2905 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2906 /* Reset status to STA infrastructure mode. */
2907 ctl &= ~B43_MACCTL_AP;
2908 ctl &= ~B43_MACCTL_KEEP_CTL;
2909 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2910 ctl &= ~B43_MACCTL_KEEP_BAD;
2911 ctl &= ~B43_MACCTL_PROMISC;
2912 ctl &= ~B43_MACCTL_BEACPROMISC;
2913 ctl |= B43_MACCTL_INFRA;
2914
2915 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2916 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2917 ctl |= B43_MACCTL_AP;
2918 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2919 ctl &= ~B43_MACCTL_INFRA;
2920
2921 if (wl->filter_flags & FIF_CONTROL)
2922 ctl |= B43_MACCTL_KEEP_CTL;
2923 if (wl->filter_flags & FIF_FCSFAIL)
2924 ctl |= B43_MACCTL_KEEP_BAD;
2925 if (wl->filter_flags & FIF_PLCPFAIL)
2926 ctl |= B43_MACCTL_KEEP_BADPLCP;
2927 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2928 ctl |= B43_MACCTL_PROMISC;
2929 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2930 ctl |= B43_MACCTL_BEACPROMISC;
2931
2932 /* Workaround: On old hardware the HW-MAC-address-filter
2933 * doesn't work properly, so always run promisc in filter
2934 * it in software. */
2935 if (dev->dev->core_rev <= 4)
2936 ctl |= B43_MACCTL_PROMISC;
2937
2938 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2939
2940 cfp_pretbtt = 2;
2941 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2942 if (dev->dev->chip_id == 0x4306 &&
2943 dev->dev->chip_rev == 3)
2944 cfp_pretbtt = 100;
2945 else
2946 cfp_pretbtt = 50;
2947 }
2948 b43_write16(dev, 0x612, cfp_pretbtt);
2949
2950 /* FIXME: We don't currently implement the PMQ mechanism,
2951 * so always disable it. If we want to implement PMQ,
2952 * we need to enable it here (clear DISCPMQ) in AP mode.
2953 */
2954 if (0 /* ctl & B43_MACCTL_AP */)
2955 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
2956 else
2957 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
2958 }
2959
b43_rate_memory_write(struct b43_wldev * dev,u16 rate,int is_ofdm)2960 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2961 {
2962 u16 offset;
2963
2964 if (is_ofdm) {
2965 offset = 0x480;
2966 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2967 } else {
2968 offset = 0x4C0;
2969 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2970 }
2971 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2972 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2973 }
2974
b43_rate_memory_init(struct b43_wldev * dev)2975 static void b43_rate_memory_init(struct b43_wldev *dev)
2976 {
2977 switch (dev->phy.type) {
2978 case B43_PHYTYPE_A:
2979 case B43_PHYTYPE_G:
2980 case B43_PHYTYPE_N:
2981 case B43_PHYTYPE_LP:
2982 case B43_PHYTYPE_HT:
2983 case B43_PHYTYPE_LCN:
2984 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2985 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2986 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2987 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2988 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2989 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2990 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2991 if (dev->phy.type == B43_PHYTYPE_A)
2992 break;
2993 /* fallthrough */
2994 case B43_PHYTYPE_B:
2995 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2996 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2997 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2998 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2999 break;
3000 default:
3001 B43_WARN_ON(1);
3002 }
3003 }
3004
3005 /* Set the default values for the PHY TX Control Words. */
b43_set_phytxctl_defaults(struct b43_wldev * dev)3006 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3007 {
3008 u16 ctl = 0;
3009
3010 ctl |= B43_TXH_PHY_ENC_CCK;
3011 ctl |= B43_TXH_PHY_ANT01AUTO;
3012 ctl |= B43_TXH_PHY_TXPWR;
3013
3014 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3015 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3016 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3017 }
3018
3019 /* Set the TX-Antenna for management frames sent by firmware. */
b43_mgmtframe_txantenna(struct b43_wldev * dev,int antenna)3020 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3021 {
3022 u16 ant;
3023 u16 tmp;
3024
3025 ant = b43_antenna_to_phyctl(antenna);
3026
3027 /* For ACK/CTS */
3028 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3029 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3030 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3031 /* For Probe Resposes */
3032 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3033 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3034 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3035 }
3036
3037 /* This is the opposite of b43_chip_init() */
b43_chip_exit(struct b43_wldev * dev)3038 static void b43_chip_exit(struct b43_wldev *dev)
3039 {
3040 b43_phy_exit(dev);
3041 b43_gpio_cleanup(dev);
3042 /* firmware is released later */
3043 }
3044
3045 /* Initialize the chip
3046 * http://bcm-specs.sipsolutions.net/ChipInit
3047 */
b43_chip_init(struct b43_wldev * dev)3048 static int b43_chip_init(struct b43_wldev *dev)
3049 {
3050 struct b43_phy *phy = &dev->phy;
3051 int err;
3052 u32 macctl;
3053 u16 value16;
3054
3055 /* Initialize the MAC control */
3056 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3057 if (dev->phy.gmode)
3058 macctl |= B43_MACCTL_GMODE;
3059 macctl |= B43_MACCTL_INFRA;
3060 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3061
3062 err = b43_upload_microcode(dev);
3063 if (err)
3064 goto out; /* firmware is released later */
3065
3066 err = b43_gpio_init(dev);
3067 if (err)
3068 goto out; /* firmware is released later */
3069
3070 err = b43_upload_initvals(dev);
3071 if (err)
3072 goto err_gpio_clean;
3073
3074 /* Turn the Analog on and initialize the PHY. */
3075 phy->ops->switch_analog(dev, 1);
3076 err = b43_phy_init(dev);
3077 if (err)
3078 goto err_gpio_clean;
3079
3080 /* Disable Interference Mitigation. */
3081 if (phy->ops->interf_mitigation)
3082 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3083
3084 /* Select the antennae */
3085 if (phy->ops->set_rx_antenna)
3086 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3087 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3088
3089 if (phy->type == B43_PHYTYPE_B) {
3090 value16 = b43_read16(dev, 0x005E);
3091 value16 |= 0x0004;
3092 b43_write16(dev, 0x005E, value16);
3093 }
3094 b43_write32(dev, 0x0100, 0x01000000);
3095 if (dev->dev->core_rev < 5)
3096 b43_write32(dev, 0x010C, 0x01000000);
3097
3098 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3099 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3100
3101 /* Probe Response Timeout value */
3102 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3103 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3104
3105 /* Initially set the wireless operation mode. */
3106 b43_adjust_opmode(dev);
3107
3108 if (dev->dev->core_rev < 3) {
3109 b43_write16(dev, 0x060E, 0x0000);
3110 b43_write16(dev, 0x0610, 0x8000);
3111 b43_write16(dev, 0x0604, 0x0000);
3112 b43_write16(dev, 0x0606, 0x0200);
3113 } else {
3114 b43_write32(dev, 0x0188, 0x80000000);
3115 b43_write32(dev, 0x018C, 0x02000000);
3116 }
3117 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3118 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
3119 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3120 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3121 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3122 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3123 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3124
3125 b43_mac_phy_clock_set(dev, true);
3126
3127 switch (dev->dev->bus_type) {
3128 #ifdef CONFIG_B43_BCMA
3129 case B43_BUS_BCMA:
3130 /* FIXME: 0xE74 is quite common, but should be read from CC */
3131 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3132 break;
3133 #endif
3134 #ifdef CONFIG_B43_SSB
3135 case B43_BUS_SSB:
3136 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3137 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3138 break;
3139 #endif
3140 }
3141
3142 err = 0;
3143 b43dbg(dev->wl, "Chip initialized\n");
3144 out:
3145 return err;
3146
3147 err_gpio_clean:
3148 b43_gpio_cleanup(dev);
3149 return err;
3150 }
3151
b43_periodic_every60sec(struct b43_wldev * dev)3152 static void b43_periodic_every60sec(struct b43_wldev *dev)
3153 {
3154 const struct b43_phy_operations *ops = dev->phy.ops;
3155
3156 if (ops->pwork_60sec)
3157 ops->pwork_60sec(dev);
3158
3159 /* Force check the TX power emission now. */
3160 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3161 }
3162
b43_periodic_every30sec(struct b43_wldev * dev)3163 static void b43_periodic_every30sec(struct b43_wldev *dev)
3164 {
3165 /* Update device statistics. */
3166 b43_calculate_link_quality(dev);
3167 }
3168
b43_periodic_every15sec(struct b43_wldev * dev)3169 static void b43_periodic_every15sec(struct b43_wldev *dev)
3170 {
3171 struct b43_phy *phy = &dev->phy;
3172 u16 wdr;
3173
3174 if (dev->fw.opensource) {
3175 /* Check if the firmware is still alive.
3176 * It will reset the watchdog counter to 0 in its idle loop. */
3177 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3178 if (unlikely(wdr)) {
3179 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3180 b43_controller_restart(dev, "Firmware watchdog");
3181 return;
3182 } else {
3183 b43_shm_write16(dev, B43_SHM_SCRATCH,
3184 B43_WATCHDOG_REG, 1);
3185 }
3186 }
3187
3188 if (phy->ops->pwork_15sec)
3189 phy->ops->pwork_15sec(dev);
3190
3191 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3192 wmb();
3193
3194 #if B43_DEBUG
3195 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3196 unsigned int i;
3197
3198 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3199 dev->irq_count / 15,
3200 dev->tx_count / 15,
3201 dev->rx_count / 15);
3202 dev->irq_count = 0;
3203 dev->tx_count = 0;
3204 dev->rx_count = 0;
3205 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3206 if (dev->irq_bit_count[i]) {
3207 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3208 dev->irq_bit_count[i] / 15, i, (1 << i));
3209 dev->irq_bit_count[i] = 0;
3210 }
3211 }
3212 }
3213 #endif
3214 }
3215
do_periodic_work(struct b43_wldev * dev)3216 static void do_periodic_work(struct b43_wldev *dev)
3217 {
3218 unsigned int state;
3219
3220 state = dev->periodic_state;
3221 if (state % 4 == 0)
3222 b43_periodic_every60sec(dev);
3223 if (state % 2 == 0)
3224 b43_periodic_every30sec(dev);
3225 b43_periodic_every15sec(dev);
3226 }
3227
3228 /* Periodic work locking policy:
3229 * The whole periodic work handler is protected by
3230 * wl->mutex. If another lock is needed somewhere in the
3231 * pwork callchain, it's acquired in-place, where it's needed.
3232 */
b43_periodic_work_handler(struct work_struct * work)3233 static void b43_periodic_work_handler(struct work_struct *work)
3234 {
3235 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3236 periodic_work.work);
3237 struct b43_wl *wl = dev->wl;
3238 unsigned long delay;
3239
3240 mutex_lock(&wl->mutex);
3241
3242 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3243 goto out;
3244 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3245 goto out_requeue;
3246
3247 do_periodic_work(dev);
3248
3249 dev->periodic_state++;
3250 out_requeue:
3251 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3252 delay = msecs_to_jiffies(50);
3253 else
3254 delay = round_jiffies_relative(HZ * 15);
3255 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3256 out:
3257 mutex_unlock(&wl->mutex);
3258 }
3259
b43_periodic_tasks_setup(struct b43_wldev * dev)3260 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3261 {
3262 struct delayed_work *work = &dev->periodic_work;
3263
3264 dev->periodic_state = 0;
3265 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3266 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3267 }
3268
3269 /* Check if communication with the device works correctly. */
b43_validate_chipaccess(struct b43_wldev * dev)3270 static int b43_validate_chipaccess(struct b43_wldev *dev)
3271 {
3272 u32 v, backup0, backup4;
3273
3274 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3275 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3276
3277 /* Check for read/write and endianness problems. */
3278 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3279 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3280 goto error;
3281 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3282 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3283 goto error;
3284
3285 /* Check if unaligned 32bit SHM_SHARED access works properly.
3286 * However, don't bail out on failure, because it's noncritical. */
3287 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3288 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3289 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3290 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3291 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3292 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3293 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3294 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3295 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3296 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3297 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3298 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3299
3300 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3301 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3302
3303 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3304 /* The 32bit register shadows the two 16bit registers
3305 * with update sideeffects. Validate this. */
3306 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3307 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3308 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3309 goto error;
3310 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3311 goto error;
3312 }
3313 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3314
3315 v = b43_read32(dev, B43_MMIO_MACCTL);
3316 v |= B43_MACCTL_GMODE;
3317 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3318 goto error;
3319
3320 return 0;
3321 error:
3322 b43err(dev->wl, "Failed to validate the chipaccess\n");
3323 return -ENODEV;
3324 }
3325
b43_security_init(struct b43_wldev * dev)3326 static void b43_security_init(struct b43_wldev *dev)
3327 {
3328 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3329 /* KTP is a word address, but we address SHM bytewise.
3330 * So multiply by two.
3331 */
3332 dev->ktp *= 2;
3333 /* Number of RCMTA address slots */
3334 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3335 /* Clear the key memory. */
3336 b43_clear_keys(dev);
3337 }
3338
3339 #ifdef CONFIG_B43_HWRNG
b43_rng_read(struct hwrng * rng,u32 * data)3340 static int b43_rng_read(struct hwrng *rng, u32 *data)
3341 {
3342 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3343 struct b43_wldev *dev;
3344 int count = -ENODEV;
3345
3346 mutex_lock(&wl->mutex);
3347 dev = wl->current_dev;
3348 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3349 *data = b43_read16(dev, B43_MMIO_RNG);
3350 count = sizeof(u16);
3351 }
3352 mutex_unlock(&wl->mutex);
3353
3354 return count;
3355 }
3356 #endif /* CONFIG_B43_HWRNG */
3357
b43_rng_exit(struct b43_wl * wl)3358 static void b43_rng_exit(struct b43_wl *wl)
3359 {
3360 #ifdef CONFIG_B43_HWRNG
3361 if (wl->rng_initialized)
3362 hwrng_unregister(&wl->rng);
3363 #endif /* CONFIG_B43_HWRNG */
3364 }
3365
b43_rng_init(struct b43_wl * wl)3366 static int b43_rng_init(struct b43_wl *wl)
3367 {
3368 int err = 0;
3369
3370 #ifdef CONFIG_B43_HWRNG
3371 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3372 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3373 wl->rng.name = wl->rng_name;
3374 wl->rng.data_read = b43_rng_read;
3375 wl->rng.priv = (unsigned long)wl;
3376 wl->rng_initialized = true;
3377 err = hwrng_register(&wl->rng);
3378 if (err) {
3379 wl->rng_initialized = false;
3380 b43err(wl, "Failed to register the random "
3381 "number generator (%d)\n", err);
3382 }
3383 #endif /* CONFIG_B43_HWRNG */
3384
3385 return err;
3386 }
3387
b43_tx_work(struct work_struct * work)3388 static void b43_tx_work(struct work_struct *work)
3389 {
3390 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3391 struct b43_wldev *dev;
3392 struct sk_buff *skb;
3393 int queue_num;
3394 int err = 0;
3395
3396 mutex_lock(&wl->mutex);
3397 dev = wl->current_dev;
3398 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3399 mutex_unlock(&wl->mutex);
3400 return;
3401 }
3402
3403 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3404 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3405 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3406 if (b43_using_pio_transfers(dev))
3407 err = b43_pio_tx(dev, skb);
3408 else
3409 err = b43_dma_tx(dev, skb);
3410 if (err == -ENOSPC) {
3411 wl->tx_queue_stopped[queue_num] = 1;
3412 ieee80211_stop_queue(wl->hw, queue_num);
3413 skb_queue_head(&wl->tx_queue[queue_num], skb);
3414 break;
3415 }
3416 if (unlikely(err))
3417 ieee80211_free_txskb(wl->hw, skb);
3418 err = 0;
3419 }
3420
3421 if (!err)
3422 wl->tx_queue_stopped[queue_num] = 0;
3423 }
3424
3425 #if B43_DEBUG
3426 dev->tx_count++;
3427 #endif
3428 mutex_unlock(&wl->mutex);
3429 }
3430
b43_op_tx(struct ieee80211_hw * hw,struct sk_buff * skb)3431 static void b43_op_tx(struct ieee80211_hw *hw,
3432 struct sk_buff *skb)
3433 {
3434 struct b43_wl *wl = hw_to_b43_wl(hw);
3435
3436 if (unlikely(skb->len < 2 + 2 + 6)) {
3437 /* Too short, this can't be a valid frame. */
3438 ieee80211_free_txskb(hw, skb);
3439 return;
3440 }
3441 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3442
3443 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3444 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3445 ieee80211_queue_work(wl->hw, &wl->tx_work);
3446 } else {
3447 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3448 }
3449 }
3450
b43_qos_params_upload(struct b43_wldev * dev,const struct ieee80211_tx_queue_params * p,u16 shm_offset)3451 static void b43_qos_params_upload(struct b43_wldev *dev,
3452 const struct ieee80211_tx_queue_params *p,
3453 u16 shm_offset)
3454 {
3455 u16 params[B43_NR_QOSPARAMS];
3456 int bslots, tmp;
3457 unsigned int i;
3458
3459 if (!dev->qos_enabled)
3460 return;
3461
3462 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3463
3464 memset(¶ms, 0, sizeof(params));
3465
3466 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3467 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3468 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3469 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3470 params[B43_QOSPARAM_AIFS] = p->aifs;
3471 params[B43_QOSPARAM_BSLOTS] = bslots;
3472 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3473
3474 for (i = 0; i < ARRAY_SIZE(params); i++) {
3475 if (i == B43_QOSPARAM_STATUS) {
3476 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3477 shm_offset + (i * 2));
3478 /* Mark the parameters as updated. */
3479 tmp |= 0x100;
3480 b43_shm_write16(dev, B43_SHM_SHARED,
3481 shm_offset + (i * 2),
3482 tmp);
3483 } else {
3484 b43_shm_write16(dev, B43_SHM_SHARED,
3485 shm_offset + (i * 2),
3486 params[i]);
3487 }
3488 }
3489 }
3490
3491 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3492 static const u16 b43_qos_shm_offsets[] = {
3493 /* [mac80211-queue-nr] = SHM_OFFSET, */
3494 [0] = B43_QOS_VOICE,
3495 [1] = B43_QOS_VIDEO,
3496 [2] = B43_QOS_BESTEFFORT,
3497 [3] = B43_QOS_BACKGROUND,
3498 };
3499
3500 /* Update all QOS parameters in hardware. */
b43_qos_upload_all(struct b43_wldev * dev)3501 static void b43_qos_upload_all(struct b43_wldev *dev)
3502 {
3503 struct b43_wl *wl = dev->wl;
3504 struct b43_qos_params *params;
3505 unsigned int i;
3506
3507 if (!dev->qos_enabled)
3508 return;
3509
3510 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3511 ARRAY_SIZE(wl->qos_params));
3512
3513 b43_mac_suspend(dev);
3514 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3515 params = &(wl->qos_params[i]);
3516 b43_qos_params_upload(dev, &(params->p),
3517 b43_qos_shm_offsets[i]);
3518 }
3519 b43_mac_enable(dev);
3520 }
3521
b43_qos_clear(struct b43_wl * wl)3522 static void b43_qos_clear(struct b43_wl *wl)
3523 {
3524 struct b43_qos_params *params;
3525 unsigned int i;
3526
3527 /* Initialize QoS parameters to sane defaults. */
3528
3529 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3530 ARRAY_SIZE(wl->qos_params));
3531
3532 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3533 params = &(wl->qos_params[i]);
3534
3535 switch (b43_qos_shm_offsets[i]) {
3536 case B43_QOS_VOICE:
3537 params->p.txop = 0;
3538 params->p.aifs = 2;
3539 params->p.cw_min = 0x0001;
3540 params->p.cw_max = 0x0001;
3541 break;
3542 case B43_QOS_VIDEO:
3543 params->p.txop = 0;
3544 params->p.aifs = 2;
3545 params->p.cw_min = 0x0001;
3546 params->p.cw_max = 0x0001;
3547 break;
3548 case B43_QOS_BESTEFFORT:
3549 params->p.txop = 0;
3550 params->p.aifs = 3;
3551 params->p.cw_min = 0x0001;
3552 params->p.cw_max = 0x03FF;
3553 break;
3554 case B43_QOS_BACKGROUND:
3555 params->p.txop = 0;
3556 params->p.aifs = 7;
3557 params->p.cw_min = 0x0001;
3558 params->p.cw_max = 0x03FF;
3559 break;
3560 default:
3561 B43_WARN_ON(1);
3562 }
3563 }
3564 }
3565
3566 /* Initialize the core's QOS capabilities */
b43_qos_init(struct b43_wldev * dev)3567 static void b43_qos_init(struct b43_wldev *dev)
3568 {
3569 if (!dev->qos_enabled) {
3570 /* Disable QOS support. */
3571 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3572 b43_write16(dev, B43_MMIO_IFSCTL,
3573 b43_read16(dev, B43_MMIO_IFSCTL)
3574 & ~B43_MMIO_IFSCTL_USE_EDCF);
3575 b43dbg(dev->wl, "QoS disabled\n");
3576 return;
3577 }
3578
3579 /* Upload the current QOS parameters. */
3580 b43_qos_upload_all(dev);
3581
3582 /* Enable QOS support. */
3583 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3584 b43_write16(dev, B43_MMIO_IFSCTL,
3585 b43_read16(dev, B43_MMIO_IFSCTL)
3586 | B43_MMIO_IFSCTL_USE_EDCF);
3587 b43dbg(dev->wl, "QoS enabled\n");
3588 }
3589
b43_op_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 _queue,const struct ieee80211_tx_queue_params * params)3590 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3591 struct ieee80211_vif *vif, u16 _queue,
3592 const struct ieee80211_tx_queue_params *params)
3593 {
3594 struct b43_wl *wl = hw_to_b43_wl(hw);
3595 struct b43_wldev *dev;
3596 unsigned int queue = (unsigned int)_queue;
3597 int err = -ENODEV;
3598
3599 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3600 /* Queue not available or don't support setting
3601 * params on this queue. Return success to not
3602 * confuse mac80211. */
3603 return 0;
3604 }
3605 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3606 ARRAY_SIZE(wl->qos_params));
3607
3608 mutex_lock(&wl->mutex);
3609 dev = wl->current_dev;
3610 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3611 goto out_unlock;
3612
3613 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3614 b43_mac_suspend(dev);
3615 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3616 b43_qos_shm_offsets[queue]);
3617 b43_mac_enable(dev);
3618 err = 0;
3619
3620 out_unlock:
3621 mutex_unlock(&wl->mutex);
3622
3623 return err;
3624 }
3625
b43_op_get_stats(struct ieee80211_hw * hw,struct ieee80211_low_level_stats * stats)3626 static int b43_op_get_stats(struct ieee80211_hw *hw,
3627 struct ieee80211_low_level_stats *stats)
3628 {
3629 struct b43_wl *wl = hw_to_b43_wl(hw);
3630
3631 mutex_lock(&wl->mutex);
3632 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3633 mutex_unlock(&wl->mutex);
3634
3635 return 0;
3636 }
3637
b43_op_get_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)3638 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3639 {
3640 struct b43_wl *wl = hw_to_b43_wl(hw);
3641 struct b43_wldev *dev;
3642 u64 tsf;
3643
3644 mutex_lock(&wl->mutex);
3645 dev = wl->current_dev;
3646
3647 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3648 b43_tsf_read(dev, &tsf);
3649 else
3650 tsf = 0;
3651
3652 mutex_unlock(&wl->mutex);
3653
3654 return tsf;
3655 }
3656
b43_op_set_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u64 tsf)3657 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3658 struct ieee80211_vif *vif, u64 tsf)
3659 {
3660 struct b43_wl *wl = hw_to_b43_wl(hw);
3661 struct b43_wldev *dev;
3662
3663 mutex_lock(&wl->mutex);
3664 dev = wl->current_dev;
3665
3666 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3667 b43_tsf_write(dev, tsf);
3668
3669 mutex_unlock(&wl->mutex);
3670 }
3671
b43_put_phy_into_reset(struct b43_wldev * dev)3672 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3673 {
3674 u32 tmp;
3675
3676 switch (dev->dev->bus_type) {
3677 #ifdef CONFIG_B43_BCMA
3678 case B43_BUS_BCMA:
3679 b43err(dev->wl,
3680 "Putting PHY into reset not supported on BCMA\n");
3681 break;
3682 #endif
3683 #ifdef CONFIG_B43_SSB
3684 case B43_BUS_SSB:
3685 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3686 tmp &= ~B43_TMSLOW_GMODE;
3687 tmp |= B43_TMSLOW_PHYRESET;
3688 tmp |= SSB_TMSLOW_FGC;
3689 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3690 msleep(1);
3691
3692 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3693 tmp &= ~SSB_TMSLOW_FGC;
3694 tmp |= B43_TMSLOW_PHYRESET;
3695 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3696 msleep(1);
3697
3698 break;
3699 #endif
3700 }
3701 }
3702
band_to_string(enum ieee80211_band band)3703 static const char *band_to_string(enum ieee80211_band band)
3704 {
3705 switch (band) {
3706 case IEEE80211_BAND_5GHZ:
3707 return "5";
3708 case IEEE80211_BAND_2GHZ:
3709 return "2.4";
3710 default:
3711 break;
3712 }
3713 B43_WARN_ON(1);
3714 return "";
3715 }
3716
3717 /* Expects wl->mutex locked */
b43_switch_band(struct b43_wl * wl,struct ieee80211_channel * chan)3718 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3719 {
3720 struct b43_wldev *up_dev = NULL;
3721 struct b43_wldev *down_dev;
3722 struct b43_wldev *d;
3723 int err;
3724 bool uninitialized_var(gmode);
3725 int prev_status;
3726
3727 /* Find a device and PHY which supports the band. */
3728 list_for_each_entry(d, &wl->devlist, list) {
3729 switch (chan->band) {
3730 case IEEE80211_BAND_5GHZ:
3731 if (d->phy.supports_5ghz) {
3732 up_dev = d;
3733 gmode = false;
3734 }
3735 break;
3736 case IEEE80211_BAND_2GHZ:
3737 if (d->phy.supports_2ghz) {
3738 up_dev = d;
3739 gmode = true;
3740 }
3741 break;
3742 default:
3743 B43_WARN_ON(1);
3744 return -EINVAL;
3745 }
3746 if (up_dev)
3747 break;
3748 }
3749 if (!up_dev) {
3750 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3751 band_to_string(chan->band));
3752 return -ENODEV;
3753 }
3754 if ((up_dev == wl->current_dev) &&
3755 (!!wl->current_dev->phy.gmode == !!gmode)) {
3756 /* This device is already running. */
3757 return 0;
3758 }
3759 b43dbg(wl, "Switching to %s-GHz band\n",
3760 band_to_string(chan->band));
3761 down_dev = wl->current_dev;
3762
3763 prev_status = b43_status(down_dev);
3764 /* Shutdown the currently running core. */
3765 if (prev_status >= B43_STAT_STARTED)
3766 down_dev = b43_wireless_core_stop(down_dev);
3767 if (prev_status >= B43_STAT_INITIALIZED)
3768 b43_wireless_core_exit(down_dev);
3769
3770 if (down_dev != up_dev) {
3771 /* We switch to a different core, so we put PHY into
3772 * RESET on the old core. */
3773 b43_put_phy_into_reset(down_dev);
3774 }
3775
3776 /* Now start the new core. */
3777 up_dev->phy.gmode = gmode;
3778 if (prev_status >= B43_STAT_INITIALIZED) {
3779 err = b43_wireless_core_init(up_dev);
3780 if (err) {
3781 b43err(wl, "Fatal: Could not initialize device for "
3782 "selected %s-GHz band\n",
3783 band_to_string(chan->band));
3784 goto init_failure;
3785 }
3786 }
3787 if (prev_status >= B43_STAT_STARTED) {
3788 err = b43_wireless_core_start(up_dev);
3789 if (err) {
3790 b43err(wl, "Fatal: Coult not start device for "
3791 "selected %s-GHz band\n",
3792 band_to_string(chan->band));
3793 b43_wireless_core_exit(up_dev);
3794 goto init_failure;
3795 }
3796 }
3797 B43_WARN_ON(b43_status(up_dev) != prev_status);
3798
3799 wl->current_dev = up_dev;
3800
3801 return 0;
3802 init_failure:
3803 /* Whoops, failed to init the new core. No core is operating now. */
3804 wl->current_dev = NULL;
3805 return err;
3806 }
3807
3808 /* Write the short and long frame retry limit values. */
b43_set_retry_limits(struct b43_wldev * dev,unsigned int short_retry,unsigned int long_retry)3809 static void b43_set_retry_limits(struct b43_wldev *dev,
3810 unsigned int short_retry,
3811 unsigned int long_retry)
3812 {
3813 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3814 * the chip-internal counter. */
3815 short_retry = min(short_retry, (unsigned int)0xF);
3816 long_retry = min(long_retry, (unsigned int)0xF);
3817
3818 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3819 short_retry);
3820 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3821 long_retry);
3822 }
3823
b43_op_config(struct ieee80211_hw * hw,u32 changed)3824 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3825 {
3826 struct b43_wl *wl = hw_to_b43_wl(hw);
3827 struct b43_wldev *dev;
3828 struct b43_phy *phy;
3829 struct ieee80211_conf *conf = &hw->conf;
3830 int antenna;
3831 int err = 0;
3832 bool reload_bss = false;
3833
3834 mutex_lock(&wl->mutex);
3835
3836 dev = wl->current_dev;
3837
3838 /* Switch the band (if necessary). This might change the active core. */
3839 err = b43_switch_band(wl, conf->channel);
3840 if (err)
3841 goto out_unlock_mutex;
3842
3843 /* Need to reload all settings if the core changed */
3844 if (dev != wl->current_dev) {
3845 dev = wl->current_dev;
3846 changed = ~0;
3847 reload_bss = true;
3848 }
3849
3850 phy = &dev->phy;
3851
3852 if (conf_is_ht(conf))
3853 phy->is_40mhz =
3854 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3855 else
3856 phy->is_40mhz = false;
3857
3858 b43_mac_suspend(dev);
3859
3860 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3861 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3862 conf->long_frame_max_tx_count);
3863 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3864 if (!changed)
3865 goto out_mac_enable;
3866
3867 /* Switch to the requested channel.
3868 * The firmware takes care of races with the TX handler. */
3869 if (conf->channel->hw_value != phy->channel)
3870 b43_switch_channel(dev, conf->channel->hw_value);
3871
3872 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3873
3874 /* Adjust the desired TX power level. */
3875 if (conf->power_level != 0) {
3876 if (conf->power_level != phy->desired_txpower) {
3877 phy->desired_txpower = conf->power_level;
3878 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3879 B43_TXPWR_IGNORE_TSSI);
3880 }
3881 }
3882
3883 /* Antennas for RX and management frame TX. */
3884 antenna = B43_ANTENNA_DEFAULT;
3885 b43_mgmtframe_txantenna(dev, antenna);
3886 antenna = B43_ANTENNA_DEFAULT;
3887 if (phy->ops->set_rx_antenna)
3888 phy->ops->set_rx_antenna(dev, antenna);
3889
3890 if (wl->radio_enabled != phy->radio_on) {
3891 if (wl->radio_enabled) {
3892 b43_software_rfkill(dev, false);
3893 b43info(dev->wl, "Radio turned on by software\n");
3894 if (!dev->radio_hw_enable) {
3895 b43info(dev->wl, "The hardware RF-kill button "
3896 "still turns the radio physically off. "
3897 "Press the button to turn it on.\n");
3898 }
3899 } else {
3900 b43_software_rfkill(dev, true);
3901 b43info(dev->wl, "Radio turned off by software\n");
3902 }
3903 }
3904
3905 out_mac_enable:
3906 b43_mac_enable(dev);
3907 out_unlock_mutex:
3908 mutex_unlock(&wl->mutex);
3909
3910 if (wl->vif && reload_bss)
3911 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3912
3913 return err;
3914 }
3915
b43_update_basic_rates(struct b43_wldev * dev,u32 brates)3916 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3917 {
3918 struct ieee80211_supported_band *sband =
3919 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3920 struct ieee80211_rate *rate;
3921 int i;
3922 u16 basic, direct, offset, basic_offset, rateptr;
3923
3924 for (i = 0; i < sband->n_bitrates; i++) {
3925 rate = &sband->bitrates[i];
3926
3927 if (b43_is_cck_rate(rate->hw_value)) {
3928 direct = B43_SHM_SH_CCKDIRECT;
3929 basic = B43_SHM_SH_CCKBASIC;
3930 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3931 offset &= 0xF;
3932 } else {
3933 direct = B43_SHM_SH_OFDMDIRECT;
3934 basic = B43_SHM_SH_OFDMBASIC;
3935 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3936 offset &= 0xF;
3937 }
3938
3939 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3940
3941 if (b43_is_cck_rate(rate->hw_value)) {
3942 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3943 basic_offset &= 0xF;
3944 } else {
3945 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3946 basic_offset &= 0xF;
3947 }
3948
3949 /*
3950 * Get the pointer that we need to point to
3951 * from the direct map
3952 */
3953 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3954 direct + 2 * basic_offset);
3955 /* and write it to the basic map */
3956 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3957 rateptr);
3958 }
3959 }
3960
b43_op_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * conf,u32 changed)3961 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3962 struct ieee80211_vif *vif,
3963 struct ieee80211_bss_conf *conf,
3964 u32 changed)
3965 {
3966 struct b43_wl *wl = hw_to_b43_wl(hw);
3967 struct b43_wldev *dev;
3968
3969 mutex_lock(&wl->mutex);
3970
3971 dev = wl->current_dev;
3972 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3973 goto out_unlock_mutex;
3974
3975 B43_WARN_ON(wl->vif != vif);
3976
3977 if (changed & BSS_CHANGED_BSSID) {
3978 if (conf->bssid)
3979 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3980 else
3981 memset(wl->bssid, 0, ETH_ALEN);
3982 }
3983
3984 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3985 if (changed & BSS_CHANGED_BEACON &&
3986 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3987 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3988 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3989 b43_update_templates(wl);
3990
3991 if (changed & BSS_CHANGED_BSSID)
3992 b43_write_mac_bssid_templates(dev);
3993 }
3994
3995 b43_mac_suspend(dev);
3996
3997 /* Update templates for AP/mesh mode. */
3998 if (changed & BSS_CHANGED_BEACON_INT &&
3999 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4000 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4001 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4002 conf->beacon_int)
4003 b43_set_beacon_int(dev, conf->beacon_int);
4004
4005 if (changed & BSS_CHANGED_BASIC_RATES)
4006 b43_update_basic_rates(dev, conf->basic_rates);
4007
4008 if (changed & BSS_CHANGED_ERP_SLOT) {
4009 if (conf->use_short_slot)
4010 b43_short_slot_timing_enable(dev);
4011 else
4012 b43_short_slot_timing_disable(dev);
4013 }
4014
4015 b43_mac_enable(dev);
4016 out_unlock_mutex:
4017 mutex_unlock(&wl->mutex);
4018 }
4019
b43_op_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)4020 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4021 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4022 struct ieee80211_key_conf *key)
4023 {
4024 struct b43_wl *wl = hw_to_b43_wl(hw);
4025 struct b43_wldev *dev;
4026 u8 algorithm;
4027 u8 index;
4028 int err;
4029 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4030
4031 if (modparam_nohwcrypt)
4032 return -ENOSPC; /* User disabled HW-crypto */
4033
4034 mutex_lock(&wl->mutex);
4035
4036 dev = wl->current_dev;
4037 err = -ENODEV;
4038 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4039 goto out_unlock;
4040
4041 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4042 /* We don't have firmware for the crypto engine.
4043 * Must use software-crypto. */
4044 err = -EOPNOTSUPP;
4045 goto out_unlock;
4046 }
4047
4048 err = -EINVAL;
4049 switch (key->cipher) {
4050 case WLAN_CIPHER_SUITE_WEP40:
4051 algorithm = B43_SEC_ALGO_WEP40;
4052 break;
4053 case WLAN_CIPHER_SUITE_WEP104:
4054 algorithm = B43_SEC_ALGO_WEP104;
4055 break;
4056 case WLAN_CIPHER_SUITE_TKIP:
4057 algorithm = B43_SEC_ALGO_TKIP;
4058 break;
4059 case WLAN_CIPHER_SUITE_CCMP:
4060 algorithm = B43_SEC_ALGO_AES;
4061 break;
4062 default:
4063 B43_WARN_ON(1);
4064 goto out_unlock;
4065 }
4066 index = (u8) (key->keyidx);
4067 if (index > 3)
4068 goto out_unlock;
4069
4070 switch (cmd) {
4071 case SET_KEY:
4072 if (algorithm == B43_SEC_ALGO_TKIP &&
4073 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4074 !modparam_hwtkip)) {
4075 /* We support only pairwise key */
4076 err = -EOPNOTSUPP;
4077 goto out_unlock;
4078 }
4079
4080 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4081 if (WARN_ON(!sta)) {
4082 err = -EOPNOTSUPP;
4083 goto out_unlock;
4084 }
4085 /* Pairwise key with an assigned MAC address. */
4086 err = b43_key_write(dev, -1, algorithm,
4087 key->key, key->keylen,
4088 sta->addr, key);
4089 } else {
4090 /* Group key */
4091 err = b43_key_write(dev, index, algorithm,
4092 key->key, key->keylen, NULL, key);
4093 }
4094 if (err)
4095 goto out_unlock;
4096
4097 if (algorithm == B43_SEC_ALGO_WEP40 ||
4098 algorithm == B43_SEC_ALGO_WEP104) {
4099 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4100 } else {
4101 b43_hf_write(dev,
4102 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4103 }
4104 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4105 if (algorithm == B43_SEC_ALGO_TKIP)
4106 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4107 break;
4108 case DISABLE_KEY: {
4109 err = b43_key_clear(dev, key->hw_key_idx);
4110 if (err)
4111 goto out_unlock;
4112 break;
4113 }
4114 default:
4115 B43_WARN_ON(1);
4116 }
4117
4118 out_unlock:
4119 if (!err) {
4120 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4121 "mac: %pM\n",
4122 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4123 sta ? sta->addr : bcast_addr);
4124 b43_dump_keymemory(dev);
4125 }
4126 mutex_unlock(&wl->mutex);
4127
4128 return err;
4129 }
4130
b43_op_configure_filter(struct ieee80211_hw * hw,unsigned int changed,unsigned int * fflags,u64 multicast)4131 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4132 unsigned int changed, unsigned int *fflags,
4133 u64 multicast)
4134 {
4135 struct b43_wl *wl = hw_to_b43_wl(hw);
4136 struct b43_wldev *dev;
4137
4138 mutex_lock(&wl->mutex);
4139 dev = wl->current_dev;
4140 if (!dev) {
4141 *fflags = 0;
4142 goto out_unlock;
4143 }
4144
4145 *fflags &= FIF_PROMISC_IN_BSS |
4146 FIF_ALLMULTI |
4147 FIF_FCSFAIL |
4148 FIF_PLCPFAIL |
4149 FIF_CONTROL |
4150 FIF_OTHER_BSS |
4151 FIF_BCN_PRBRESP_PROMISC;
4152
4153 changed &= FIF_PROMISC_IN_BSS |
4154 FIF_ALLMULTI |
4155 FIF_FCSFAIL |
4156 FIF_PLCPFAIL |
4157 FIF_CONTROL |
4158 FIF_OTHER_BSS |
4159 FIF_BCN_PRBRESP_PROMISC;
4160
4161 wl->filter_flags = *fflags;
4162
4163 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4164 b43_adjust_opmode(dev);
4165
4166 out_unlock:
4167 mutex_unlock(&wl->mutex);
4168 }
4169
4170 /* Locking: wl->mutex
4171 * Returns the current dev. This might be different from the passed in dev,
4172 * because the core might be gone away while we unlocked the mutex. */
b43_wireless_core_stop(struct b43_wldev * dev)4173 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4174 {
4175 struct b43_wl *wl;
4176 struct b43_wldev *orig_dev;
4177 u32 mask;
4178 int queue_num;
4179
4180 if (!dev)
4181 return NULL;
4182 wl = dev->wl;
4183 redo:
4184 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4185 return dev;
4186
4187 /* Cancel work. Unlock to avoid deadlocks. */
4188 mutex_unlock(&wl->mutex);
4189 cancel_delayed_work_sync(&dev->periodic_work);
4190 cancel_work_sync(&wl->tx_work);
4191 cancel_work_sync(&wl->firmware_load);
4192 mutex_lock(&wl->mutex);
4193 dev = wl->current_dev;
4194 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4195 /* Whoops, aliens ate up the device while we were unlocked. */
4196 return dev;
4197 }
4198
4199 /* Disable interrupts on the device. */
4200 b43_set_status(dev, B43_STAT_INITIALIZED);
4201 if (b43_bus_host_is_sdio(dev->dev)) {
4202 /* wl->mutex is locked. That is enough. */
4203 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4204 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4205 } else {
4206 spin_lock_irq(&wl->hardirq_lock);
4207 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4208 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4209 spin_unlock_irq(&wl->hardirq_lock);
4210 }
4211 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4212 orig_dev = dev;
4213 mutex_unlock(&wl->mutex);
4214 if (b43_bus_host_is_sdio(dev->dev)) {
4215 b43_sdio_free_irq(dev);
4216 } else {
4217 synchronize_irq(dev->dev->irq);
4218 free_irq(dev->dev->irq, dev);
4219 }
4220 mutex_lock(&wl->mutex);
4221 dev = wl->current_dev;
4222 if (!dev)
4223 return dev;
4224 if (dev != orig_dev) {
4225 if (b43_status(dev) >= B43_STAT_STARTED)
4226 goto redo;
4227 return dev;
4228 }
4229 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4230 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4231
4232 /* Drain all TX queues. */
4233 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4234 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4235 struct sk_buff *skb;
4236
4237 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4238 ieee80211_free_txskb(wl->hw, skb);
4239 }
4240 }
4241
4242 b43_mac_suspend(dev);
4243 b43_leds_exit(dev);
4244 b43dbg(wl, "Wireless interface stopped\n");
4245
4246 return dev;
4247 }
4248
4249 /* Locking: wl->mutex */
b43_wireless_core_start(struct b43_wldev * dev)4250 static int b43_wireless_core_start(struct b43_wldev *dev)
4251 {
4252 int err;
4253
4254 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4255
4256 drain_txstatus_queue(dev);
4257 if (b43_bus_host_is_sdio(dev->dev)) {
4258 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4259 if (err) {
4260 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4261 goto out;
4262 }
4263 } else {
4264 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4265 b43_interrupt_thread_handler,
4266 IRQF_SHARED, KBUILD_MODNAME, dev);
4267 if (err) {
4268 b43err(dev->wl, "Cannot request IRQ-%d\n",
4269 dev->dev->irq);
4270 goto out;
4271 }
4272 }
4273
4274 /* We are ready to run. */
4275 ieee80211_wake_queues(dev->wl->hw);
4276 b43_set_status(dev, B43_STAT_STARTED);
4277
4278 /* Start data flow (TX/RX). */
4279 b43_mac_enable(dev);
4280 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4281
4282 /* Start maintenance work */
4283 b43_periodic_tasks_setup(dev);
4284
4285 b43_leds_init(dev);
4286
4287 b43dbg(dev->wl, "Wireless interface started\n");
4288 out:
4289 return err;
4290 }
4291
4292 /* Get PHY and RADIO versioning numbers */
b43_phy_versioning(struct b43_wldev * dev)4293 static int b43_phy_versioning(struct b43_wldev *dev)
4294 {
4295 struct b43_phy *phy = &dev->phy;
4296 u32 tmp;
4297 u8 analog_type;
4298 u8 phy_type;
4299 u8 phy_rev;
4300 u16 radio_manuf;
4301 u16 radio_ver;
4302 u16 radio_rev;
4303 int unsupported = 0;
4304
4305 /* Get PHY versioning */
4306 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4307 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4308 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4309 phy_rev = (tmp & B43_PHYVER_VERSION);
4310 switch (phy_type) {
4311 case B43_PHYTYPE_A:
4312 if (phy_rev >= 4)
4313 unsupported = 1;
4314 break;
4315 case B43_PHYTYPE_B:
4316 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4317 && phy_rev != 7)
4318 unsupported = 1;
4319 break;
4320 case B43_PHYTYPE_G:
4321 if (phy_rev > 9)
4322 unsupported = 1;
4323 break;
4324 #ifdef CONFIG_B43_PHY_N
4325 case B43_PHYTYPE_N:
4326 if (phy_rev > 9)
4327 unsupported = 1;
4328 break;
4329 #endif
4330 #ifdef CONFIG_B43_PHY_LP
4331 case B43_PHYTYPE_LP:
4332 if (phy_rev > 2)
4333 unsupported = 1;
4334 break;
4335 #endif
4336 #ifdef CONFIG_B43_PHY_HT
4337 case B43_PHYTYPE_HT:
4338 if (phy_rev > 1)
4339 unsupported = 1;
4340 break;
4341 #endif
4342 #ifdef CONFIG_B43_PHY_LCN
4343 case B43_PHYTYPE_LCN:
4344 if (phy_rev > 1)
4345 unsupported = 1;
4346 break;
4347 #endif
4348 default:
4349 unsupported = 1;
4350 }
4351 if (unsupported) {
4352 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4353 "(Analog %u, Type %u, Revision %u)\n",
4354 analog_type, phy_type, phy_rev);
4355 return -EOPNOTSUPP;
4356 }
4357 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4358 analog_type, phy_type, phy_rev);
4359
4360 /* Get RADIO versioning */
4361 if (dev->dev->core_rev >= 24) {
4362 u16 radio24[3];
4363
4364 for (tmp = 0; tmp < 3; tmp++) {
4365 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4366 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4367 }
4368
4369 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4370 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4371
4372 radio_manuf = 0x17F;
4373 radio_ver = (radio24[2] << 8) | radio24[1];
4374 radio_rev = (radio24[0] & 0xF);
4375 } else {
4376 if (dev->dev->chip_id == 0x4317) {
4377 if (dev->dev->chip_rev == 0)
4378 tmp = 0x3205017F;
4379 else if (dev->dev->chip_rev == 1)
4380 tmp = 0x4205017F;
4381 else
4382 tmp = 0x5205017F;
4383 } else {
4384 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4385 B43_RADIOCTL_ID);
4386 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4387 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4388 B43_RADIOCTL_ID);
4389 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4390 << 16;
4391 }
4392 radio_manuf = (tmp & 0x00000FFF);
4393 radio_ver = (tmp & 0x0FFFF000) >> 12;
4394 radio_rev = (tmp & 0xF0000000) >> 28;
4395 }
4396
4397 if (radio_manuf != 0x17F /* Broadcom */)
4398 unsupported = 1;
4399 switch (phy_type) {
4400 case B43_PHYTYPE_A:
4401 if (radio_ver != 0x2060)
4402 unsupported = 1;
4403 if (radio_rev != 1)
4404 unsupported = 1;
4405 if (radio_manuf != 0x17F)
4406 unsupported = 1;
4407 break;
4408 case B43_PHYTYPE_B:
4409 if ((radio_ver & 0xFFF0) != 0x2050)
4410 unsupported = 1;
4411 break;
4412 case B43_PHYTYPE_G:
4413 if (radio_ver != 0x2050)
4414 unsupported = 1;
4415 break;
4416 case B43_PHYTYPE_N:
4417 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4418 unsupported = 1;
4419 break;
4420 case B43_PHYTYPE_LP:
4421 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4422 unsupported = 1;
4423 break;
4424 case B43_PHYTYPE_HT:
4425 if (radio_ver != 0x2059)
4426 unsupported = 1;
4427 break;
4428 case B43_PHYTYPE_LCN:
4429 if (radio_ver != 0x2064)
4430 unsupported = 1;
4431 break;
4432 default:
4433 B43_WARN_ON(1);
4434 }
4435 if (unsupported) {
4436 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4437 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4438 radio_manuf, radio_ver, radio_rev);
4439 return -EOPNOTSUPP;
4440 }
4441 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4442 radio_manuf, radio_ver, radio_rev);
4443
4444 phy->radio_manuf = radio_manuf;
4445 phy->radio_ver = radio_ver;
4446 phy->radio_rev = radio_rev;
4447
4448 phy->analog = analog_type;
4449 phy->type = phy_type;
4450 phy->rev = phy_rev;
4451
4452 return 0;
4453 }
4454
setup_struct_phy_for_init(struct b43_wldev * dev,struct b43_phy * phy)4455 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4456 struct b43_phy *phy)
4457 {
4458 phy->hardware_power_control = !!modparam_hwpctl;
4459 phy->next_txpwr_check_time = jiffies;
4460 /* PHY TX errors counter. */
4461 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4462
4463 #if B43_DEBUG
4464 phy->phy_locked = false;
4465 phy->radio_locked = false;
4466 #endif
4467 }
4468
setup_struct_wldev_for_init(struct b43_wldev * dev)4469 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4470 {
4471 dev->dfq_valid = false;
4472
4473 /* Assume the radio is enabled. If it's not enabled, the state will
4474 * immediately get fixed on the first periodic work run. */
4475 dev->radio_hw_enable = true;
4476
4477 /* Stats */
4478 memset(&dev->stats, 0, sizeof(dev->stats));
4479
4480 setup_struct_phy_for_init(dev, &dev->phy);
4481
4482 /* IRQ related flags */
4483 dev->irq_reason = 0;
4484 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4485 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4486 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4487 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4488
4489 dev->mac_suspended = 1;
4490
4491 /* Noise calculation context */
4492 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4493 }
4494
b43_bluetooth_coext_enable(struct b43_wldev * dev)4495 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4496 {
4497 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4498 u64 hf;
4499
4500 if (!modparam_btcoex)
4501 return;
4502 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4503 return;
4504 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4505 return;
4506
4507 hf = b43_hf_read(dev);
4508 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4509 hf |= B43_HF_BTCOEXALT;
4510 else
4511 hf |= B43_HF_BTCOEX;
4512 b43_hf_write(dev, hf);
4513 }
4514
b43_bluetooth_coext_disable(struct b43_wldev * dev)4515 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4516 {
4517 if (!modparam_btcoex)
4518 return;
4519 //TODO
4520 }
4521
b43_imcfglo_timeouts_workaround(struct b43_wldev * dev)4522 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4523 {
4524 struct ssb_bus *bus;
4525 u32 tmp;
4526
4527 if (dev->dev->bus_type != B43_BUS_SSB)
4528 return;
4529
4530 bus = dev->dev->sdev->bus;
4531
4532 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4533 (bus->chip_id == 0x4312)) {
4534 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4535 tmp &= ~SSB_IMCFGLO_REQTO;
4536 tmp &= ~SSB_IMCFGLO_SERTO;
4537 tmp |= 0x3;
4538 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4539 ssb_commit_settings(bus);
4540 }
4541 }
4542
b43_set_synth_pu_delay(struct b43_wldev * dev,bool idle)4543 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4544 {
4545 u16 pu_delay;
4546
4547 /* The time value is in microseconds. */
4548 if (dev->phy.type == B43_PHYTYPE_A)
4549 pu_delay = 3700;
4550 else
4551 pu_delay = 1050;
4552 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4553 pu_delay = 500;
4554 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4555 pu_delay = max(pu_delay, (u16)2400);
4556
4557 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4558 }
4559
4560 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
b43_set_pretbtt(struct b43_wldev * dev)4561 static void b43_set_pretbtt(struct b43_wldev *dev)
4562 {
4563 u16 pretbtt;
4564
4565 /* The time value is in microseconds. */
4566 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4567 pretbtt = 2;
4568 } else {
4569 if (dev->phy.type == B43_PHYTYPE_A)
4570 pretbtt = 120;
4571 else
4572 pretbtt = 250;
4573 }
4574 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4575 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4576 }
4577
4578 /* Shutdown a wireless core */
4579 /* Locking: wl->mutex */
b43_wireless_core_exit(struct b43_wldev * dev)4580 static void b43_wireless_core_exit(struct b43_wldev *dev)
4581 {
4582 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4583 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4584 return;
4585
4586 /* Unregister HW RNG driver */
4587 b43_rng_exit(dev->wl);
4588
4589 b43_set_status(dev, B43_STAT_UNINIT);
4590
4591 /* Stop the microcode PSM. */
4592 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4593 B43_MACCTL_PSM_JMP0);
4594
4595 b43_dma_free(dev);
4596 b43_pio_free(dev);
4597 b43_chip_exit(dev);
4598 dev->phy.ops->switch_analog(dev, 0);
4599 if (dev->wl->current_beacon) {
4600 dev_kfree_skb_any(dev->wl->current_beacon);
4601 dev->wl->current_beacon = NULL;
4602 }
4603
4604 b43_device_disable(dev, 0);
4605 b43_bus_may_powerdown(dev);
4606 }
4607
4608 /* Initialize a wireless core */
b43_wireless_core_init(struct b43_wldev * dev)4609 static int b43_wireless_core_init(struct b43_wldev *dev)
4610 {
4611 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4612 struct b43_phy *phy = &dev->phy;
4613 int err;
4614 u64 hf;
4615
4616 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4617
4618 err = b43_bus_powerup(dev, 0);
4619 if (err)
4620 goto out;
4621 if (!b43_device_is_enabled(dev))
4622 b43_wireless_core_reset(dev, phy->gmode);
4623
4624 /* Reset all data structures. */
4625 setup_struct_wldev_for_init(dev);
4626 phy->ops->prepare_structs(dev);
4627
4628 /* Enable IRQ routing to this device. */
4629 switch (dev->dev->bus_type) {
4630 #ifdef CONFIG_B43_BCMA
4631 case B43_BUS_BCMA:
4632 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4633 dev->dev->bdev, true);
4634 break;
4635 #endif
4636 #ifdef CONFIG_B43_SSB
4637 case B43_BUS_SSB:
4638 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4639 dev->dev->sdev);
4640 break;
4641 #endif
4642 }
4643
4644 b43_imcfglo_timeouts_workaround(dev);
4645 b43_bluetooth_coext_disable(dev);
4646 if (phy->ops->prepare_hardware) {
4647 err = phy->ops->prepare_hardware(dev);
4648 if (err)
4649 goto err_busdown;
4650 }
4651 err = b43_chip_init(dev);
4652 if (err)
4653 goto err_busdown;
4654 b43_shm_write16(dev, B43_SHM_SHARED,
4655 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4656 hf = b43_hf_read(dev);
4657 if (phy->type == B43_PHYTYPE_G) {
4658 hf |= B43_HF_SYMW;
4659 if (phy->rev == 1)
4660 hf |= B43_HF_GDCW;
4661 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4662 hf |= B43_HF_OFDMPABOOST;
4663 }
4664 if (phy->radio_ver == 0x2050) {
4665 if (phy->radio_rev == 6)
4666 hf |= B43_HF_4318TSSI;
4667 if (phy->radio_rev < 6)
4668 hf |= B43_HF_VCORECALC;
4669 }
4670 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4671 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4672 #ifdef CONFIG_SSB_DRIVER_PCICORE
4673 if (dev->dev->bus_type == B43_BUS_SSB &&
4674 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4675 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4676 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4677 #endif
4678 hf &= ~B43_HF_SKCFPUP;
4679 b43_hf_write(dev, hf);
4680
4681 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4682 B43_DEFAULT_LONG_RETRY_LIMIT);
4683 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4684 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4685
4686 /* Disable sending probe responses from firmware.
4687 * Setting the MaxTime to one usec will always trigger
4688 * a timeout, so we never send any probe resp.
4689 * A timeout of zero is infinite. */
4690 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4691
4692 b43_rate_memory_init(dev);
4693 b43_set_phytxctl_defaults(dev);
4694
4695 /* Minimum Contention Window */
4696 if (phy->type == B43_PHYTYPE_B)
4697 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4698 else
4699 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4700 /* Maximum Contention Window */
4701 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4702
4703 if (b43_bus_host_is_pcmcia(dev->dev) ||
4704 b43_bus_host_is_sdio(dev->dev)) {
4705 dev->__using_pio_transfers = true;
4706 err = b43_pio_init(dev);
4707 } else if (dev->use_pio) {
4708 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4709 "This should not be needed and will result in lower "
4710 "performance.\n");
4711 dev->__using_pio_transfers = true;
4712 err = b43_pio_init(dev);
4713 } else {
4714 dev->__using_pio_transfers = false;
4715 err = b43_dma_init(dev);
4716 }
4717 if (err)
4718 goto err_chip_exit;
4719 b43_qos_init(dev);
4720 b43_set_synth_pu_delay(dev, 1);
4721 b43_bluetooth_coext_enable(dev);
4722
4723 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4724 b43_upload_card_macaddress(dev);
4725 b43_security_init(dev);
4726
4727 ieee80211_wake_queues(dev->wl->hw);
4728
4729 b43_set_status(dev, B43_STAT_INITIALIZED);
4730
4731 /* Register HW RNG driver */
4732 b43_rng_init(dev->wl);
4733
4734 out:
4735 return err;
4736
4737 err_chip_exit:
4738 b43_chip_exit(dev);
4739 err_busdown:
4740 b43_bus_may_powerdown(dev);
4741 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4742 return err;
4743 }
4744
b43_op_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)4745 static int b43_op_add_interface(struct ieee80211_hw *hw,
4746 struct ieee80211_vif *vif)
4747 {
4748 struct b43_wl *wl = hw_to_b43_wl(hw);
4749 struct b43_wldev *dev;
4750 int err = -EOPNOTSUPP;
4751
4752 /* TODO: allow WDS/AP devices to coexist */
4753
4754 if (vif->type != NL80211_IFTYPE_AP &&
4755 vif->type != NL80211_IFTYPE_MESH_POINT &&
4756 vif->type != NL80211_IFTYPE_STATION &&
4757 vif->type != NL80211_IFTYPE_WDS &&
4758 vif->type != NL80211_IFTYPE_ADHOC)
4759 return -EOPNOTSUPP;
4760
4761 mutex_lock(&wl->mutex);
4762 if (wl->operating)
4763 goto out_mutex_unlock;
4764
4765 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4766
4767 dev = wl->current_dev;
4768 wl->operating = true;
4769 wl->vif = vif;
4770 wl->if_type = vif->type;
4771 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4772
4773 b43_adjust_opmode(dev);
4774 b43_set_pretbtt(dev);
4775 b43_set_synth_pu_delay(dev, 0);
4776 b43_upload_card_macaddress(dev);
4777
4778 err = 0;
4779 out_mutex_unlock:
4780 mutex_unlock(&wl->mutex);
4781
4782 if (err == 0)
4783 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4784
4785 return err;
4786 }
4787
b43_op_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)4788 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4789 struct ieee80211_vif *vif)
4790 {
4791 struct b43_wl *wl = hw_to_b43_wl(hw);
4792 struct b43_wldev *dev = wl->current_dev;
4793
4794 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4795
4796 mutex_lock(&wl->mutex);
4797
4798 B43_WARN_ON(!wl->operating);
4799 B43_WARN_ON(wl->vif != vif);
4800 wl->vif = NULL;
4801
4802 wl->operating = false;
4803
4804 b43_adjust_opmode(dev);
4805 memset(wl->mac_addr, 0, ETH_ALEN);
4806 b43_upload_card_macaddress(dev);
4807
4808 mutex_unlock(&wl->mutex);
4809 }
4810
b43_op_start(struct ieee80211_hw * hw)4811 static int b43_op_start(struct ieee80211_hw *hw)
4812 {
4813 struct b43_wl *wl = hw_to_b43_wl(hw);
4814 struct b43_wldev *dev = wl->current_dev;
4815 int did_init = 0;
4816 int err = 0;
4817
4818 /* Kill all old instance specific information to make sure
4819 * the card won't use it in the short timeframe between start
4820 * and mac80211 reconfiguring it. */
4821 memset(wl->bssid, 0, ETH_ALEN);
4822 memset(wl->mac_addr, 0, ETH_ALEN);
4823 wl->filter_flags = 0;
4824 wl->radiotap_enabled = false;
4825 b43_qos_clear(wl);
4826 wl->beacon0_uploaded = false;
4827 wl->beacon1_uploaded = false;
4828 wl->beacon_templates_virgin = true;
4829 wl->radio_enabled = true;
4830
4831 mutex_lock(&wl->mutex);
4832
4833 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4834 err = b43_wireless_core_init(dev);
4835 if (err)
4836 goto out_mutex_unlock;
4837 did_init = 1;
4838 }
4839
4840 if (b43_status(dev) < B43_STAT_STARTED) {
4841 err = b43_wireless_core_start(dev);
4842 if (err) {
4843 if (did_init)
4844 b43_wireless_core_exit(dev);
4845 goto out_mutex_unlock;
4846 }
4847 }
4848
4849 /* XXX: only do if device doesn't support rfkill irq */
4850 wiphy_rfkill_start_polling(hw->wiphy);
4851
4852 out_mutex_unlock:
4853 mutex_unlock(&wl->mutex);
4854
4855 /*
4856 * Configuration may have been overwritten during initialization.
4857 * Reload the configuration, but only if initialization was
4858 * successful. Reloading the configuration after a failed init
4859 * may hang the system.
4860 */
4861 if (!err)
4862 b43_op_config(hw, ~0);
4863
4864 return err;
4865 }
4866
b43_op_stop(struct ieee80211_hw * hw)4867 static void b43_op_stop(struct ieee80211_hw *hw)
4868 {
4869 struct b43_wl *wl = hw_to_b43_wl(hw);
4870 struct b43_wldev *dev = wl->current_dev;
4871
4872 cancel_work_sync(&(wl->beacon_update_trigger));
4873
4874 if (!dev)
4875 goto out;
4876
4877 mutex_lock(&wl->mutex);
4878 if (b43_status(dev) >= B43_STAT_STARTED) {
4879 dev = b43_wireless_core_stop(dev);
4880 if (!dev)
4881 goto out_unlock;
4882 }
4883 b43_wireless_core_exit(dev);
4884 wl->radio_enabled = false;
4885
4886 out_unlock:
4887 mutex_unlock(&wl->mutex);
4888 out:
4889 cancel_work_sync(&(wl->txpower_adjust_work));
4890 }
4891
b43_op_beacon_set_tim(struct ieee80211_hw * hw,struct ieee80211_sta * sta,bool set)4892 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4893 struct ieee80211_sta *sta, bool set)
4894 {
4895 struct b43_wl *wl = hw_to_b43_wl(hw);
4896
4897 /* FIXME: add locking */
4898 b43_update_templates(wl);
4899
4900 return 0;
4901 }
4902
b43_op_sta_notify(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum sta_notify_cmd notify_cmd,struct ieee80211_sta * sta)4903 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4904 struct ieee80211_vif *vif,
4905 enum sta_notify_cmd notify_cmd,
4906 struct ieee80211_sta *sta)
4907 {
4908 struct b43_wl *wl = hw_to_b43_wl(hw);
4909
4910 B43_WARN_ON(!vif || wl->vif != vif);
4911 }
4912
b43_op_sw_scan_start_notifier(struct ieee80211_hw * hw)4913 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4914 {
4915 struct b43_wl *wl = hw_to_b43_wl(hw);
4916 struct b43_wldev *dev;
4917
4918 mutex_lock(&wl->mutex);
4919 dev = wl->current_dev;
4920 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4921 /* Disable CFP update during scan on other channels. */
4922 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4923 }
4924 mutex_unlock(&wl->mutex);
4925 }
4926
b43_op_sw_scan_complete_notifier(struct ieee80211_hw * hw)4927 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4928 {
4929 struct b43_wl *wl = hw_to_b43_wl(hw);
4930 struct b43_wldev *dev;
4931
4932 mutex_lock(&wl->mutex);
4933 dev = wl->current_dev;
4934 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4935 /* Re-enable CFP update. */
4936 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4937 }
4938 mutex_unlock(&wl->mutex);
4939 }
4940
b43_op_get_survey(struct ieee80211_hw * hw,int idx,struct survey_info * survey)4941 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4942 struct survey_info *survey)
4943 {
4944 struct b43_wl *wl = hw_to_b43_wl(hw);
4945 struct b43_wldev *dev = wl->current_dev;
4946 struct ieee80211_conf *conf = &hw->conf;
4947
4948 if (idx != 0)
4949 return -ENOENT;
4950
4951 survey->channel = conf->channel;
4952 survey->filled = SURVEY_INFO_NOISE_DBM;
4953 survey->noise = dev->stats.link_noise;
4954
4955 return 0;
4956 }
4957
4958 static const struct ieee80211_ops b43_hw_ops = {
4959 .tx = b43_op_tx,
4960 .conf_tx = b43_op_conf_tx,
4961 .add_interface = b43_op_add_interface,
4962 .remove_interface = b43_op_remove_interface,
4963 .config = b43_op_config,
4964 .bss_info_changed = b43_op_bss_info_changed,
4965 .configure_filter = b43_op_configure_filter,
4966 .set_key = b43_op_set_key,
4967 .update_tkip_key = b43_op_update_tkip_key,
4968 .get_stats = b43_op_get_stats,
4969 .get_tsf = b43_op_get_tsf,
4970 .set_tsf = b43_op_set_tsf,
4971 .start = b43_op_start,
4972 .stop = b43_op_stop,
4973 .set_tim = b43_op_beacon_set_tim,
4974 .sta_notify = b43_op_sta_notify,
4975 .sw_scan_start = b43_op_sw_scan_start_notifier,
4976 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4977 .get_survey = b43_op_get_survey,
4978 .rfkill_poll = b43_rfkill_poll,
4979 };
4980
4981 /* Hard-reset the chip. Do not call this directly.
4982 * Use b43_controller_restart()
4983 */
b43_chip_reset(struct work_struct * work)4984 static void b43_chip_reset(struct work_struct *work)
4985 {
4986 struct b43_wldev *dev =
4987 container_of(work, struct b43_wldev, restart_work);
4988 struct b43_wl *wl = dev->wl;
4989 int err = 0;
4990 int prev_status;
4991
4992 mutex_lock(&wl->mutex);
4993
4994 prev_status = b43_status(dev);
4995 /* Bring the device down... */
4996 if (prev_status >= B43_STAT_STARTED) {
4997 dev = b43_wireless_core_stop(dev);
4998 if (!dev) {
4999 err = -ENODEV;
5000 goto out;
5001 }
5002 }
5003 if (prev_status >= B43_STAT_INITIALIZED)
5004 b43_wireless_core_exit(dev);
5005
5006 /* ...and up again. */
5007 if (prev_status >= B43_STAT_INITIALIZED) {
5008 err = b43_wireless_core_init(dev);
5009 if (err)
5010 goto out;
5011 }
5012 if (prev_status >= B43_STAT_STARTED) {
5013 err = b43_wireless_core_start(dev);
5014 if (err) {
5015 b43_wireless_core_exit(dev);
5016 goto out;
5017 }
5018 }
5019 out:
5020 if (err)
5021 wl->current_dev = NULL; /* Failed to init the dev. */
5022 mutex_unlock(&wl->mutex);
5023
5024 if (err) {
5025 b43err(wl, "Controller restart FAILED\n");
5026 return;
5027 }
5028
5029 /* reload configuration */
5030 b43_op_config(wl->hw, ~0);
5031 if (wl->vif)
5032 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5033
5034 b43info(wl, "Controller restarted\n");
5035 }
5036
b43_setup_bands(struct b43_wldev * dev,bool have_2ghz_phy,bool have_5ghz_phy)5037 static int b43_setup_bands(struct b43_wldev *dev,
5038 bool have_2ghz_phy, bool have_5ghz_phy)
5039 {
5040 struct ieee80211_hw *hw = dev->wl->hw;
5041
5042 if (have_2ghz_phy)
5043 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5044 if (dev->phy.type == B43_PHYTYPE_N) {
5045 if (have_5ghz_phy)
5046 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5047 } else {
5048 if (have_5ghz_phy)
5049 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5050 }
5051
5052 dev->phy.supports_2ghz = have_2ghz_phy;
5053 dev->phy.supports_5ghz = have_5ghz_phy;
5054
5055 return 0;
5056 }
5057
b43_wireless_core_detach(struct b43_wldev * dev)5058 static void b43_wireless_core_detach(struct b43_wldev *dev)
5059 {
5060 /* We release firmware that late to not be required to re-request
5061 * is all the time when we reinit the core. */
5062 b43_release_firmware(dev);
5063 b43_phy_free(dev);
5064 }
5065
b43_wireless_core_attach(struct b43_wldev * dev)5066 static int b43_wireless_core_attach(struct b43_wldev *dev)
5067 {
5068 struct b43_wl *wl = dev->wl;
5069 struct pci_dev *pdev = NULL;
5070 int err;
5071 u32 tmp;
5072 bool have_2ghz_phy = false, have_5ghz_phy = false;
5073
5074 /* Do NOT do any device initialization here.
5075 * Do it in wireless_core_init() instead.
5076 * This function is for gathering basic information about the HW, only.
5077 * Also some structs may be set up here. But most likely you want to have
5078 * that in core_init(), too.
5079 */
5080
5081 #ifdef CONFIG_B43_SSB
5082 if (dev->dev->bus_type == B43_BUS_SSB &&
5083 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5084 pdev = dev->dev->sdev->bus->host_pci;
5085 #endif
5086
5087 err = b43_bus_powerup(dev, 0);
5088 if (err) {
5089 b43err(wl, "Bus powerup failed\n");
5090 goto out;
5091 }
5092
5093 /* Get the PHY type. */
5094 switch (dev->dev->bus_type) {
5095 #ifdef CONFIG_B43_BCMA
5096 case B43_BUS_BCMA:
5097 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5098 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5099 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5100 break;
5101 #endif
5102 #ifdef CONFIG_B43_SSB
5103 case B43_BUS_SSB:
5104 if (dev->dev->core_rev >= 5) {
5105 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5106 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5107 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5108 } else
5109 B43_WARN_ON(1);
5110 break;
5111 #endif
5112 }
5113
5114 dev->phy.gmode = have_2ghz_phy;
5115 dev->phy.radio_on = true;
5116 b43_wireless_core_reset(dev, dev->phy.gmode);
5117
5118 err = b43_phy_versioning(dev);
5119 if (err)
5120 goto err_powerdown;
5121 /* Check if this device supports multiband. */
5122 if (!pdev ||
5123 (pdev->device != 0x4312 &&
5124 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5125 /* No multiband support. */
5126 have_2ghz_phy = false;
5127 have_5ghz_phy = false;
5128 switch (dev->phy.type) {
5129 case B43_PHYTYPE_A:
5130 have_5ghz_phy = true;
5131 break;
5132 case B43_PHYTYPE_LP: //FIXME not always!
5133 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5134 have_5ghz_phy = 1;
5135 #endif
5136 case B43_PHYTYPE_G:
5137 case B43_PHYTYPE_N:
5138 case B43_PHYTYPE_HT:
5139 case B43_PHYTYPE_LCN:
5140 have_2ghz_phy = true;
5141 break;
5142 default:
5143 B43_WARN_ON(1);
5144 }
5145 }
5146 if (dev->phy.type == B43_PHYTYPE_A) {
5147 /* FIXME */
5148 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5149 err = -EOPNOTSUPP;
5150 goto err_powerdown;
5151 }
5152 if (1 /* disable A-PHY */) {
5153 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5154 if (dev->phy.type != B43_PHYTYPE_N &&
5155 dev->phy.type != B43_PHYTYPE_LP) {
5156 have_2ghz_phy = true;
5157 have_5ghz_phy = false;
5158 }
5159 }
5160
5161 err = b43_phy_allocate(dev);
5162 if (err)
5163 goto err_powerdown;
5164
5165 dev->phy.gmode = have_2ghz_phy;
5166 b43_wireless_core_reset(dev, dev->phy.gmode);
5167
5168 err = b43_validate_chipaccess(dev);
5169 if (err)
5170 goto err_phy_free;
5171 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5172 if (err)
5173 goto err_phy_free;
5174
5175 /* Now set some default "current_dev" */
5176 if (!wl->current_dev)
5177 wl->current_dev = dev;
5178 INIT_WORK(&dev->restart_work, b43_chip_reset);
5179
5180 dev->phy.ops->switch_analog(dev, 0);
5181 b43_device_disable(dev, 0);
5182 b43_bus_may_powerdown(dev);
5183
5184 out:
5185 return err;
5186
5187 err_phy_free:
5188 b43_phy_free(dev);
5189 err_powerdown:
5190 b43_bus_may_powerdown(dev);
5191 return err;
5192 }
5193
b43_one_core_detach(struct b43_bus_dev * dev)5194 static void b43_one_core_detach(struct b43_bus_dev *dev)
5195 {
5196 struct b43_wldev *wldev;
5197 struct b43_wl *wl;
5198
5199 /* Do not cancel ieee80211-workqueue based work here.
5200 * See comment in b43_remove(). */
5201
5202 wldev = b43_bus_get_wldev(dev);
5203 wl = wldev->wl;
5204 b43_debugfs_remove_device(wldev);
5205 b43_wireless_core_detach(wldev);
5206 list_del(&wldev->list);
5207 wl->nr_devs--;
5208 b43_bus_set_wldev(dev, NULL);
5209 kfree(wldev);
5210 }
5211
b43_one_core_attach(struct b43_bus_dev * dev,struct b43_wl * wl)5212 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5213 {
5214 struct b43_wldev *wldev;
5215 int err = -ENOMEM;
5216
5217 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5218 if (!wldev)
5219 goto out;
5220
5221 wldev->use_pio = b43_modparam_pio;
5222 wldev->dev = dev;
5223 wldev->wl = wl;
5224 b43_set_status(wldev, B43_STAT_UNINIT);
5225 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5226 INIT_LIST_HEAD(&wldev->list);
5227
5228 err = b43_wireless_core_attach(wldev);
5229 if (err)
5230 goto err_kfree_wldev;
5231
5232 list_add(&wldev->list, &wl->devlist);
5233 wl->nr_devs++;
5234 b43_bus_set_wldev(dev, wldev);
5235 b43_debugfs_add_device(wldev);
5236
5237 out:
5238 return err;
5239
5240 err_kfree_wldev:
5241 kfree(wldev);
5242 return err;
5243 }
5244
5245 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5246 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5247 (pdev->device == _device) && \
5248 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5249 (pdev->subsystem_device == _subdevice) )
5250
b43_sprom_fixup(struct ssb_bus * bus)5251 static void b43_sprom_fixup(struct ssb_bus *bus)
5252 {
5253 struct pci_dev *pdev;
5254
5255 /* boardflags workarounds */
5256 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5257 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
5258 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5259 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5260 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
5261 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5262 if (bus->bustype == SSB_BUSTYPE_PCI) {
5263 pdev = bus->host_pci;
5264 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5265 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5266 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5267 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5268 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5269 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5270 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5271 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5272 }
5273 }
5274
b43_wireless_exit(struct b43_bus_dev * dev,struct b43_wl * wl)5275 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5276 {
5277 struct ieee80211_hw *hw = wl->hw;
5278
5279 ssb_set_devtypedata(dev->sdev, NULL);
5280 ieee80211_free_hw(hw);
5281 }
5282
b43_wireless_init(struct b43_bus_dev * dev)5283 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5284 {
5285 struct ssb_sprom *sprom = dev->bus_sprom;
5286 struct ieee80211_hw *hw;
5287 struct b43_wl *wl;
5288 char chip_name[6];
5289 int queue_num;
5290
5291 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5292 if (!hw) {
5293 b43err(NULL, "Could not allocate ieee80211 device\n");
5294 return ERR_PTR(-ENOMEM);
5295 }
5296 wl = hw_to_b43_wl(hw);
5297
5298 /* fill hw info */
5299 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5300 IEEE80211_HW_SIGNAL_DBM;
5301
5302 hw->wiphy->interface_modes =
5303 BIT(NL80211_IFTYPE_AP) |
5304 BIT(NL80211_IFTYPE_MESH_POINT) |
5305 BIT(NL80211_IFTYPE_STATION) |
5306 BIT(NL80211_IFTYPE_WDS) |
5307 BIT(NL80211_IFTYPE_ADHOC);
5308
5309 hw->queues = modparam_qos ? B43_QOS_QUEUE_NUM : 1;
5310 wl->mac80211_initially_registered_queues = hw->queues;
5311 hw->max_rates = 2;
5312 SET_IEEE80211_DEV(hw, dev->dev);
5313 if (is_valid_ether_addr(sprom->et1mac))
5314 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5315 else
5316 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5317
5318 /* Initialize struct b43_wl */
5319 wl->hw = hw;
5320 mutex_init(&wl->mutex);
5321 spin_lock_init(&wl->hardirq_lock);
5322 INIT_LIST_HEAD(&wl->devlist);
5323 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5324 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5325 INIT_WORK(&wl->tx_work, b43_tx_work);
5326
5327 /* Initialize queues and flags. */
5328 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5329 skb_queue_head_init(&wl->tx_queue[queue_num]);
5330 wl->tx_queue_stopped[queue_num] = 0;
5331 }
5332
5333 snprintf(chip_name, ARRAY_SIZE(chip_name),
5334 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5335 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5336 dev->core_rev);
5337 return wl;
5338 }
5339
5340 #ifdef CONFIG_B43_BCMA
b43_bcma_probe(struct bcma_device * core)5341 static int b43_bcma_probe(struct bcma_device *core)
5342 {
5343 struct b43_bus_dev *dev;
5344 struct b43_wl *wl;
5345 int err;
5346
5347 dev = b43_bus_dev_bcma_init(core);
5348 if (!dev)
5349 return -ENODEV;
5350
5351 wl = b43_wireless_init(dev);
5352 if (IS_ERR(wl)) {
5353 err = PTR_ERR(wl);
5354 goto bcma_out;
5355 }
5356
5357 err = b43_one_core_attach(dev, wl);
5358 if (err)
5359 goto bcma_err_wireless_exit;
5360
5361 /* setup and start work to load firmware */
5362 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5363 schedule_work(&wl->firmware_load);
5364
5365 bcma_out:
5366 return err;
5367
5368 bcma_err_wireless_exit:
5369 ieee80211_free_hw(wl->hw);
5370 return err;
5371 }
5372
b43_bcma_remove(struct bcma_device * core)5373 static void b43_bcma_remove(struct bcma_device *core)
5374 {
5375 struct b43_wldev *wldev = bcma_get_drvdata(core);
5376 struct b43_wl *wl = wldev->wl;
5377
5378 /* We must cancel any work here before unregistering from ieee80211,
5379 * as the ieee80211 unreg will destroy the workqueue. */
5380 cancel_work_sync(&wldev->restart_work);
5381
5382 /* Restore the queues count before unregistering, because firmware detect
5383 * might have modified it. Restoring is important, so the networking
5384 * stack can properly free resources. */
5385 wl->hw->queues = wl->mac80211_initially_registered_queues;
5386 b43_leds_stop(wldev);
5387 ieee80211_unregister_hw(wl->hw);
5388
5389 b43_one_core_detach(wldev->dev);
5390
5391 b43_leds_unregister(wl);
5392
5393 ieee80211_free_hw(wl->hw);
5394 }
5395
5396 static struct bcma_driver b43_bcma_driver = {
5397 .name = KBUILD_MODNAME,
5398 .id_table = b43_bcma_tbl,
5399 .probe = b43_bcma_probe,
5400 .remove = b43_bcma_remove,
5401 };
5402 #endif
5403
5404 #ifdef CONFIG_B43_SSB
5405 static
b43_ssb_probe(struct ssb_device * sdev,const struct ssb_device_id * id)5406 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5407 {
5408 struct b43_bus_dev *dev;
5409 struct b43_wl *wl;
5410 int err;
5411 int first = 0;
5412
5413 dev = b43_bus_dev_ssb_init(sdev);
5414 if (!dev)
5415 return -ENOMEM;
5416
5417 wl = ssb_get_devtypedata(sdev);
5418 if (!wl) {
5419 /* Probing the first core. Must setup common struct b43_wl */
5420 first = 1;
5421 b43_sprom_fixup(sdev->bus);
5422 wl = b43_wireless_init(dev);
5423 if (IS_ERR(wl)) {
5424 err = PTR_ERR(wl);
5425 goto out;
5426 }
5427 ssb_set_devtypedata(sdev, wl);
5428 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5429 }
5430 err = b43_one_core_attach(dev, wl);
5431 if (err)
5432 goto err_wireless_exit;
5433
5434 /* setup and start work to load firmware */
5435 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5436 schedule_work(&wl->firmware_load);
5437
5438 out:
5439 return err;
5440
5441 err_wireless_exit:
5442 if (first)
5443 b43_wireless_exit(dev, wl);
5444 return err;
5445 }
5446
b43_ssb_remove(struct ssb_device * sdev)5447 static void b43_ssb_remove(struct ssb_device *sdev)
5448 {
5449 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5450 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5451 struct b43_bus_dev *dev = wldev->dev;
5452
5453 /* We must cancel any work here before unregistering from ieee80211,
5454 * as the ieee80211 unreg will destroy the workqueue. */
5455 cancel_work_sync(&wldev->restart_work);
5456
5457 B43_WARN_ON(!wl);
5458 if (!wldev->fw.ucode.data)
5459 return; /* NULL if firmware never loaded */
5460 if (wl->current_dev == wldev) {
5461 /* Restore the queues count before unregistering, because firmware detect
5462 * might have modified it. Restoring is important, so the networking
5463 * stack can properly free resources. */
5464 wl->hw->queues = wl->mac80211_initially_registered_queues;
5465 b43_leds_stop(wldev);
5466 ieee80211_unregister_hw(wl->hw);
5467 }
5468
5469 b43_one_core_detach(dev);
5470
5471 if (list_empty(&wl->devlist)) {
5472 b43_leds_unregister(wl);
5473 /* Last core on the chip unregistered.
5474 * We can destroy common struct b43_wl.
5475 */
5476 b43_wireless_exit(dev, wl);
5477 }
5478 }
5479
5480 static struct ssb_driver b43_ssb_driver = {
5481 .name = KBUILD_MODNAME,
5482 .id_table = b43_ssb_tbl,
5483 .probe = b43_ssb_probe,
5484 .remove = b43_ssb_remove,
5485 };
5486 #endif /* CONFIG_B43_SSB */
5487
5488 /* Perform a hardware reset. This can be called from any context. */
b43_controller_restart(struct b43_wldev * dev,const char * reason)5489 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5490 {
5491 /* Must avoid requeueing, if we are in shutdown. */
5492 if (b43_status(dev) < B43_STAT_INITIALIZED)
5493 return;
5494 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5495 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5496 }
5497
b43_print_driverinfo(void)5498 static void b43_print_driverinfo(void)
5499 {
5500 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5501 *feat_leds = "", *feat_sdio = "";
5502
5503 #ifdef CONFIG_B43_PCI_AUTOSELECT
5504 feat_pci = "P";
5505 #endif
5506 #ifdef CONFIG_B43_PCMCIA
5507 feat_pcmcia = "M";
5508 #endif
5509 #ifdef CONFIG_B43_PHY_N
5510 feat_nphy = "N";
5511 #endif
5512 #ifdef CONFIG_B43_LEDS
5513 feat_leds = "L";
5514 #endif
5515 #ifdef CONFIG_B43_SDIO
5516 feat_sdio = "S";
5517 #endif
5518 printk(KERN_INFO "Broadcom 43xx driver loaded "
5519 "[ Features: %s%s%s%s%s ]\n",
5520 feat_pci, feat_pcmcia, feat_nphy,
5521 feat_leds, feat_sdio);
5522 }
5523
b43_init(void)5524 static int __init b43_init(void)
5525 {
5526 int err;
5527
5528 b43_debugfs_init();
5529 err = b43_pcmcia_init();
5530 if (err)
5531 goto err_dfs_exit;
5532 err = b43_sdio_init();
5533 if (err)
5534 goto err_pcmcia_exit;
5535 #ifdef CONFIG_B43_BCMA
5536 err = bcma_driver_register(&b43_bcma_driver);
5537 if (err)
5538 goto err_sdio_exit;
5539 #endif
5540 #ifdef CONFIG_B43_SSB
5541 err = ssb_driver_register(&b43_ssb_driver);
5542 if (err)
5543 goto err_bcma_driver_exit;
5544 #endif
5545 b43_print_driverinfo();
5546
5547 return err;
5548
5549 #ifdef CONFIG_B43_SSB
5550 err_bcma_driver_exit:
5551 #endif
5552 #ifdef CONFIG_B43_BCMA
5553 bcma_driver_unregister(&b43_bcma_driver);
5554 err_sdio_exit:
5555 #endif
5556 b43_sdio_exit();
5557 err_pcmcia_exit:
5558 b43_pcmcia_exit();
5559 err_dfs_exit:
5560 b43_debugfs_exit();
5561 return err;
5562 }
5563
b43_exit(void)5564 static void __exit b43_exit(void)
5565 {
5566 #ifdef CONFIG_B43_SSB
5567 ssb_driver_unregister(&b43_ssb_driver);
5568 #endif
5569 #ifdef CONFIG_B43_BCMA
5570 bcma_driver_unregister(&b43_bcma_driver);
5571 #endif
5572 b43_sdio_exit();
5573 b43_pcmcia_exit();
5574 b43_debugfs_exit();
5575 }
5576
5577 module_init(b43_init)
5578 module_exit(b43_exit)
5579