1 /* linux/arch/arm/plat-s5p/clock.c
2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P - Common clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/device.h>
21 #include <linux/io.h>
22 #include <asm/div64.h>
23
24 #include <mach/regs-clock.h>
25
26 #include <plat/clock.h>
27 #include <plat/clock-clksrc.h>
28 #include <plat/s5p-clock.h>
29
30 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
31 * clk_ext_xtal_mux.
32 */
33 struct clk clk_ext_xtal_mux = {
34 .name = "ext_xtal",
35 .id = -1,
36 };
37
38 struct clk clk_xusbxti = {
39 .name = "xusbxti",
40 .id = -1,
41 .rate = 24000000,
42 };
43
44 struct clk s5p_clk_27m = {
45 .name = "clk_27m",
46 .id = -1,
47 .rate = 27000000,
48 };
49
50 /* 48MHz USB Phy clock output */
51 struct clk clk_48m = {
52 .name = "clk_48m",
53 .id = -1,
54 .rate = 48000000,
55 };
56
57 /* APLL clock output
58 * No need .ctrlbit, this is always on
59 */
60 struct clk clk_fout_apll = {
61 .name = "fout_apll",
62 .id = -1,
63 };
64
65 /* BPLL clock output */
66
67 struct clk clk_fout_bpll = {
68 .name = "fout_bpll",
69 .id = -1,
70 };
71
72 /* CPLL clock output */
73
74 struct clk clk_fout_cpll = {
75 .name = "fout_cpll",
76 .id = -1,
77 };
78
79 /* MPLL clock output
80 * No need .ctrlbit, this is always on
81 */
82 struct clk clk_fout_mpll = {
83 .name = "fout_mpll",
84 .id = -1,
85 };
86
87 /* EPLL clock output */
88 struct clk clk_fout_epll = {
89 .name = "fout_epll",
90 .id = -1,
91 .ctrlbit = (1 << 31),
92 };
93
94 /* DPLL clock output */
95 struct clk clk_fout_dpll = {
96 .name = "fout_dpll",
97 .id = -1,
98 .ctrlbit = (1 << 31),
99 };
100
101 /* VPLL clock output */
102 struct clk clk_fout_vpll = {
103 .name = "fout_vpll",
104 .id = -1,
105 .ctrlbit = (1 << 31),
106 };
107
108 /* Possible clock sources for APLL Mux */
109 static struct clk *clk_src_apll_list[] = {
110 [0] = &clk_fin_apll,
111 [1] = &clk_fout_apll,
112 };
113
114 struct clksrc_sources clk_src_apll = {
115 .sources = clk_src_apll_list,
116 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
117 };
118
119 /* Possible clock sources for BPLL Mux */
120 static struct clk *clk_src_bpll_list[] = {
121 [0] = &clk_fin_bpll,
122 [1] = &clk_fout_bpll,
123 };
124
125 struct clksrc_sources clk_src_bpll = {
126 .sources = clk_src_bpll_list,
127 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
128 };
129
130 /* Possible clock sources for CPLL Mux */
131 static struct clk *clk_src_cpll_list[] = {
132 [0] = &clk_fin_cpll,
133 [1] = &clk_fout_cpll,
134 };
135
136 struct clksrc_sources clk_src_cpll = {
137 .sources = clk_src_cpll_list,
138 .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
139 };
140
141 /* Possible clock sources for MPLL Mux */
142 static struct clk *clk_src_mpll_list[] = {
143 [0] = &clk_fin_mpll,
144 [1] = &clk_fout_mpll,
145 };
146
147 struct clksrc_sources clk_src_mpll = {
148 .sources = clk_src_mpll_list,
149 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
150 };
151
152 /* Possible clock sources for EPLL Mux */
153 static struct clk *clk_src_epll_list[] = {
154 [0] = &clk_fin_epll,
155 [1] = &clk_fout_epll,
156 };
157
158 struct clksrc_sources clk_src_epll = {
159 .sources = clk_src_epll_list,
160 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
161 };
162
163 /* Possible clock sources for DPLL Mux */
164 static struct clk *clk_src_dpll_list[] = {
165 [0] = &clk_fin_dpll,
166 [1] = &clk_fout_dpll,
167 };
168
169 struct clksrc_sources clk_src_dpll = {
170 .sources = clk_src_dpll_list,
171 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
172 };
173
174 struct clk clk_vpll = {
175 .name = "vpll",
176 .id = -1,
177 };
178
s5p_gatectrl(void __iomem * reg,struct clk * clk,int enable)179 int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
180 {
181 unsigned int ctrlbit = clk->ctrlbit;
182 u32 con;
183
184 con = __raw_readl(reg);
185 con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
186 __raw_writel(con, reg);
187 return 0;
188 }
189
s5p_epll_enable(struct clk * clk,int enable)190 int s5p_epll_enable(struct clk *clk, int enable)
191 {
192 unsigned int ctrlbit = clk->ctrlbit;
193 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
194
195 if (enable)
196 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
197 else
198 __raw_writel(epll_con, S5P_EPLL_CON);
199
200 return 0;
201 }
202
s5p_epll_get_rate(struct clk * clk)203 unsigned long s5p_epll_get_rate(struct clk *clk)
204 {
205 return clk->rate;
206 }
207
s5p_spdif_set_rate(struct clk * clk,unsigned long rate)208 int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
209 {
210 struct clk *pclk;
211 int ret;
212
213 pclk = clk_get_parent(clk);
214 if (IS_ERR(pclk))
215 return -EINVAL;
216
217 ret = pclk->ops->set_rate(pclk, rate);
218 clk_put(pclk);
219
220 return ret;
221 }
222
s5p_spdif_get_rate(struct clk * clk)223 unsigned long s5p_spdif_get_rate(struct clk *clk)
224 {
225 struct clk *pclk;
226 int rate;
227
228 pclk = clk_get_parent(clk);
229 if (IS_ERR(pclk))
230 return -EINVAL;
231
232 rate = pclk->ops->get_rate(pclk);
233 clk_put(pclk);
234
235 return rate;
236 }
237
238 struct clk_ops s5p_sclk_spdif_ops = {
239 .set_rate = s5p_spdif_set_rate,
240 .get_rate = s5p_spdif_get_rate,
241 };
242
243 static struct clk *s5p_clks[] __initdata = {
244 &clk_ext_xtal_mux,
245 &clk_48m,
246 &s5p_clk_27m,
247 &clk_fout_apll,
248 &clk_fout_mpll,
249 &clk_fout_epll,
250 &clk_fout_dpll,
251 &clk_fout_vpll,
252 &clk_vpll,
253 &clk_xusbxti,
254 };
255
s5p_register_clocks(unsigned long xtal_freq)256 void __init s5p_register_clocks(unsigned long xtal_freq)
257 {
258 int ret;
259
260 clk_ext_xtal_mux.rate = xtal_freq;
261
262 ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
263 if (ret > 0)
264 printk(KERN_ERR "Failed to register s5p clocks\n");
265 }
266