• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * linux/arch/arm/mach-omap2/prcm.c
3  *
4  * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5  *
6  * Copyright (C) 2005 Nokia Corporation
7  *
8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
9  *
10  * Copyright (C) 2007 Texas Instruments, Inc.
11  * Rajendra Nayak <rnayak@ti.com>
12  *
13  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14  * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20 
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/clk.h>
24 #include <linux/io.h>
25 #include <linux/delay.h>
26 #include <linux/export.h>
27 
28 #include "common.h"
29 #include <plat/prcm.h>
30 #include <plat/irqs.h>
31 
32 #include "clock.h"
33 #include "clock2xxx.h"
34 #include "cm2xxx_3xxx.h"
35 #include "prm2xxx_3xxx.h"
36 #include "prm44xx.h"
37 #include "prminst44xx.h"
38 #include "prm-regbits-24xx.h"
39 #include "prm-regbits-44xx.h"
40 #include "control.h"
41 
42 void __iomem *prm_base;
43 void __iomem *cm_base;
44 void __iomem *cm2_base;
45 
46 #define MAX_MODULE_ENABLE_WAIT		100000
47 
omap_prcm_get_reset_sources(void)48 u32 omap_prcm_get_reset_sources(void)
49 {
50 	/* XXX This presumably needs modification for 34XX */
51 	if (cpu_is_omap24xx() || cpu_is_omap34xx())
52 		return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
53 	if (cpu_is_omap44xx())
54 		return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
55 
56 	return 0;
57 }
58 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
59 
60 /* Resets clock rates and reboots the system. Only called from system.h */
omap_prcm_restart(char mode,const char * cmd)61 void omap_prcm_restart(char mode, const char *cmd)
62 {
63 	s16 prcm_offs = 0;
64 
65 	if (cpu_is_omap24xx()) {
66 		omap2xxx_clk_prepare_for_reboot();
67 
68 		prcm_offs = WKUP_MOD;
69 	} else if (cpu_is_omap34xx()) {
70 		prcm_offs = OMAP3430_GR_MOD;
71 		omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
72 	} else if (cpu_is_omap44xx()) {
73 		omap4_prminst_global_warm_sw_reset(); /* never returns */
74 	} else {
75 		WARN_ON(1);
76 	}
77 
78 	/*
79 	 * As per Errata i520, in some cases, user will not be able to
80 	 * access DDR memory after warm-reset.
81 	 * This situation occurs while the warm-reset happens during a read
82 	 * access to DDR memory. In that particular condition, DDR memory
83 	 * does not respond to a corrupted read command due to the warm
84 	 * reset occurrence but SDRC is waiting for read completion.
85 	 * SDRC is not sensitive to the warm reset, but the interconnect is
86 	 * reset on the fly, thus causing a misalignment between SDRC logic,
87 	 * interconnect logic and DDR memory state.
88 	 * WORKAROUND:
89 	 * Steps to perform before a Warm reset is trigged:
90 	 * 1. enable self-refresh on idle request
91 	 * 2. put SDRC in idle
92 	 * 3. wait until SDRC goes to idle
93 	 * 4. generate SW reset (Global SW reset)
94 	 *
95 	 * Steps to be performed after warm reset occurs (in bootloader):
96 	 * if HW warm reset is the source, apply below steps before any
97 	 * accesses to SDRAM:
98 	 * 1. Reset SMS and SDRC and wait till reset is complete
99 	 * 2. Re-initialize SMS, SDRC and memory
100 	 *
101 	 * NOTE: Above work around is required only if arch reset is implemented
102 	 * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
103 	 * the WA since it resets SDRC as well as part of cold reset.
104 	 */
105 
106 	/* XXX should be moved to some OMAP2/3 specific code */
107 	omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
108 				   OMAP2_RM_RSTCTRL);
109 	omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
110 }
111 
112 /**
113  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
114  * @reg: physical address of module IDLEST register
115  * @mask: value to mask against to determine if the module is active
116  * @idlest: idle state indicator (0 or 1) for the clock
117  * @name: name of the clock (for printk)
118  *
119  * Returns 1 if the module indicated readiness in time, or 0 if it
120  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
121  *
122  * XXX This function is deprecated.  It should be removed once the
123  * hwmod conversion is complete.
124  */
omap2_cm_wait_idlest(void __iomem * reg,u32 mask,u8 idlest,const char * name)125 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
126 				const char *name)
127 {
128 	int i = 0;
129 	int ena = 0;
130 
131 	if (idlest)
132 		ena = 0;
133 	else
134 		ena = mask;
135 
136 	/* Wait for lock */
137 	omap_test_timeout(((__raw_readl(reg) & mask) == ena),
138 			  MAX_MODULE_ENABLE_WAIT, i);
139 
140 	if (i < MAX_MODULE_ENABLE_WAIT)
141 		pr_debug("cm: Module associated with clock %s ready after %d "
142 			 "loops\n", name, i);
143 	else
144 		pr_err("cm: Module associated with clock %s didn't enable in "
145 		       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
146 
147 	return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
148 };
149 
omap2_set_globals_prcm(struct omap_globals * omap2_globals)150 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
151 {
152 	if (omap2_globals->prm)
153 		prm_base = omap2_globals->prm;
154 	if (omap2_globals->cm)
155 		cm_base = omap2_globals->cm;
156 	if (omap2_globals->cm2)
157 		cm2_base = omap2_globals->cm2;
158 }
159