1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "drm_crtc_helper.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "drm_dp_helper.h"
39
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44 #define DP_LINK_CONFIGURATION_SIZE 9
45
46 struct intel_dp {
47 struct intel_encoder base;
48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
51 bool has_audio;
52 enum hdmi_force_audio force_audio;
53 uint32_t color_range;
54 int dpms_mode;
55 uint8_t link_bw;
56 uint8_t lane_count;
57 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
60 bool is_pch_edp;
61 uint8_t train_set[4];
62 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
67 struct drm_display_mode *panel_fixed_mode; /* for eDP */
68 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd;
70 };
71
72 /**
73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
74 * @intel_dp: DP struct
75 *
76 * If a CPU or PCH DP output is attached to an eDP panel, this function
77 * will return true, and false otherwise.
78 */
is_edp(struct intel_dp * intel_dp)79 static bool is_edp(struct intel_dp *intel_dp)
80 {
81 return intel_dp->base.type == INTEL_OUTPUT_EDP;
82 }
83
84 /**
85 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
86 * @intel_dp: DP struct
87 *
88 * Returns true if the given DP struct corresponds to a PCH DP port attached
89 * to an eDP panel, false otherwise. Helpful for determining whether we
90 * may need FDI resources for a given DP output or not.
91 */
is_pch_edp(struct intel_dp * intel_dp)92 static bool is_pch_edp(struct intel_dp *intel_dp)
93 {
94 return intel_dp->is_pch_edp;
95 }
96
97 /**
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
100 *
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
102 */
is_cpu_edp(struct intel_dp * intel_dp)103 static bool is_cpu_edp(struct intel_dp *intel_dp)
104 {
105 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
106 }
107
enc_to_intel_dp(struct drm_encoder * encoder)108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
109 {
110 return container_of(encoder, struct intel_dp, base.base);
111 }
112
intel_attached_dp(struct drm_connector * connector)113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
114 {
115 return container_of(intel_attached_encoder(connector),
116 struct intel_dp, base);
117 }
118
119 /**
120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
121 * @encoder: DRM encoder
122 *
123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
124 * by intel_display.c.
125 */
intel_encoder_is_pch_edp(struct drm_encoder * encoder)126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
127 {
128 struct intel_dp *intel_dp;
129
130 if (!encoder)
131 return false;
132
133 intel_dp = enc_to_intel_dp(encoder);
134
135 return is_pch_edp(intel_dp);
136 }
137
138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
140 static void intel_dp_link_down(struct intel_dp *intel_dp);
141
142 void
intel_edp_link_config(struct intel_encoder * intel_encoder,int * lane_num,int * link_bw)143 intel_edp_link_config(struct intel_encoder *intel_encoder,
144 int *lane_num, int *link_bw)
145 {
146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
147
148 *lane_num = intel_dp->lane_count;
149 if (intel_dp->link_bw == DP_LINK_BW_1_62)
150 *link_bw = 162000;
151 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
152 *link_bw = 270000;
153 }
154
155 static int
intel_dp_max_lane_count(struct intel_dp * intel_dp)156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
157 {
158 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
159 switch (max_lane_count) {
160 case 1: case 2: case 4:
161 break;
162 default:
163 max_lane_count = 4;
164 }
165 return max_lane_count;
166 }
167
168 static int
intel_dp_max_link_bw(struct intel_dp * intel_dp)169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
170 {
171 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
172
173 switch (max_link_bw) {
174 case DP_LINK_BW_1_62:
175 case DP_LINK_BW_2_7:
176 break;
177 default:
178 max_link_bw = DP_LINK_BW_1_62;
179 break;
180 }
181 return max_link_bw;
182 }
183
184 static int
intel_dp_link_clock(uint8_t link_bw)185 intel_dp_link_clock(uint8_t link_bw)
186 {
187 if (link_bw == DP_LINK_BW_2_7)
188 return 270000;
189 else
190 return 162000;
191 }
192
193 /*
194 * The units on the numbers in the next two are... bizarre. Examples will
195 * make it clearer; this one parallels an example in the eDP spec.
196 *
197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
198 *
199 * 270000 * 1 * 8 / 10 == 216000
200 *
201 * The actual data capacity of that configuration is 2.16Gbit/s, so the
202 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
203 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
204 * 119000. At 18bpp that's 2142000 kilobits per second.
205 *
206 * Thus the strange-looking division by 10 in intel_dp_link_required, to
207 * get the result in decakilobits instead of kilobits.
208 */
209
210 static int
intel_dp_link_required(int pixel_clock,int bpp)211 intel_dp_link_required(int pixel_clock, int bpp)
212 {
213 return (pixel_clock * bpp + 9) / 10;
214 }
215
216 static int
intel_dp_max_data_rate(int max_link_clock,int max_lanes)217 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
218 {
219 return (max_link_clock * max_lanes * 8) / 10;
220 }
221
222 static bool
intel_dp_adjust_dithering(struct intel_dp * intel_dp,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)223 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
224 struct drm_display_mode *mode,
225 struct drm_display_mode *adjusted_mode)
226 {
227 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
228 int max_lanes = intel_dp_max_lane_count(intel_dp);
229 int max_rate, mode_rate;
230
231 mode_rate = intel_dp_link_required(mode->clock, 24);
232 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
233
234 if (mode_rate > max_rate) {
235 mode_rate = intel_dp_link_required(mode->clock, 18);
236 if (mode_rate > max_rate)
237 return false;
238
239 if (adjusted_mode)
240 adjusted_mode->private_flags
241 |= INTEL_MODE_DP_FORCE_6BPC;
242
243 return true;
244 }
245
246 return true;
247 }
248
249 static int
intel_dp_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)250 intel_dp_mode_valid(struct drm_connector *connector,
251 struct drm_display_mode *mode)
252 {
253 struct intel_dp *intel_dp = intel_attached_dp(connector);
254
255 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
256 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
257 return MODE_PANEL;
258
259 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
260 return MODE_PANEL;
261 }
262
263 if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
264 return MODE_CLOCK_HIGH;
265
266 if (mode->clock < 10000)
267 return MODE_CLOCK_LOW;
268
269 return MODE_OK;
270 }
271
272 static uint32_t
pack_aux(uint8_t * src,int src_bytes)273 pack_aux(uint8_t *src, int src_bytes)
274 {
275 int i;
276 uint32_t v = 0;
277
278 if (src_bytes > 4)
279 src_bytes = 4;
280 for (i = 0; i < src_bytes; i++)
281 v |= ((uint32_t) src[i]) << ((3-i) * 8);
282 return v;
283 }
284
285 static void
unpack_aux(uint32_t src,uint8_t * dst,int dst_bytes)286 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
287 {
288 int i;
289 if (dst_bytes > 4)
290 dst_bytes = 4;
291 for (i = 0; i < dst_bytes; i++)
292 dst[i] = src >> ((3-i) * 8);
293 }
294
295 /* hrawclock is 1/4 the FSB frequency */
296 static int
intel_hrawclk(struct drm_device * dev)297 intel_hrawclk(struct drm_device *dev)
298 {
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 uint32_t clkcfg;
301
302 clkcfg = I915_READ(CLKCFG);
303 switch (clkcfg & CLKCFG_FSB_MASK) {
304 case CLKCFG_FSB_400:
305 return 100;
306 case CLKCFG_FSB_533:
307 return 133;
308 case CLKCFG_FSB_667:
309 return 166;
310 case CLKCFG_FSB_800:
311 return 200;
312 case CLKCFG_FSB_1067:
313 return 266;
314 case CLKCFG_FSB_1333:
315 return 333;
316 /* these two are just a guess; one of them might be right */
317 case CLKCFG_FSB_1600:
318 case CLKCFG_FSB_1600_ALT:
319 return 400;
320 default:
321 return 133;
322 }
323 }
324
ironlake_edp_have_panel_power(struct intel_dp * intel_dp)325 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
326 {
327 struct drm_device *dev = intel_dp->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
329
330 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
331 }
332
ironlake_edp_have_panel_vdd(struct intel_dp * intel_dp)333 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
334 {
335 struct drm_device *dev = intel_dp->base.base.dev;
336 struct drm_i915_private *dev_priv = dev->dev_private;
337
338 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
339 }
340
341 static void
intel_dp_check_edp(struct intel_dp * intel_dp)342 intel_dp_check_edp(struct intel_dp *intel_dp)
343 {
344 struct drm_device *dev = intel_dp->base.base.dev;
345 struct drm_i915_private *dev_priv = dev->dev_private;
346
347 if (!is_edp(intel_dp))
348 return;
349 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
350 WARN(1, "eDP powered off while attempting aux channel communication.\n");
351 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
352 I915_READ(PCH_PP_STATUS),
353 I915_READ(PCH_PP_CONTROL));
354 }
355 }
356
357 static int
intel_dp_aux_ch(struct intel_dp * intel_dp,uint8_t * send,int send_bytes,uint8_t * recv,int recv_size)358 intel_dp_aux_ch(struct intel_dp *intel_dp,
359 uint8_t *send, int send_bytes,
360 uint8_t *recv, int recv_size)
361 {
362 uint32_t output_reg = intel_dp->output_reg;
363 struct drm_device *dev = intel_dp->base.base.dev;
364 struct drm_i915_private *dev_priv = dev->dev_private;
365 uint32_t ch_ctl = output_reg + 0x10;
366 uint32_t ch_data = ch_ctl + 4;
367 int i;
368 int recv_bytes;
369 uint32_t status;
370 uint32_t aux_clock_divider;
371 int try, precharge;
372
373 intel_dp_check_edp(intel_dp);
374 /* The clock divider is based off the hrawclk,
375 * and would like to run at 2MHz. So, take the
376 * hrawclk value and divide by 2 and use that
377 *
378 * Note that PCH attached eDP panels should use a 125MHz input
379 * clock divider.
380 */
381 if (is_cpu_edp(intel_dp)) {
382 if (IS_GEN6(dev) || IS_GEN7(dev))
383 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
384 else
385 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
386 } else if (HAS_PCH_SPLIT(dev))
387 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
388 else
389 aux_clock_divider = intel_hrawclk(dev) / 2;
390
391 if (IS_GEN6(dev))
392 precharge = 3;
393 else
394 precharge = 5;
395
396 /* Try to wait for any previous AUX channel activity */
397 for (try = 0; try < 3; try++) {
398 status = I915_READ(ch_ctl);
399 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
400 break;
401 msleep(1);
402 }
403
404 if (try == 3) {
405 WARN(1, "dp_aux_ch not started status 0x%08x\n",
406 I915_READ(ch_ctl));
407 return -EBUSY;
408 }
409
410 /* Must try at least 3 times according to DP spec */
411 for (try = 0; try < 5; try++) {
412 /* Load the send data into the aux channel data registers */
413 for (i = 0; i < send_bytes; i += 4)
414 I915_WRITE(ch_data + i,
415 pack_aux(send + i, send_bytes - i));
416
417 /* Send the command and wait for it to complete */
418 I915_WRITE(ch_ctl,
419 DP_AUX_CH_CTL_SEND_BUSY |
420 DP_AUX_CH_CTL_TIME_OUT_400us |
421 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
422 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
423 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
424 DP_AUX_CH_CTL_DONE |
425 DP_AUX_CH_CTL_TIME_OUT_ERROR |
426 DP_AUX_CH_CTL_RECEIVE_ERROR);
427 for (;;) {
428 status = I915_READ(ch_ctl);
429 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
430 break;
431 udelay(100);
432 }
433
434 /* Clear done status and any errors */
435 I915_WRITE(ch_ctl,
436 status |
437 DP_AUX_CH_CTL_DONE |
438 DP_AUX_CH_CTL_TIME_OUT_ERROR |
439 DP_AUX_CH_CTL_RECEIVE_ERROR);
440
441 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
442 DP_AUX_CH_CTL_RECEIVE_ERROR))
443 continue;
444 if (status & DP_AUX_CH_CTL_DONE)
445 break;
446 }
447
448 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
449 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
450 return -EBUSY;
451 }
452
453 /* Check for timeout or receive error.
454 * Timeouts occur when the sink is not connected
455 */
456 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
457 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
458 return -EIO;
459 }
460
461 /* Timeouts occur when the device isn't connected, so they're
462 * "normal" -- don't fill the kernel log with these */
463 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
464 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
465 return -ETIMEDOUT;
466 }
467
468 /* Unload any bytes sent back from the other side */
469 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
470 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
471 if (recv_bytes > recv_size)
472 recv_bytes = recv_size;
473
474 for (i = 0; i < recv_bytes; i += 4)
475 unpack_aux(I915_READ(ch_data + i),
476 recv + i, recv_bytes - i);
477
478 return recv_bytes;
479 }
480
481 /* Write data to the aux channel in native mode */
482 static int
intel_dp_aux_native_write(struct intel_dp * intel_dp,uint16_t address,uint8_t * send,int send_bytes)483 intel_dp_aux_native_write(struct intel_dp *intel_dp,
484 uint16_t address, uint8_t *send, int send_bytes)
485 {
486 int ret;
487 uint8_t msg[20];
488 int msg_bytes;
489 uint8_t ack;
490
491 intel_dp_check_edp(intel_dp);
492 if (send_bytes > 16)
493 return -1;
494 msg[0] = AUX_NATIVE_WRITE << 4;
495 msg[1] = address >> 8;
496 msg[2] = address & 0xff;
497 msg[3] = send_bytes - 1;
498 memcpy(&msg[4], send, send_bytes);
499 msg_bytes = send_bytes + 4;
500 for (;;) {
501 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
502 if (ret < 0)
503 return ret;
504 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
505 break;
506 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
507 udelay(100);
508 else
509 return -EIO;
510 }
511 return send_bytes;
512 }
513
514 /* Write a single byte to the aux channel in native mode */
515 static int
intel_dp_aux_native_write_1(struct intel_dp * intel_dp,uint16_t address,uint8_t byte)516 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
517 uint16_t address, uint8_t byte)
518 {
519 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
520 }
521
522 /* read bytes from a native aux channel */
523 static int
intel_dp_aux_native_read(struct intel_dp * intel_dp,uint16_t address,uint8_t * recv,int recv_bytes)524 intel_dp_aux_native_read(struct intel_dp *intel_dp,
525 uint16_t address, uint8_t *recv, int recv_bytes)
526 {
527 uint8_t msg[4];
528 int msg_bytes;
529 uint8_t reply[20];
530 int reply_bytes;
531 uint8_t ack;
532 int ret;
533
534 intel_dp_check_edp(intel_dp);
535 msg[0] = AUX_NATIVE_READ << 4;
536 msg[1] = address >> 8;
537 msg[2] = address & 0xff;
538 msg[3] = recv_bytes - 1;
539
540 msg_bytes = 4;
541 reply_bytes = recv_bytes + 1;
542
543 for (;;) {
544 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
545 reply, reply_bytes);
546 if (ret == 0)
547 return -EPROTO;
548 if (ret < 0)
549 return ret;
550 ack = reply[0];
551 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
552 memcpy(recv, reply + 1, ret - 1);
553 return ret - 1;
554 }
555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
556 udelay(100);
557 else
558 return -EIO;
559 }
560 }
561
562 static int
intel_dp_i2c_aux_ch(struct i2c_adapter * adapter,int mode,uint8_t write_byte,uint8_t * read_byte)563 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
564 uint8_t write_byte, uint8_t *read_byte)
565 {
566 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
567 struct intel_dp *intel_dp = container_of(adapter,
568 struct intel_dp,
569 adapter);
570 uint16_t address = algo_data->address;
571 uint8_t msg[5];
572 uint8_t reply[2];
573 unsigned retry;
574 int msg_bytes;
575 int reply_bytes;
576 int ret;
577
578 intel_dp_check_edp(intel_dp);
579 /* Set up the command byte */
580 if (mode & MODE_I2C_READ)
581 msg[0] = AUX_I2C_READ << 4;
582 else
583 msg[0] = AUX_I2C_WRITE << 4;
584
585 if (!(mode & MODE_I2C_STOP))
586 msg[0] |= AUX_I2C_MOT << 4;
587
588 msg[1] = address >> 8;
589 msg[2] = address;
590
591 switch (mode) {
592 case MODE_I2C_WRITE:
593 msg[3] = 0;
594 msg[4] = write_byte;
595 msg_bytes = 5;
596 reply_bytes = 1;
597 break;
598 case MODE_I2C_READ:
599 msg[3] = 0;
600 msg_bytes = 4;
601 reply_bytes = 2;
602 break;
603 default:
604 msg_bytes = 3;
605 reply_bytes = 1;
606 break;
607 }
608
609 for (retry = 0; retry < 5; retry++) {
610 ret = intel_dp_aux_ch(intel_dp,
611 msg, msg_bytes,
612 reply, reply_bytes);
613 if (ret < 0) {
614 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
615 return ret;
616 }
617
618 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
619 case AUX_NATIVE_REPLY_ACK:
620 /* I2C-over-AUX Reply field is only valid
621 * when paired with AUX ACK.
622 */
623 break;
624 case AUX_NATIVE_REPLY_NACK:
625 DRM_DEBUG_KMS("aux_ch native nack\n");
626 return -EREMOTEIO;
627 case AUX_NATIVE_REPLY_DEFER:
628 /*
629 * For now, just give more slack to branch devices. We
630 * could check the DPCD for I2C bit rate capabilities,
631 * and if available, adjust the interval. We could also
632 * be more careful with DP-to-Legacy adapters where a
633 * long legacy cable may force very low I2C bit rates.
634 */
635 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
636 DP_DWN_STRM_PORT_PRESENT)
637 usleep_range(500, 600);
638 else
639 usleep_range(300, 400);
640 continue;
641 default:
642 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
643 reply[0]);
644 return -EREMOTEIO;
645 }
646
647 switch (reply[0] & AUX_I2C_REPLY_MASK) {
648 case AUX_I2C_REPLY_ACK:
649 if (mode == MODE_I2C_READ) {
650 *read_byte = reply[1];
651 }
652 return reply_bytes - 1;
653 case AUX_I2C_REPLY_NACK:
654 DRM_DEBUG_KMS("aux_i2c nack\n");
655 return -EREMOTEIO;
656 case AUX_I2C_REPLY_DEFER:
657 DRM_DEBUG_KMS("aux_i2c defer\n");
658 udelay(100);
659 break;
660 default:
661 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
662 return -EREMOTEIO;
663 }
664 }
665
666 DRM_ERROR("too many retries, giving up\n");
667 return -EREMOTEIO;
668 }
669
670 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
671 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
672
673 static int
intel_dp_i2c_init(struct intel_dp * intel_dp,struct intel_connector * intel_connector,const char * name)674 intel_dp_i2c_init(struct intel_dp *intel_dp,
675 struct intel_connector *intel_connector, const char *name)
676 {
677 int ret;
678
679 DRM_DEBUG_KMS("i2c_init %s\n", name);
680 intel_dp->algo.running = false;
681 intel_dp->algo.address = 0;
682 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
683
684 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
685 intel_dp->adapter.owner = THIS_MODULE;
686 intel_dp->adapter.class = I2C_CLASS_DDC;
687 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
688 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
689 intel_dp->adapter.algo_data = &intel_dp->algo;
690 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
691
692 ironlake_edp_panel_vdd_on(intel_dp);
693 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
694 ironlake_edp_panel_vdd_off(intel_dp, false);
695 return ret;
696 }
697
698 static bool
intel_dp_mode_fixup(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)699 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
700 struct drm_display_mode *adjusted_mode)
701 {
702 struct drm_device *dev = encoder->dev;
703 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
704 int lane_count, clock;
705 int max_lane_count = intel_dp_max_lane_count(intel_dp);
706 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
707 int bpp;
708 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
709
710 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
711 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
712 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
713 mode, adjusted_mode);
714 /*
715 * the mode->clock is used to calculate the Data&Link M/N
716 * of the pipe. For the eDP the fixed clock should be used.
717 */
718 mode->clock = intel_dp->panel_fixed_mode->clock;
719 }
720
721 if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
722 return false;
723
724 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
725
726 for (clock = 0; clock <= max_clock; clock++) {
727 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
728 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
729
730 if (intel_dp_link_required(mode->clock, bpp)
731 <= link_avail) {
732 intel_dp->link_bw = bws[clock];
733 intel_dp->lane_count = lane_count;
734 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
735 DRM_DEBUG_KMS("Display port link bw %02x lane "
736 "count %d clock %d\n",
737 intel_dp->link_bw, intel_dp->lane_count,
738 adjusted_mode->clock);
739 return true;
740 }
741 }
742 }
743
744 return false;
745 }
746
747 struct intel_dp_m_n {
748 uint32_t tu;
749 uint32_t gmch_m;
750 uint32_t gmch_n;
751 uint32_t link_m;
752 uint32_t link_n;
753 };
754
755 static void
intel_reduce_ratio(uint32_t * num,uint32_t * den)756 intel_reduce_ratio(uint32_t *num, uint32_t *den)
757 {
758 while (*num > 0xffffff || *den > 0xffffff) {
759 *num >>= 1;
760 *den >>= 1;
761 }
762 }
763
764 static void
intel_dp_compute_m_n(int bpp,int nlanes,int pixel_clock,int link_clock,struct intel_dp_m_n * m_n)765 intel_dp_compute_m_n(int bpp,
766 int nlanes,
767 int pixel_clock,
768 int link_clock,
769 struct intel_dp_m_n *m_n)
770 {
771 m_n->tu = 64;
772 m_n->gmch_m = (pixel_clock * bpp) >> 3;
773 m_n->gmch_n = link_clock * nlanes;
774 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
775 m_n->link_m = pixel_clock;
776 m_n->link_n = link_clock;
777 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
778 }
779
780 void
intel_dp_set_m_n(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)781 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
782 struct drm_display_mode *adjusted_mode)
783 {
784 struct drm_device *dev = crtc->dev;
785 struct drm_mode_config *mode_config = &dev->mode_config;
786 struct drm_encoder *encoder;
787 struct drm_i915_private *dev_priv = dev->dev_private;
788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
789 int lane_count = 4;
790 struct intel_dp_m_n m_n;
791 int pipe = intel_crtc->pipe;
792
793 /*
794 * Find the lane count in the intel_encoder private
795 */
796 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
797 struct intel_dp *intel_dp;
798
799 if (encoder->crtc != crtc)
800 continue;
801
802 intel_dp = enc_to_intel_dp(encoder);
803 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
804 intel_dp->base.type == INTEL_OUTPUT_EDP)
805 {
806 lane_count = intel_dp->lane_count;
807 break;
808 }
809 }
810
811 /*
812 * Compute the GMCH and Link ratios. The '3' here is
813 * the number of bytes_per_pixel post-LUT, which we always
814 * set up for 8-bits of R/G/B, or 3 bytes total.
815 */
816 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
817 mode->clock, adjusted_mode->clock, &m_n);
818
819 if (HAS_PCH_SPLIT(dev)) {
820 I915_WRITE(TRANSDATA_M1(pipe),
821 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
822 m_n.gmch_m);
823 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
824 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
825 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
826 } else {
827 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
828 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
829 m_n.gmch_m);
830 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
831 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
832 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
833 }
834 }
835
836 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
837 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
838
839 static void
intel_dp_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)840 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
841 struct drm_display_mode *adjusted_mode)
842 {
843 struct drm_device *dev = encoder->dev;
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
846 struct drm_crtc *crtc = intel_dp->base.base.crtc;
847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
848
849 /* Turn on the eDP PLL if needed */
850 if (is_edp(intel_dp)) {
851 if (!is_pch_edp(intel_dp))
852 ironlake_edp_pll_on(encoder);
853 else
854 ironlake_edp_pll_off(encoder);
855 }
856
857 /*
858 * There are four kinds of DP registers:
859 *
860 * IBX PCH
861 * SNB CPU
862 * IVB CPU
863 * CPT PCH
864 *
865 * IBX PCH and CPU are the same for almost everything,
866 * except that the CPU DP PLL is configured in this
867 * register
868 *
869 * CPT PCH is quite different, having many bits moved
870 * to the TRANS_DP_CTL register instead. That
871 * configuration happens (oddly) in ironlake_pch_enable
872 */
873
874 /* Preserve the BIOS-computed detected bit. This is
875 * supposed to be read-only.
876 */
877 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
878 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
879
880 /* Handle DP bits in common between all three register formats */
881
882 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
883
884 switch (intel_dp->lane_count) {
885 case 1:
886 intel_dp->DP |= DP_PORT_WIDTH_1;
887 break;
888 case 2:
889 intel_dp->DP |= DP_PORT_WIDTH_2;
890 break;
891 case 4:
892 intel_dp->DP |= DP_PORT_WIDTH_4;
893 break;
894 }
895 if (intel_dp->has_audio) {
896 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
897 pipe_name(intel_crtc->pipe));
898 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
899 intel_write_eld(encoder, adjusted_mode);
900 }
901 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
902 intel_dp->link_configuration[0] = intel_dp->link_bw;
903 intel_dp->link_configuration[1] = intel_dp->lane_count;
904 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
905 /*
906 * Check for DPCD version > 1.1 and enhanced framing support
907 */
908 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
909 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
910 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
911 }
912
913 /* Split out the IBX/CPU vs CPT settings */
914
915 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
916 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
917 intel_dp->DP |= DP_SYNC_HS_HIGH;
918 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
919 intel_dp->DP |= DP_SYNC_VS_HIGH;
920 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
921
922 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
923 intel_dp->DP |= DP_ENHANCED_FRAMING;
924
925 intel_dp->DP |= intel_crtc->pipe << 29;
926
927 /* don't miss out required setting for eDP */
928 intel_dp->DP |= DP_PLL_ENABLE;
929 if (adjusted_mode->clock < 200000)
930 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
931 else
932 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
933 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
934 intel_dp->DP |= intel_dp->color_range;
935
936 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
937 intel_dp->DP |= DP_SYNC_HS_HIGH;
938 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
939 intel_dp->DP |= DP_SYNC_VS_HIGH;
940 intel_dp->DP |= DP_LINK_TRAIN_OFF;
941
942 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
943 intel_dp->DP |= DP_ENHANCED_FRAMING;
944
945 if (intel_crtc->pipe == 1)
946 intel_dp->DP |= DP_PIPEB_SELECT;
947
948 if (is_cpu_edp(intel_dp)) {
949 /* don't miss out required setting for eDP */
950 intel_dp->DP |= DP_PLL_ENABLE;
951 if (adjusted_mode->clock < 200000)
952 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
953 else
954 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
955 }
956 } else {
957 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
958 }
959 }
960
961 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
962 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
963
964 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
965 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
966
967 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
968 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
969
ironlake_wait_panel_status(struct intel_dp * intel_dp,u32 mask,u32 value)970 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
971 u32 mask,
972 u32 value)
973 {
974 struct drm_device *dev = intel_dp->base.base.dev;
975 struct drm_i915_private *dev_priv = dev->dev_private;
976
977 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
978 mask, value,
979 I915_READ(PCH_PP_STATUS),
980 I915_READ(PCH_PP_CONTROL));
981
982 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
983 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
984 I915_READ(PCH_PP_STATUS),
985 I915_READ(PCH_PP_CONTROL));
986 }
987 }
988
ironlake_wait_panel_on(struct intel_dp * intel_dp)989 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
990 {
991 DRM_DEBUG_KMS("Wait for panel power on\n");
992 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
993 }
994
ironlake_wait_panel_off(struct intel_dp * intel_dp)995 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
996 {
997 DRM_DEBUG_KMS("Wait for panel power off time\n");
998 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
999 }
1000
ironlake_wait_panel_power_cycle(struct intel_dp * intel_dp)1001 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1002 {
1003 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1004 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1005 }
1006
1007
1008 /* Read the current pp_control value, unlocking the register if it
1009 * is locked
1010 */
1011
ironlake_get_pp_control(struct drm_i915_private * dev_priv)1012 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1013 {
1014 u32 control = I915_READ(PCH_PP_CONTROL);
1015
1016 control &= ~PANEL_UNLOCK_MASK;
1017 control |= PANEL_UNLOCK_REGS;
1018 return control;
1019 }
1020
ironlake_edp_panel_vdd_on(struct intel_dp * intel_dp)1021 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1022 {
1023 struct drm_device *dev = intel_dp->base.base.dev;
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 u32 pp;
1026
1027 if (!is_edp(intel_dp))
1028 return;
1029 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1030
1031 WARN(intel_dp->want_panel_vdd,
1032 "eDP VDD already requested on\n");
1033
1034 intel_dp->want_panel_vdd = true;
1035
1036 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1037 DRM_DEBUG_KMS("eDP VDD already on\n");
1038 return;
1039 }
1040
1041 if (!ironlake_edp_have_panel_power(intel_dp))
1042 ironlake_wait_panel_power_cycle(intel_dp);
1043
1044 pp = ironlake_get_pp_control(dev_priv);
1045 pp |= EDP_FORCE_VDD;
1046 I915_WRITE(PCH_PP_CONTROL, pp);
1047 POSTING_READ(PCH_PP_CONTROL);
1048 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1049 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1050
1051 /*
1052 * If the panel wasn't on, delay before accessing aux channel
1053 */
1054 if (!ironlake_edp_have_panel_power(intel_dp)) {
1055 DRM_DEBUG_KMS("eDP was not running\n");
1056 msleep(intel_dp->panel_power_up_delay);
1057 }
1058 }
1059
ironlake_panel_vdd_off_sync(struct intel_dp * intel_dp)1060 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1061 {
1062 struct drm_device *dev = intel_dp->base.base.dev;
1063 struct drm_i915_private *dev_priv = dev->dev_private;
1064 u32 pp;
1065
1066 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1067 pp = ironlake_get_pp_control(dev_priv);
1068 pp &= ~EDP_FORCE_VDD;
1069 I915_WRITE(PCH_PP_CONTROL, pp);
1070 POSTING_READ(PCH_PP_CONTROL);
1071
1072 /* Make sure sequencer is idle before allowing subsequent activity */
1073 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1074 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1075
1076 msleep(intel_dp->panel_power_down_delay);
1077 }
1078 }
1079
ironlake_panel_vdd_work(struct work_struct * __work)1080 static void ironlake_panel_vdd_work(struct work_struct *__work)
1081 {
1082 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1083 struct intel_dp, panel_vdd_work);
1084 struct drm_device *dev = intel_dp->base.base.dev;
1085
1086 mutex_lock(&dev->mode_config.mutex);
1087 ironlake_panel_vdd_off_sync(intel_dp);
1088 mutex_unlock(&dev->mode_config.mutex);
1089 }
1090
ironlake_edp_panel_vdd_off(struct intel_dp * intel_dp,bool sync)1091 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1092 {
1093 if (!is_edp(intel_dp))
1094 return;
1095
1096 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1097 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1098
1099 intel_dp->want_panel_vdd = false;
1100
1101 if (sync) {
1102 ironlake_panel_vdd_off_sync(intel_dp);
1103 } else {
1104 /*
1105 * Queue the timer to fire a long
1106 * time from now (relative to the power down delay)
1107 * to keep the panel power up across a sequence of operations
1108 */
1109 schedule_delayed_work(&intel_dp->panel_vdd_work,
1110 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1111 }
1112 }
1113
ironlake_edp_panel_on(struct intel_dp * intel_dp)1114 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1115 {
1116 struct drm_device *dev = intel_dp->base.base.dev;
1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118 u32 pp;
1119
1120 if (!is_edp(intel_dp))
1121 return;
1122
1123 DRM_DEBUG_KMS("Turn eDP power on\n");
1124
1125 if (ironlake_edp_have_panel_power(intel_dp)) {
1126 DRM_DEBUG_KMS("eDP power already on\n");
1127 return;
1128 }
1129
1130 ironlake_wait_panel_power_cycle(intel_dp);
1131
1132 pp = ironlake_get_pp_control(dev_priv);
1133 if (IS_GEN5(dev)) {
1134 /* ILK workaround: disable reset around power sequence */
1135 pp &= ~PANEL_POWER_RESET;
1136 I915_WRITE(PCH_PP_CONTROL, pp);
1137 POSTING_READ(PCH_PP_CONTROL);
1138 }
1139
1140 pp |= POWER_TARGET_ON;
1141 if (!IS_GEN5(dev))
1142 pp |= PANEL_POWER_RESET;
1143
1144 I915_WRITE(PCH_PP_CONTROL, pp);
1145 POSTING_READ(PCH_PP_CONTROL);
1146
1147 ironlake_wait_panel_on(intel_dp);
1148
1149 if (IS_GEN5(dev)) {
1150 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1151 I915_WRITE(PCH_PP_CONTROL, pp);
1152 POSTING_READ(PCH_PP_CONTROL);
1153 }
1154 }
1155
ironlake_edp_panel_off(struct intel_dp * intel_dp)1156 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1157 {
1158 struct drm_device *dev = intel_dp->base.base.dev;
1159 struct drm_i915_private *dev_priv = dev->dev_private;
1160 u32 pp;
1161
1162 if (!is_edp(intel_dp))
1163 return;
1164
1165 DRM_DEBUG_KMS("Turn eDP power off\n");
1166
1167 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1168
1169 pp = ironlake_get_pp_control(dev_priv);
1170 /* We need to switch off panel power _and_ force vdd, for otherwise some
1171 * panels get very unhappy and cease to work. */
1172 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1173 I915_WRITE(PCH_PP_CONTROL, pp);
1174 POSTING_READ(PCH_PP_CONTROL);
1175
1176 intel_dp->want_panel_vdd = false;
1177
1178 ironlake_wait_panel_off(intel_dp);
1179 }
1180
ironlake_edp_backlight_on(struct intel_dp * intel_dp)1181 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1182 {
1183 struct drm_device *dev = intel_dp->base.base.dev;
1184 struct drm_i915_private *dev_priv = dev->dev_private;
1185 u32 pp;
1186
1187 if (!is_edp(intel_dp))
1188 return;
1189
1190 DRM_DEBUG_KMS("\n");
1191 /*
1192 * If we enable the backlight right away following a panel power
1193 * on, we may see slight flicker as the panel syncs with the eDP
1194 * link. So delay a bit to make sure the image is solid before
1195 * allowing it to appear.
1196 */
1197 msleep(intel_dp->backlight_on_delay);
1198 pp = ironlake_get_pp_control(dev_priv);
1199 pp |= EDP_BLC_ENABLE;
1200 I915_WRITE(PCH_PP_CONTROL, pp);
1201 POSTING_READ(PCH_PP_CONTROL);
1202 }
1203
ironlake_edp_backlight_off(struct intel_dp * intel_dp)1204 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1205 {
1206 struct drm_device *dev = intel_dp->base.base.dev;
1207 struct drm_i915_private *dev_priv = dev->dev_private;
1208 u32 pp;
1209
1210 if (!is_edp(intel_dp))
1211 return;
1212
1213 DRM_DEBUG_KMS("\n");
1214 pp = ironlake_get_pp_control(dev_priv);
1215 pp &= ~EDP_BLC_ENABLE;
1216 I915_WRITE(PCH_PP_CONTROL, pp);
1217 POSTING_READ(PCH_PP_CONTROL);
1218 msleep(intel_dp->backlight_off_delay);
1219 }
1220
ironlake_edp_pll_on(struct drm_encoder * encoder)1221 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1222 {
1223 struct drm_device *dev = encoder->dev;
1224 struct drm_i915_private *dev_priv = dev->dev_private;
1225 u32 dpa_ctl;
1226
1227 DRM_DEBUG_KMS("\n");
1228 dpa_ctl = I915_READ(DP_A);
1229 dpa_ctl |= DP_PLL_ENABLE;
1230 I915_WRITE(DP_A, dpa_ctl);
1231 POSTING_READ(DP_A);
1232 udelay(200);
1233 }
1234
ironlake_edp_pll_off(struct drm_encoder * encoder)1235 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1236 {
1237 struct drm_device *dev = encoder->dev;
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239 u32 dpa_ctl;
1240
1241 dpa_ctl = I915_READ(DP_A);
1242 dpa_ctl &= ~DP_PLL_ENABLE;
1243 I915_WRITE(DP_A, dpa_ctl);
1244 POSTING_READ(DP_A);
1245 udelay(200);
1246 }
1247
1248 /* If the sink supports it, try to set the power state appropriately */
intel_dp_sink_dpms(struct intel_dp * intel_dp,int mode)1249 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1250 {
1251 int ret, i;
1252
1253 /* Should have a valid DPCD by this point */
1254 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1255 return;
1256
1257 if (mode != DRM_MODE_DPMS_ON) {
1258 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1259 DP_SET_POWER_D3);
1260 if (ret != 1)
1261 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1262 } else {
1263 /*
1264 * When turning on, we need to retry for 1ms to give the sink
1265 * time to wake up.
1266 */
1267 for (i = 0; i < 3; i++) {
1268 ret = intel_dp_aux_native_write_1(intel_dp,
1269 DP_SET_POWER,
1270 DP_SET_POWER_D0);
1271 if (ret == 1)
1272 break;
1273 msleep(1);
1274 }
1275 }
1276 }
1277
intel_dp_prepare(struct drm_encoder * encoder)1278 static void intel_dp_prepare(struct drm_encoder *encoder)
1279 {
1280 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1281
1282
1283 /* Make sure the panel is off before trying to change the mode. But also
1284 * ensure that we have vdd while we switch off the panel. */
1285 ironlake_edp_panel_vdd_on(intel_dp);
1286 ironlake_edp_backlight_off(intel_dp);
1287 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1288 ironlake_edp_panel_off(intel_dp);
1289 intel_dp_link_down(intel_dp);
1290 }
1291
intel_dp_commit(struct drm_encoder * encoder)1292 static void intel_dp_commit(struct drm_encoder *encoder)
1293 {
1294 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1295 struct drm_device *dev = encoder->dev;
1296 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1297
1298 ironlake_edp_panel_vdd_on(intel_dp);
1299 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1300 intel_dp_start_link_train(intel_dp);
1301 ironlake_edp_panel_on(intel_dp);
1302 ironlake_edp_panel_vdd_off(intel_dp, true);
1303 intel_dp_complete_link_train(intel_dp);
1304 ironlake_edp_backlight_on(intel_dp);
1305
1306 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1307
1308 if (HAS_PCH_CPT(dev))
1309 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1310 }
1311
1312 static void
intel_dp_dpms(struct drm_encoder * encoder,int mode)1313 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1314 {
1315 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1316 struct drm_device *dev = encoder->dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1319
1320 if (mode != DRM_MODE_DPMS_ON) {
1321 /* Switching the panel off requires vdd. */
1322 ironlake_edp_panel_vdd_on(intel_dp);
1323 ironlake_edp_backlight_off(intel_dp);
1324 intel_dp_sink_dpms(intel_dp, mode);
1325 ironlake_edp_panel_off(intel_dp);
1326 intel_dp_link_down(intel_dp);
1327
1328 if (is_cpu_edp(intel_dp))
1329 ironlake_edp_pll_off(encoder);
1330 } else {
1331 if (is_cpu_edp(intel_dp))
1332 ironlake_edp_pll_on(encoder);
1333
1334 ironlake_edp_panel_vdd_on(intel_dp);
1335 intel_dp_sink_dpms(intel_dp, mode);
1336 if (!(dp_reg & DP_PORT_EN)) {
1337 intel_dp_start_link_train(intel_dp);
1338 ironlake_edp_panel_on(intel_dp);
1339 ironlake_edp_panel_vdd_off(intel_dp, true);
1340 intel_dp_complete_link_train(intel_dp);
1341 } else
1342 ironlake_edp_panel_vdd_off(intel_dp, false);
1343 ironlake_edp_backlight_on(intel_dp);
1344 }
1345 intel_dp->dpms_mode = mode;
1346 }
1347
1348 /*
1349 * Native read with retry for link status and receiver capability reads for
1350 * cases where the sink may still be asleep.
1351 */
1352 static bool
intel_dp_aux_native_read_retry(struct intel_dp * intel_dp,uint16_t address,uint8_t * recv,int recv_bytes)1353 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1354 uint8_t *recv, int recv_bytes)
1355 {
1356 int ret, i;
1357
1358 /*
1359 * Sinks are *supposed* to come up within 1ms from an off state,
1360 * but we're also supposed to retry 3 times per the spec.
1361 */
1362 for (i = 0; i < 3; i++) {
1363 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1364 recv_bytes);
1365 if (ret == recv_bytes)
1366 return true;
1367 msleep(1);
1368 }
1369
1370 return false;
1371 }
1372
1373 /*
1374 * Fetch AUX CH registers 0x202 - 0x207 which contain
1375 * link status information
1376 */
1377 static bool
intel_dp_get_link_status(struct intel_dp * intel_dp,uint8_t link_status[DP_LINK_STATUS_SIZE])1378 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1379 {
1380 return intel_dp_aux_native_read_retry(intel_dp,
1381 DP_LANE0_1_STATUS,
1382 link_status,
1383 DP_LINK_STATUS_SIZE);
1384 }
1385
1386 static uint8_t
intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],int r)1387 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1388 int r)
1389 {
1390 return link_status[r - DP_LANE0_1_STATUS];
1391 }
1392
1393 static uint8_t
intel_get_adjust_request_voltage(uint8_t adjust_request[2],int lane)1394 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1395 int lane)
1396 {
1397 int s = ((lane & 1) ?
1398 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1399 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1400 uint8_t l = adjust_request[lane>>1];
1401
1402 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1403 }
1404
1405 static uint8_t
intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],int lane)1406 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1407 int lane)
1408 {
1409 int s = ((lane & 1) ?
1410 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1411 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1412 uint8_t l = adjust_request[lane>>1];
1413
1414 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1415 }
1416
1417
1418 #if 0
1419 static char *voltage_names[] = {
1420 "0.4V", "0.6V", "0.8V", "1.2V"
1421 };
1422 static char *pre_emph_names[] = {
1423 "0dB", "3.5dB", "6dB", "9.5dB"
1424 };
1425 static char *link_train_names[] = {
1426 "pattern 1", "pattern 2", "idle", "off"
1427 };
1428 #endif
1429
1430 /*
1431 * These are source-specific values; current Intel hardware supports
1432 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1433 */
1434
1435 static uint8_t
intel_dp_voltage_max(struct intel_dp * intel_dp)1436 intel_dp_voltage_max(struct intel_dp *intel_dp)
1437 {
1438 struct drm_device *dev = intel_dp->base.base.dev;
1439
1440 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1441 return DP_TRAIN_VOLTAGE_SWING_800;
1442 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1443 return DP_TRAIN_VOLTAGE_SWING_1200;
1444 else
1445 return DP_TRAIN_VOLTAGE_SWING_800;
1446 }
1447
1448 static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp * intel_dp,uint8_t voltage_swing)1449 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1450 {
1451 struct drm_device *dev = intel_dp->base.base.dev;
1452
1453 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1454 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1455 case DP_TRAIN_VOLTAGE_SWING_400:
1456 return DP_TRAIN_PRE_EMPHASIS_6;
1457 case DP_TRAIN_VOLTAGE_SWING_600:
1458 case DP_TRAIN_VOLTAGE_SWING_800:
1459 return DP_TRAIN_PRE_EMPHASIS_3_5;
1460 default:
1461 return DP_TRAIN_PRE_EMPHASIS_0;
1462 }
1463 } else {
1464 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1465 case DP_TRAIN_VOLTAGE_SWING_400:
1466 return DP_TRAIN_PRE_EMPHASIS_6;
1467 case DP_TRAIN_VOLTAGE_SWING_600:
1468 return DP_TRAIN_PRE_EMPHASIS_6;
1469 case DP_TRAIN_VOLTAGE_SWING_800:
1470 return DP_TRAIN_PRE_EMPHASIS_3_5;
1471 case DP_TRAIN_VOLTAGE_SWING_1200:
1472 default:
1473 return DP_TRAIN_PRE_EMPHASIS_0;
1474 }
1475 }
1476 }
1477
1478 static void
intel_get_adjust_train(struct intel_dp * intel_dp,uint8_t link_status[DP_LINK_STATUS_SIZE])1479 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1480 {
1481 uint8_t v = 0;
1482 uint8_t p = 0;
1483 int lane;
1484 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1485 uint8_t voltage_max;
1486 uint8_t preemph_max;
1487
1488 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1489 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1490 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1491
1492 if (this_v > v)
1493 v = this_v;
1494 if (this_p > p)
1495 p = this_p;
1496 }
1497
1498 voltage_max = intel_dp_voltage_max(intel_dp);
1499 if (v >= voltage_max)
1500 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1501
1502 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1503 if (p >= preemph_max)
1504 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1505
1506 for (lane = 0; lane < 4; lane++)
1507 intel_dp->train_set[lane] = v | p;
1508 }
1509
1510 static uint32_t
intel_dp_signal_levels(uint8_t train_set)1511 intel_dp_signal_levels(uint8_t train_set)
1512 {
1513 uint32_t signal_levels = 0;
1514
1515 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1516 case DP_TRAIN_VOLTAGE_SWING_400:
1517 default:
1518 signal_levels |= DP_VOLTAGE_0_4;
1519 break;
1520 case DP_TRAIN_VOLTAGE_SWING_600:
1521 signal_levels |= DP_VOLTAGE_0_6;
1522 break;
1523 case DP_TRAIN_VOLTAGE_SWING_800:
1524 signal_levels |= DP_VOLTAGE_0_8;
1525 break;
1526 case DP_TRAIN_VOLTAGE_SWING_1200:
1527 signal_levels |= DP_VOLTAGE_1_2;
1528 break;
1529 }
1530 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1531 case DP_TRAIN_PRE_EMPHASIS_0:
1532 default:
1533 signal_levels |= DP_PRE_EMPHASIS_0;
1534 break;
1535 case DP_TRAIN_PRE_EMPHASIS_3_5:
1536 signal_levels |= DP_PRE_EMPHASIS_3_5;
1537 break;
1538 case DP_TRAIN_PRE_EMPHASIS_6:
1539 signal_levels |= DP_PRE_EMPHASIS_6;
1540 break;
1541 case DP_TRAIN_PRE_EMPHASIS_9_5:
1542 signal_levels |= DP_PRE_EMPHASIS_9_5;
1543 break;
1544 }
1545 return signal_levels;
1546 }
1547
1548 /* Gen6's DP voltage swing and pre-emphasis control */
1549 static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)1550 intel_gen6_edp_signal_levels(uint8_t train_set)
1551 {
1552 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1553 DP_TRAIN_PRE_EMPHASIS_MASK);
1554 switch (signal_levels) {
1555 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1556 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1557 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1558 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1559 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1560 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1561 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1562 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1563 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1564 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1565 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1566 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1567 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1568 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1569 default:
1570 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1571 "0x%x\n", signal_levels);
1572 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1573 }
1574 }
1575
1576 /* Gen7's DP voltage swing and pre-emphasis control */
1577 static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)1578 intel_gen7_edp_signal_levels(uint8_t train_set)
1579 {
1580 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1581 DP_TRAIN_PRE_EMPHASIS_MASK);
1582 switch (signal_levels) {
1583 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1584 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1585 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1586 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1587 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1588 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1589
1590 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1591 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1592 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1593 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1594
1595 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1596 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1597 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1598 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1599
1600 default:
1601 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1602 "0x%x\n", signal_levels);
1603 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1604 }
1605 }
1606
1607 static uint8_t
intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],int lane)1608 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1609 int lane)
1610 {
1611 int s = (lane & 1) * 4;
1612 uint8_t l = link_status[lane>>1];
1613
1614 return (l >> s) & 0xf;
1615 }
1616
1617 /* Check for clock recovery is done on all channels */
1618 static bool
intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE],int lane_count)1619 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1620 {
1621 int lane;
1622 uint8_t lane_status;
1623
1624 for (lane = 0; lane < lane_count; lane++) {
1625 lane_status = intel_get_lane_status(link_status, lane);
1626 if ((lane_status & DP_LANE_CR_DONE) == 0)
1627 return false;
1628 }
1629 return true;
1630 }
1631
1632 /* Check to see if channel eq is done on all channels */
1633 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1634 DP_LANE_CHANNEL_EQ_DONE|\
1635 DP_LANE_SYMBOL_LOCKED)
1636 static bool
intel_channel_eq_ok(struct intel_dp * intel_dp,uint8_t link_status[DP_LINK_STATUS_SIZE])1637 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1638 {
1639 uint8_t lane_align;
1640 uint8_t lane_status;
1641 int lane;
1642
1643 lane_align = intel_dp_link_status(link_status,
1644 DP_LANE_ALIGN_STATUS_UPDATED);
1645 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1646 return false;
1647 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1648 lane_status = intel_get_lane_status(link_status, lane);
1649 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1650 return false;
1651 }
1652 return true;
1653 }
1654
1655 static bool
intel_dp_set_link_train(struct intel_dp * intel_dp,uint32_t dp_reg_value,uint8_t dp_train_pat)1656 intel_dp_set_link_train(struct intel_dp *intel_dp,
1657 uint32_t dp_reg_value,
1658 uint8_t dp_train_pat)
1659 {
1660 struct drm_device *dev = intel_dp->base.base.dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 int ret;
1663
1664 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1665 POSTING_READ(intel_dp->output_reg);
1666
1667 intel_dp_aux_native_write_1(intel_dp,
1668 DP_TRAINING_PATTERN_SET,
1669 dp_train_pat);
1670
1671 ret = intel_dp_aux_native_write(intel_dp,
1672 DP_TRAINING_LANE0_SET,
1673 intel_dp->train_set,
1674 intel_dp->lane_count);
1675 if (ret != intel_dp->lane_count)
1676 return false;
1677
1678 return true;
1679 }
1680
1681 /* Enable corresponding port and start training pattern 1 */
1682 static void
intel_dp_start_link_train(struct intel_dp * intel_dp)1683 intel_dp_start_link_train(struct intel_dp *intel_dp)
1684 {
1685 struct drm_device *dev = intel_dp->base.base.dev;
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1688 int i;
1689 uint8_t voltage;
1690 bool clock_recovery = false;
1691 int voltage_tries, loop_tries;
1692 u32 reg;
1693 uint32_t DP = intel_dp->DP;
1694
1695 /*
1696 * On CPT we have to enable the port in training pattern 1, which
1697 * will happen below in intel_dp_set_link_train. Otherwise, enable
1698 * the port and wait for it to become active.
1699 */
1700 if (!HAS_PCH_CPT(dev)) {
1701 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1702 POSTING_READ(intel_dp->output_reg);
1703 intel_wait_for_vblank(dev, intel_crtc->pipe);
1704 }
1705
1706 /* Write the link configuration data */
1707 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1708 intel_dp->link_configuration,
1709 DP_LINK_CONFIGURATION_SIZE);
1710
1711 DP |= DP_PORT_EN;
1712
1713 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1714 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1715 else
1716 DP &= ~DP_LINK_TRAIN_MASK;
1717 memset(intel_dp->train_set, 0, 4);
1718 voltage = 0xff;
1719 voltage_tries = 0;
1720 loop_tries = 0;
1721 clock_recovery = false;
1722 for (;;) {
1723 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1724 uint8_t link_status[DP_LINK_STATUS_SIZE];
1725 uint32_t signal_levels;
1726
1727
1728 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1729 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1730 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1731 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1732 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1733 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1734 } else {
1735 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1736 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1737 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1738 }
1739
1740 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1741 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1742 else
1743 reg = DP | DP_LINK_TRAIN_PAT_1;
1744
1745 if (!intel_dp_set_link_train(intel_dp, reg,
1746 DP_TRAINING_PATTERN_1 |
1747 DP_LINK_SCRAMBLING_DISABLE))
1748 break;
1749 /* Set training pattern 1 */
1750
1751 udelay(100);
1752 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1753 DRM_ERROR("failed to get link status\n");
1754 break;
1755 }
1756
1757 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1758 DRM_DEBUG_KMS("clock recovery OK\n");
1759 clock_recovery = true;
1760 break;
1761 }
1762
1763 /* Check to see if we've tried the max voltage */
1764 for (i = 0; i < intel_dp->lane_count; i++)
1765 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1766 break;
1767 if (i == intel_dp->lane_count) {
1768 ++loop_tries;
1769 if (loop_tries == 5) {
1770 DRM_DEBUG_KMS("too many full retries, give up\n");
1771 break;
1772 }
1773 memset(intel_dp->train_set, 0, 4);
1774 voltage_tries = 0;
1775 continue;
1776 }
1777
1778 /* Check to see if we've tried the same voltage 5 times */
1779 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1780 ++voltage_tries;
1781 if (voltage_tries == 5) {
1782 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1783 break;
1784 }
1785 } else
1786 voltage_tries = 0;
1787 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1788
1789 /* Compute new intel_dp->train_set as requested by target */
1790 intel_get_adjust_train(intel_dp, link_status);
1791 }
1792
1793 intel_dp->DP = DP;
1794 }
1795
1796 static void
intel_dp_complete_link_train(struct intel_dp * intel_dp)1797 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1798 {
1799 struct drm_device *dev = intel_dp->base.base.dev;
1800 struct drm_i915_private *dev_priv = dev->dev_private;
1801 bool channel_eq = false;
1802 int tries, cr_tries;
1803 u32 reg;
1804 uint32_t DP = intel_dp->DP;
1805
1806 /* channel equalization */
1807 tries = 0;
1808 cr_tries = 0;
1809 channel_eq = false;
1810 for (;;) {
1811 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1812 uint32_t signal_levels;
1813 uint8_t link_status[DP_LINK_STATUS_SIZE];
1814
1815 if (cr_tries > 5) {
1816 DRM_ERROR("failed to train DP, aborting\n");
1817 intel_dp_link_down(intel_dp);
1818 break;
1819 }
1820
1821 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1822 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1823 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1824 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1825 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1826 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1827 } else {
1828 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1829 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1830 }
1831
1832 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1833 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1834 else
1835 reg = DP | DP_LINK_TRAIN_PAT_2;
1836
1837 /* channel eq pattern */
1838 if (!intel_dp_set_link_train(intel_dp, reg,
1839 DP_TRAINING_PATTERN_2 |
1840 DP_LINK_SCRAMBLING_DISABLE))
1841 break;
1842
1843 udelay(400);
1844 if (!intel_dp_get_link_status(intel_dp, link_status))
1845 break;
1846
1847 /* Make sure clock is still ok */
1848 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1849 intel_dp_start_link_train(intel_dp);
1850 cr_tries++;
1851 continue;
1852 }
1853
1854 if (intel_channel_eq_ok(intel_dp, link_status)) {
1855 channel_eq = true;
1856 break;
1857 }
1858
1859 /* Try 5 times, then try clock recovery if that fails */
1860 if (tries > 5) {
1861 intel_dp_link_down(intel_dp);
1862 intel_dp_start_link_train(intel_dp);
1863 tries = 0;
1864 cr_tries++;
1865 continue;
1866 }
1867
1868 /* Compute new intel_dp->train_set as requested by target */
1869 intel_get_adjust_train(intel_dp, link_status);
1870 ++tries;
1871 }
1872
1873 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1874 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1875 else
1876 reg = DP | DP_LINK_TRAIN_OFF;
1877
1878 I915_WRITE(intel_dp->output_reg, reg);
1879 POSTING_READ(intel_dp->output_reg);
1880 intel_dp_aux_native_write_1(intel_dp,
1881 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1882 }
1883
1884 static void
intel_dp_link_down(struct intel_dp * intel_dp)1885 intel_dp_link_down(struct intel_dp *intel_dp)
1886 {
1887 struct drm_device *dev = intel_dp->base.base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 uint32_t DP = intel_dp->DP;
1890
1891 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1892 return;
1893
1894 DRM_DEBUG_KMS("\n");
1895
1896 if (is_edp(intel_dp)) {
1897 DP &= ~DP_PLL_ENABLE;
1898 I915_WRITE(intel_dp->output_reg, DP);
1899 POSTING_READ(intel_dp->output_reg);
1900 udelay(100);
1901 }
1902
1903 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1904 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1905 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1906 } else {
1907 DP &= ~DP_LINK_TRAIN_MASK;
1908 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1909 }
1910 POSTING_READ(intel_dp->output_reg);
1911
1912 msleep(17);
1913
1914 if (is_edp(intel_dp)) {
1915 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1916 DP |= DP_LINK_TRAIN_OFF_CPT;
1917 else
1918 DP |= DP_LINK_TRAIN_OFF;
1919 }
1920
1921 if (!HAS_PCH_CPT(dev) &&
1922 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1923 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1924
1925 /* Hardware workaround: leaving our transcoder select
1926 * set to transcoder B while it's off will prevent the
1927 * corresponding HDMI output on transcoder A.
1928 *
1929 * Combine this with another hardware workaround:
1930 * transcoder select bit can only be cleared while the
1931 * port is enabled.
1932 */
1933 DP &= ~DP_PIPEB_SELECT;
1934 I915_WRITE(intel_dp->output_reg, DP);
1935
1936 /* Changes to enable or select take place the vblank
1937 * after being written.
1938 */
1939 if (crtc == NULL) {
1940 /* We can arrive here never having been attached
1941 * to a CRTC, for instance, due to inheriting
1942 * random state from the BIOS.
1943 *
1944 * If the pipe is not running, play safe and
1945 * wait for the clocks to stabilise before
1946 * continuing.
1947 */
1948 POSTING_READ(intel_dp->output_reg);
1949 msleep(50);
1950 } else
1951 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1952 }
1953
1954 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1955 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1956 POSTING_READ(intel_dp->output_reg);
1957 msleep(intel_dp->panel_power_down_delay);
1958 }
1959
1960 static bool
intel_dp_get_dpcd(struct intel_dp * intel_dp)1961 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1962 {
1963 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1964 sizeof(intel_dp->dpcd)) &&
1965 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1966 return true;
1967 }
1968
1969 return false;
1970 }
1971
1972 static bool
intel_dp_get_sink_irq(struct intel_dp * intel_dp,u8 * sink_irq_vector)1973 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1974 {
1975 int ret;
1976
1977 ret = intel_dp_aux_native_read_retry(intel_dp,
1978 DP_DEVICE_SERVICE_IRQ_VECTOR,
1979 sink_irq_vector, 1);
1980 if (!ret)
1981 return false;
1982
1983 return true;
1984 }
1985
1986 static void
intel_dp_handle_test_request(struct intel_dp * intel_dp)1987 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1988 {
1989 /* NAK by default */
1990 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1991 }
1992
1993 /*
1994 * According to DP spec
1995 * 5.1.2:
1996 * 1. Read DPCD
1997 * 2. Configure link according to Receiver Capabilities
1998 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1999 * 4. Check link status on receipt of hot-plug interrupt
2000 */
2001
2002 static void
intel_dp_check_link_status(struct intel_dp * intel_dp)2003 intel_dp_check_link_status(struct intel_dp *intel_dp)
2004 {
2005 u8 sink_irq_vector;
2006 u8 link_status[DP_LINK_STATUS_SIZE];
2007
2008 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2009 return;
2010
2011 if (!intel_dp->base.base.crtc)
2012 return;
2013
2014 /* Try to read receiver status if the link appears to be up */
2015 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2016 intel_dp_link_down(intel_dp);
2017 return;
2018 }
2019
2020 /* Now read the DPCD to see if it's actually running */
2021 if (!intel_dp_get_dpcd(intel_dp)) {
2022 intel_dp_link_down(intel_dp);
2023 return;
2024 }
2025
2026 /* Try to read the source of the interrupt */
2027 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2028 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2029 /* Clear interrupt source */
2030 intel_dp_aux_native_write_1(intel_dp,
2031 DP_DEVICE_SERVICE_IRQ_VECTOR,
2032 sink_irq_vector);
2033
2034 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2035 intel_dp_handle_test_request(intel_dp);
2036 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2037 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2038 }
2039
2040 if (!intel_channel_eq_ok(intel_dp, link_status)) {
2041 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2042 drm_get_encoder_name(&intel_dp->base.base));
2043 intel_dp_start_link_train(intel_dp);
2044 intel_dp_complete_link_train(intel_dp);
2045 }
2046 }
2047
2048 static enum drm_connector_status
intel_dp_detect_dpcd(struct intel_dp * intel_dp)2049 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2050 {
2051 if (intel_dp_get_dpcd(intel_dp))
2052 return connector_status_connected;
2053 return connector_status_disconnected;
2054 }
2055
2056 static enum drm_connector_status
ironlake_dp_detect(struct intel_dp * intel_dp)2057 ironlake_dp_detect(struct intel_dp *intel_dp)
2058 {
2059 enum drm_connector_status status;
2060
2061 /* Can't disconnect eDP, but you can close the lid... */
2062 if (is_edp(intel_dp)) {
2063 status = intel_panel_detect(intel_dp->base.base.dev);
2064 if (status == connector_status_unknown)
2065 status = connector_status_connected;
2066 return status;
2067 }
2068
2069 return intel_dp_detect_dpcd(intel_dp);
2070 }
2071
2072 static enum drm_connector_status
g4x_dp_detect(struct intel_dp * intel_dp)2073 g4x_dp_detect(struct intel_dp *intel_dp)
2074 {
2075 struct drm_device *dev = intel_dp->base.base.dev;
2076 struct drm_i915_private *dev_priv = dev->dev_private;
2077 uint32_t temp, bit;
2078
2079 switch (intel_dp->output_reg) {
2080 case DP_B:
2081 bit = DPB_HOTPLUG_INT_STATUS;
2082 break;
2083 case DP_C:
2084 bit = DPC_HOTPLUG_INT_STATUS;
2085 break;
2086 case DP_D:
2087 bit = DPD_HOTPLUG_INT_STATUS;
2088 break;
2089 default:
2090 return connector_status_unknown;
2091 }
2092
2093 temp = I915_READ(PORT_HOTPLUG_STAT);
2094
2095 if ((temp & bit) == 0)
2096 return connector_status_disconnected;
2097
2098 return intel_dp_detect_dpcd(intel_dp);
2099 }
2100
2101 static struct edid *
intel_dp_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)2102 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2103 {
2104 struct intel_dp *intel_dp = intel_attached_dp(connector);
2105 struct edid *edid;
2106
2107 ironlake_edp_panel_vdd_on(intel_dp);
2108 edid = drm_get_edid(connector, adapter);
2109 ironlake_edp_panel_vdd_off(intel_dp, false);
2110 return edid;
2111 }
2112
2113 static int
intel_dp_get_edid_modes(struct drm_connector * connector,struct i2c_adapter * adapter)2114 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2115 {
2116 struct intel_dp *intel_dp = intel_attached_dp(connector);
2117 int ret;
2118
2119 ironlake_edp_panel_vdd_on(intel_dp);
2120 ret = intel_ddc_get_modes(connector, adapter);
2121 ironlake_edp_panel_vdd_off(intel_dp, false);
2122 return ret;
2123 }
2124
2125
2126 /**
2127 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2128 *
2129 * \return true if DP port is connected.
2130 * \return false if DP port is disconnected.
2131 */
2132 static enum drm_connector_status
intel_dp_detect(struct drm_connector * connector,bool force)2133 intel_dp_detect(struct drm_connector *connector, bool force)
2134 {
2135 struct intel_dp *intel_dp = intel_attached_dp(connector);
2136 struct drm_device *dev = intel_dp->base.base.dev;
2137 enum drm_connector_status status;
2138 struct edid *edid = NULL;
2139
2140 intel_dp->has_audio = false;
2141
2142 if (HAS_PCH_SPLIT(dev))
2143 status = ironlake_dp_detect(intel_dp);
2144 else
2145 status = g4x_dp_detect(intel_dp);
2146
2147 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2148 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2149 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2150 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2151
2152 if (status != connector_status_connected)
2153 return status;
2154
2155 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2156 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2157 } else {
2158 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2159 if (edid) {
2160 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2161 connector->display_info.raw_edid = NULL;
2162 kfree(edid);
2163 }
2164 }
2165
2166 return connector_status_connected;
2167 }
2168
intel_dp_get_modes(struct drm_connector * connector)2169 static int intel_dp_get_modes(struct drm_connector *connector)
2170 {
2171 struct intel_dp *intel_dp = intel_attached_dp(connector);
2172 struct drm_device *dev = intel_dp->base.base.dev;
2173 struct drm_i915_private *dev_priv = dev->dev_private;
2174 int ret;
2175
2176 /* We should parse the EDID data and find out if it has an audio sink
2177 */
2178
2179 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2180 if (ret) {
2181 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2182 struct drm_display_mode *newmode;
2183 list_for_each_entry(newmode, &connector->probed_modes,
2184 head) {
2185 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2186 intel_dp->panel_fixed_mode =
2187 drm_mode_duplicate(dev, newmode);
2188 break;
2189 }
2190 }
2191 }
2192 return ret;
2193 }
2194
2195 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2196 if (is_edp(intel_dp)) {
2197 /* initialize panel mode from VBT if available for eDP */
2198 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2199 intel_dp->panel_fixed_mode =
2200 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2201 if (intel_dp->panel_fixed_mode) {
2202 intel_dp->panel_fixed_mode->type |=
2203 DRM_MODE_TYPE_PREFERRED;
2204 }
2205 }
2206 if (intel_dp->panel_fixed_mode) {
2207 struct drm_display_mode *mode;
2208 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2209 drm_mode_probed_add(connector, mode);
2210 return 1;
2211 }
2212 }
2213 return 0;
2214 }
2215
2216 static bool
intel_dp_detect_audio(struct drm_connector * connector)2217 intel_dp_detect_audio(struct drm_connector *connector)
2218 {
2219 struct intel_dp *intel_dp = intel_attached_dp(connector);
2220 struct edid *edid;
2221 bool has_audio = false;
2222
2223 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2224 if (edid) {
2225 has_audio = drm_detect_monitor_audio(edid);
2226
2227 connector->display_info.raw_edid = NULL;
2228 kfree(edid);
2229 }
2230
2231 return has_audio;
2232 }
2233
2234 static int
intel_dp_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)2235 intel_dp_set_property(struct drm_connector *connector,
2236 struct drm_property *property,
2237 uint64_t val)
2238 {
2239 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2240 struct intel_dp *intel_dp = intel_attached_dp(connector);
2241 int ret;
2242
2243 ret = drm_connector_property_set_value(connector, property, val);
2244 if (ret)
2245 return ret;
2246
2247 if (property == dev_priv->force_audio_property) {
2248 int i = val;
2249 bool has_audio;
2250
2251 if (i == intel_dp->force_audio)
2252 return 0;
2253
2254 intel_dp->force_audio = i;
2255
2256 if (i == HDMI_AUDIO_AUTO)
2257 has_audio = intel_dp_detect_audio(connector);
2258 else
2259 has_audio = (i == HDMI_AUDIO_ON);
2260
2261 if (has_audio == intel_dp->has_audio)
2262 return 0;
2263
2264 intel_dp->has_audio = has_audio;
2265 goto done;
2266 }
2267
2268 if (property == dev_priv->broadcast_rgb_property) {
2269 if (val == !!intel_dp->color_range)
2270 return 0;
2271
2272 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2273 goto done;
2274 }
2275
2276 return -EINVAL;
2277
2278 done:
2279 if (intel_dp->base.base.crtc) {
2280 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2281 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2282 crtc->x, crtc->y,
2283 crtc->fb);
2284 }
2285
2286 return 0;
2287 }
2288
2289 static void
intel_dp_destroy(struct drm_connector * connector)2290 intel_dp_destroy(struct drm_connector *connector)
2291 {
2292 struct drm_device *dev = connector->dev;
2293
2294 if (intel_dpd_is_edp(dev))
2295 intel_panel_destroy_backlight(dev);
2296
2297 drm_sysfs_connector_remove(connector);
2298 drm_connector_cleanup(connector);
2299 kfree(connector);
2300 }
2301
intel_dp_encoder_destroy(struct drm_encoder * encoder)2302 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2303 {
2304 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2305
2306 i2c_del_adapter(&intel_dp->adapter);
2307 drm_encoder_cleanup(encoder);
2308 if (is_edp(intel_dp)) {
2309 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2310 ironlake_panel_vdd_off_sync(intel_dp);
2311 }
2312 kfree(intel_dp);
2313 }
2314
2315 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2316 .dpms = intel_dp_dpms,
2317 .mode_fixup = intel_dp_mode_fixup,
2318 .prepare = intel_dp_prepare,
2319 .mode_set = intel_dp_mode_set,
2320 .commit = intel_dp_commit,
2321 };
2322
2323 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2324 .dpms = drm_helper_connector_dpms,
2325 .detect = intel_dp_detect,
2326 .fill_modes = drm_helper_probe_single_connector_modes,
2327 .set_property = intel_dp_set_property,
2328 .destroy = intel_dp_destroy,
2329 };
2330
2331 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2332 .get_modes = intel_dp_get_modes,
2333 .mode_valid = intel_dp_mode_valid,
2334 .best_encoder = intel_best_encoder,
2335 };
2336
2337 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2338 .destroy = intel_dp_encoder_destroy,
2339 };
2340
2341 static void
intel_dp_hot_plug(struct intel_encoder * intel_encoder)2342 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2343 {
2344 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2345
2346 intel_dp_check_link_status(intel_dp);
2347 }
2348
2349 /* Return which DP Port should be selected for Transcoder DP control */
2350 int
intel_trans_dp_port_sel(struct drm_crtc * crtc)2351 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2352 {
2353 struct drm_device *dev = crtc->dev;
2354 struct drm_mode_config *mode_config = &dev->mode_config;
2355 struct drm_encoder *encoder;
2356
2357 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2358 struct intel_dp *intel_dp;
2359
2360 if (encoder->crtc != crtc)
2361 continue;
2362
2363 intel_dp = enc_to_intel_dp(encoder);
2364 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2365 intel_dp->base.type == INTEL_OUTPUT_EDP)
2366 return intel_dp->output_reg;
2367 }
2368
2369 return -1;
2370 }
2371
2372 /* check the VBT to see whether the eDP is on DP-D port */
intel_dpd_is_edp(struct drm_device * dev)2373 bool intel_dpd_is_edp(struct drm_device *dev)
2374 {
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 struct child_device_config *p_child;
2377 int i;
2378
2379 if (!dev_priv->child_dev_num)
2380 return false;
2381
2382 for (i = 0; i < dev_priv->child_dev_num; i++) {
2383 p_child = dev_priv->child_dev + i;
2384
2385 if (p_child->dvo_port == PORT_IDPD &&
2386 p_child->device_type == DEVICE_TYPE_eDP)
2387 return true;
2388 }
2389 return false;
2390 }
2391
2392 static void
intel_dp_add_properties(struct intel_dp * intel_dp,struct drm_connector * connector)2393 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2394 {
2395 intel_attach_force_audio_property(connector);
2396 intel_attach_broadcast_rgb_property(connector);
2397 }
2398
2399 void
intel_dp_init(struct drm_device * dev,int output_reg)2400 intel_dp_init(struct drm_device *dev, int output_reg)
2401 {
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 struct drm_connector *connector;
2404 struct intel_dp *intel_dp;
2405 struct intel_encoder *intel_encoder;
2406 struct intel_connector *intel_connector;
2407 const char *name = NULL;
2408 int type;
2409
2410 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2411 if (!intel_dp)
2412 return;
2413
2414 intel_dp->output_reg = output_reg;
2415 intel_dp->dpms_mode = -1;
2416
2417 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2418 if (!intel_connector) {
2419 kfree(intel_dp);
2420 return;
2421 }
2422 intel_encoder = &intel_dp->base;
2423
2424 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2425 if (intel_dpd_is_edp(dev))
2426 intel_dp->is_pch_edp = true;
2427
2428 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2429 type = DRM_MODE_CONNECTOR_eDP;
2430 intel_encoder->type = INTEL_OUTPUT_EDP;
2431 } else {
2432 type = DRM_MODE_CONNECTOR_DisplayPort;
2433 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2434 }
2435
2436 connector = &intel_connector->base;
2437 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2438 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2439
2440 connector->polled = DRM_CONNECTOR_POLL_HPD;
2441
2442 if (output_reg == DP_B || output_reg == PCH_DP_B)
2443 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2444 else if (output_reg == DP_C || output_reg == PCH_DP_C)
2445 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2446 else if (output_reg == DP_D || output_reg == PCH_DP_D)
2447 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2448
2449 if (is_edp(intel_dp)) {
2450 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2451 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2452 ironlake_panel_vdd_work);
2453 }
2454
2455 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2456 connector->interlace_allowed = true;
2457 connector->doublescan_allowed = 0;
2458
2459 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2460 DRM_MODE_ENCODER_TMDS);
2461 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2462
2463 intel_connector_attach_encoder(intel_connector, intel_encoder);
2464 drm_sysfs_connector_add(connector);
2465
2466 /* Set up the DDC bus. */
2467 switch (output_reg) {
2468 case DP_A:
2469 name = "DPDDC-A";
2470 break;
2471 case DP_B:
2472 case PCH_DP_B:
2473 dev_priv->hotplug_supported_mask |=
2474 HDMIB_HOTPLUG_INT_STATUS;
2475 name = "DPDDC-B";
2476 break;
2477 case DP_C:
2478 case PCH_DP_C:
2479 dev_priv->hotplug_supported_mask |=
2480 HDMIC_HOTPLUG_INT_STATUS;
2481 name = "DPDDC-C";
2482 break;
2483 case DP_D:
2484 case PCH_DP_D:
2485 dev_priv->hotplug_supported_mask |=
2486 HDMID_HOTPLUG_INT_STATUS;
2487 name = "DPDDC-D";
2488 break;
2489 }
2490
2491 /* Cache some DPCD data in the eDP case */
2492 if (is_edp(intel_dp)) {
2493 bool ret;
2494 struct edp_power_seq cur, vbt;
2495 u32 pp_on, pp_off, pp_div;
2496
2497 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2498 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2499 pp_div = I915_READ(PCH_PP_DIVISOR);
2500
2501 /* Pull timing values out of registers */
2502 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2503 PANEL_POWER_UP_DELAY_SHIFT;
2504
2505 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2506 PANEL_LIGHT_ON_DELAY_SHIFT;
2507
2508 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2509 PANEL_LIGHT_OFF_DELAY_SHIFT;
2510
2511 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2512 PANEL_POWER_DOWN_DELAY_SHIFT;
2513
2514 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2515 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2516
2517 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2518 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2519
2520 vbt = dev_priv->edp.pps;
2521
2522 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2523 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2524
2525 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2526
2527 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2528 intel_dp->backlight_on_delay = get_delay(t8);
2529 intel_dp->backlight_off_delay = get_delay(t9);
2530 intel_dp->panel_power_down_delay = get_delay(t10);
2531 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2532
2533 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2534 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2535 intel_dp->panel_power_cycle_delay);
2536
2537 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2538 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2539
2540 ironlake_edp_panel_vdd_on(intel_dp);
2541 ret = intel_dp_get_dpcd(intel_dp);
2542 ironlake_edp_panel_vdd_off(intel_dp, false);
2543
2544 if (ret) {
2545 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2546 dev_priv->no_aux_handshake =
2547 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2548 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2549 } else {
2550 /* if this fails, presume the device is a ghost */
2551 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2552 intel_dp_encoder_destroy(&intel_dp->base.base);
2553 intel_dp_destroy(&intel_connector->base);
2554 return;
2555 }
2556 }
2557
2558 intel_dp_i2c_init(intel_dp, intel_connector, name);
2559
2560 intel_encoder->hot_plug = intel_dp_hot_plug;
2561
2562 if (is_edp(intel_dp)) {
2563 dev_priv->int_edp_connector = connector;
2564 intel_panel_setup_backlight(dev);
2565 }
2566
2567 intel_dp_add_properties(intel_dp, connector);
2568
2569 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2570 * 0xd. Failure to do so will result in spurious interrupts being
2571 * generated on the port when a cable is not attached.
2572 */
2573 if (IS_G4X(dev) && !IS_GM45(dev)) {
2574 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2575 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2576 }
2577 }
2578