1 /*
2 * Isochronous I/O functionality:
3 * - Isochronous DMA context management
4 * - Isochronous bus resource management (channels, bandwidth), client side
5 *
6 * Copyright (C) 2006 Kristian Hoegsberg <krh@bitplanet.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23 #include <linux/dma-mapping.h>
24 #include <linux/errno.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/kernel.h>
28 #include <linux/mm.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/vmalloc.h>
32 #include <linux/export.h>
33
34 #include <asm/byteorder.h>
35
36 #include "core.h"
37
38 /*
39 * Isochronous DMA context management
40 */
41
fw_iso_buffer_init(struct fw_iso_buffer * buffer,struct fw_card * card,int page_count,enum dma_data_direction direction)42 int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card,
43 int page_count, enum dma_data_direction direction)
44 {
45 int i, j;
46 dma_addr_t address;
47
48 buffer->page_count = page_count;
49 buffer->direction = direction;
50
51 buffer->pages = kmalloc(page_count * sizeof(buffer->pages[0]),
52 GFP_KERNEL);
53 if (buffer->pages == NULL)
54 goto out;
55
56 for (i = 0; i < buffer->page_count; i++) {
57 buffer->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
58 if (buffer->pages[i] == NULL)
59 goto out_pages;
60
61 address = dma_map_page(card->device, buffer->pages[i],
62 0, PAGE_SIZE, direction);
63 if (dma_mapping_error(card->device, address)) {
64 __free_page(buffer->pages[i]);
65 goto out_pages;
66 }
67 set_page_private(buffer->pages[i], address);
68 }
69
70 return 0;
71
72 out_pages:
73 for (j = 0; j < i; j++) {
74 address = page_private(buffer->pages[j]);
75 dma_unmap_page(card->device, address,
76 PAGE_SIZE, direction);
77 __free_page(buffer->pages[j]);
78 }
79 kfree(buffer->pages);
80 out:
81 buffer->pages = NULL;
82
83 return -ENOMEM;
84 }
85 EXPORT_SYMBOL(fw_iso_buffer_init);
86
fw_iso_buffer_map(struct fw_iso_buffer * buffer,struct vm_area_struct * vma)87 int fw_iso_buffer_map(struct fw_iso_buffer *buffer, struct vm_area_struct *vma)
88 {
89 unsigned long uaddr;
90 int i, err;
91
92 uaddr = vma->vm_start;
93 for (i = 0; i < buffer->page_count; i++) {
94 err = vm_insert_page(vma, uaddr, buffer->pages[i]);
95 if (err)
96 return err;
97
98 uaddr += PAGE_SIZE;
99 }
100
101 return 0;
102 }
103
fw_iso_buffer_destroy(struct fw_iso_buffer * buffer,struct fw_card * card)104 void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer,
105 struct fw_card *card)
106 {
107 int i;
108 dma_addr_t address;
109
110 for (i = 0; i < buffer->page_count; i++) {
111 address = page_private(buffer->pages[i]);
112 dma_unmap_page(card->device, address,
113 PAGE_SIZE, buffer->direction);
114 __free_page(buffer->pages[i]);
115 }
116
117 kfree(buffer->pages);
118 buffer->pages = NULL;
119 }
120 EXPORT_SYMBOL(fw_iso_buffer_destroy);
121
122 /* Convert DMA address to offset into virtually contiguous buffer. */
fw_iso_buffer_lookup(struct fw_iso_buffer * buffer,dma_addr_t completed)123 size_t fw_iso_buffer_lookup(struct fw_iso_buffer *buffer, dma_addr_t completed)
124 {
125 int i;
126 dma_addr_t address;
127 ssize_t offset;
128
129 for (i = 0; i < buffer->page_count; i++) {
130 address = page_private(buffer->pages[i]);
131 offset = (ssize_t)completed - (ssize_t)address;
132 if (offset > 0 && offset <= PAGE_SIZE)
133 return (i << PAGE_SHIFT) + offset;
134 }
135
136 return 0;
137 }
138
fw_iso_context_create(struct fw_card * card,int type,int channel,int speed,size_t header_size,fw_iso_callback_t callback,void * callback_data)139 struct fw_iso_context *fw_iso_context_create(struct fw_card *card,
140 int type, int channel, int speed, size_t header_size,
141 fw_iso_callback_t callback, void *callback_data)
142 {
143 struct fw_iso_context *ctx;
144
145 ctx = card->driver->allocate_iso_context(card,
146 type, channel, header_size);
147 if (IS_ERR(ctx))
148 return ctx;
149
150 ctx->card = card;
151 ctx->type = type;
152 ctx->channel = channel;
153 ctx->speed = speed;
154 ctx->header_size = header_size;
155 ctx->callback.sc = callback;
156 ctx->callback_data = callback_data;
157
158 return ctx;
159 }
160 EXPORT_SYMBOL(fw_iso_context_create);
161
fw_iso_context_destroy(struct fw_iso_context * ctx)162 void fw_iso_context_destroy(struct fw_iso_context *ctx)
163 {
164 ctx->card->driver->free_iso_context(ctx);
165 }
166 EXPORT_SYMBOL(fw_iso_context_destroy);
167
fw_iso_context_start(struct fw_iso_context * ctx,int cycle,int sync,int tags)168 int fw_iso_context_start(struct fw_iso_context *ctx,
169 int cycle, int sync, int tags)
170 {
171 return ctx->card->driver->start_iso(ctx, cycle, sync, tags);
172 }
173 EXPORT_SYMBOL(fw_iso_context_start);
174
fw_iso_context_set_channels(struct fw_iso_context * ctx,u64 * channels)175 int fw_iso_context_set_channels(struct fw_iso_context *ctx, u64 *channels)
176 {
177 return ctx->card->driver->set_iso_channels(ctx, channels);
178 }
179
fw_iso_context_queue(struct fw_iso_context * ctx,struct fw_iso_packet * packet,struct fw_iso_buffer * buffer,unsigned long payload)180 int fw_iso_context_queue(struct fw_iso_context *ctx,
181 struct fw_iso_packet *packet,
182 struct fw_iso_buffer *buffer,
183 unsigned long payload)
184 {
185 return ctx->card->driver->queue_iso(ctx, packet, buffer, payload);
186 }
187 EXPORT_SYMBOL(fw_iso_context_queue);
188
fw_iso_context_queue_flush(struct fw_iso_context * ctx)189 void fw_iso_context_queue_flush(struct fw_iso_context *ctx)
190 {
191 ctx->card->driver->flush_queue_iso(ctx);
192 }
193 EXPORT_SYMBOL(fw_iso_context_queue_flush);
194
fw_iso_context_flush_completions(struct fw_iso_context * ctx)195 int fw_iso_context_flush_completions(struct fw_iso_context *ctx)
196 {
197 return ctx->card->driver->flush_iso_completions(ctx);
198 }
199 EXPORT_SYMBOL(fw_iso_context_flush_completions);
200
fw_iso_context_stop(struct fw_iso_context * ctx)201 int fw_iso_context_stop(struct fw_iso_context *ctx)
202 {
203 return ctx->card->driver->stop_iso(ctx);
204 }
205 EXPORT_SYMBOL(fw_iso_context_stop);
206
207 /*
208 * Isochronous bus resource management (channels, bandwidth), client side
209 */
210
manage_bandwidth(struct fw_card * card,int irm_id,int generation,int bandwidth,bool allocate)211 static int manage_bandwidth(struct fw_card *card, int irm_id, int generation,
212 int bandwidth, bool allocate)
213 {
214 int try, new, old = allocate ? BANDWIDTH_AVAILABLE_INITIAL : 0;
215 __be32 data[2];
216
217 /*
218 * On a 1394a IRM with low contention, try < 1 is enough.
219 * On a 1394-1995 IRM, we need at least try < 2.
220 * Let's just do try < 5.
221 */
222 for (try = 0; try < 5; try++) {
223 new = allocate ? old - bandwidth : old + bandwidth;
224 if (new < 0 || new > BANDWIDTH_AVAILABLE_INITIAL)
225 return -EBUSY;
226
227 data[0] = cpu_to_be32(old);
228 data[1] = cpu_to_be32(new);
229 switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
230 irm_id, generation, SCODE_100,
231 CSR_REGISTER_BASE + CSR_BANDWIDTH_AVAILABLE,
232 data, 8)) {
233 case RCODE_GENERATION:
234 /* A generation change frees all bandwidth. */
235 return allocate ? -EAGAIN : bandwidth;
236
237 case RCODE_COMPLETE:
238 if (be32_to_cpup(data) == old)
239 return bandwidth;
240
241 old = be32_to_cpup(data);
242 /* Fall through. */
243 }
244 }
245
246 return -EIO;
247 }
248
manage_channel(struct fw_card * card,int irm_id,int generation,u32 channels_mask,u64 offset,bool allocate)249 static int manage_channel(struct fw_card *card, int irm_id, int generation,
250 u32 channels_mask, u64 offset, bool allocate)
251 {
252 __be32 bit, all, old;
253 __be32 data[2];
254 int channel, ret = -EIO, retry = 5;
255
256 old = all = allocate ? cpu_to_be32(~0) : 0;
257
258 for (channel = 0; channel < 32; channel++) {
259 if (!(channels_mask & 1 << channel))
260 continue;
261
262 ret = -EBUSY;
263
264 bit = cpu_to_be32(1 << (31 - channel));
265 if ((old & bit) != (all & bit))
266 continue;
267
268 data[0] = old;
269 data[1] = old ^ bit;
270 switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
271 irm_id, generation, SCODE_100,
272 offset, data, 8)) {
273 case RCODE_GENERATION:
274 /* A generation change frees all channels. */
275 return allocate ? -EAGAIN : channel;
276
277 case RCODE_COMPLETE:
278 if (data[0] == old)
279 return channel;
280
281 old = data[0];
282
283 /* Is the IRM 1394a-2000 compliant? */
284 if ((data[0] & bit) == (data[1] & bit))
285 continue;
286
287 /* 1394-1995 IRM, fall through to retry. */
288 default:
289 if (retry) {
290 retry--;
291 channel--;
292 } else {
293 ret = -EIO;
294 }
295 }
296 }
297
298 return ret;
299 }
300
deallocate_channel(struct fw_card * card,int irm_id,int generation,int channel)301 static void deallocate_channel(struct fw_card *card, int irm_id,
302 int generation, int channel)
303 {
304 u32 mask;
305 u64 offset;
306
307 mask = channel < 32 ? 1 << channel : 1 << (channel - 32);
308 offset = channel < 32 ? CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI :
309 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO;
310
311 manage_channel(card, irm_id, generation, mask, offset, false);
312 }
313
314 /**
315 * fw_iso_resource_manage() - Allocate or deallocate a channel and/or bandwidth
316 *
317 * In parameters: card, generation, channels_mask, bandwidth, allocate
318 * Out parameters: channel, bandwidth
319 * This function blocks (sleeps) during communication with the IRM.
320 *
321 * Allocates or deallocates at most one channel out of channels_mask.
322 * channels_mask is a bitfield with MSB for channel 63 and LSB for channel 0.
323 * (Note, the IRM's CHANNELS_AVAILABLE is a big-endian bitfield with MSB for
324 * channel 0 and LSB for channel 63.)
325 * Allocates or deallocates as many bandwidth allocation units as specified.
326 *
327 * Returns channel < 0 if no channel was allocated or deallocated.
328 * Returns bandwidth = 0 if no bandwidth was allocated or deallocated.
329 *
330 * If generation is stale, deallocations succeed but allocations fail with
331 * channel = -EAGAIN.
332 *
333 * If channel allocation fails, no bandwidth will be allocated either.
334 * If bandwidth allocation fails, no channel will be allocated either.
335 * But deallocations of channel and bandwidth are tried independently
336 * of each other's success.
337 */
fw_iso_resource_manage(struct fw_card * card,int generation,u64 channels_mask,int * channel,int * bandwidth,bool allocate)338 void fw_iso_resource_manage(struct fw_card *card, int generation,
339 u64 channels_mask, int *channel, int *bandwidth,
340 bool allocate)
341 {
342 u32 channels_hi = channels_mask; /* channels 31...0 */
343 u32 channels_lo = channels_mask >> 32; /* channels 63...32 */
344 int irm_id, ret, c = -EINVAL;
345
346 spin_lock_irq(&card->lock);
347 irm_id = card->irm_node->node_id;
348 spin_unlock_irq(&card->lock);
349
350 if (channels_hi)
351 c = manage_channel(card, irm_id, generation, channels_hi,
352 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI,
353 allocate);
354 if (channels_lo && c < 0) {
355 c = manage_channel(card, irm_id, generation, channels_lo,
356 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO,
357 allocate);
358 if (c >= 0)
359 c += 32;
360 }
361 *channel = c;
362
363 if (allocate && channels_mask != 0 && c < 0)
364 *bandwidth = 0;
365
366 if (*bandwidth == 0)
367 return;
368
369 ret = manage_bandwidth(card, irm_id, generation, *bandwidth, allocate);
370 if (ret < 0)
371 *bandwidth = 0;
372
373 if (allocate && ret < 0) {
374 if (c >= 0)
375 deallocate_channel(card, irm_id, generation, c);
376 *channel = ret;
377 }
378 }
379 EXPORT_SYMBOL(fw_iso_resource_manage);
380