1 /*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/i2c.h>
16 #include <linux/gpio.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/input.h>
20 #include <linux/spi/flash.h>
21 #include <linux/spi/spi.h>
22
23 #include <mach/common.h>
24 #include <mach/hardware.h>
25 #include <mach/iomux-mx51.h>
26
27 #include <asm/setup.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/time.h>
31
32 #include "devices-imx51.h"
33 #include "cpu_op-mx51.h"
34
35 #define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
36 #define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
37 #define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5)
38 #define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
39 #define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
40 #define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
41 #define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
42 #define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
43 #define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
44
45 /* USB_CTRL_1 */
46 #define MX51_USB_CTRL_1_OFFSET 0x10
47 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
48
49 #define MX51_USB_PLLDIV_12_MHZ 0x00
50 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
51 #define MX51_USB_PLL_DIV_24_MHZ 0x02
52
53 static struct gpio_keys_button babbage_buttons[] = {
54 {
55 .gpio = BABBAGE_POWER_KEY,
56 .code = BTN_0,
57 .desc = "PWR",
58 .active_low = 1,
59 .wakeup = 1,
60 },
61 };
62
63 static const struct gpio_keys_platform_data imx_button_data __initconst = {
64 .buttons = babbage_buttons,
65 .nbuttons = ARRAY_SIZE(babbage_buttons),
66 };
67
68 static iomux_v3_cfg_t mx51babbage_pads[] = {
69 /* UART1 */
70 MX51_PAD_UART1_RXD__UART1_RXD,
71 MX51_PAD_UART1_TXD__UART1_TXD,
72 MX51_PAD_UART1_RTS__UART1_RTS,
73 MX51_PAD_UART1_CTS__UART1_CTS,
74
75 /* UART2 */
76 MX51_PAD_UART2_RXD__UART2_RXD,
77 MX51_PAD_UART2_TXD__UART2_TXD,
78
79 /* UART3 */
80 MX51_PAD_EIM_D25__UART3_RXD,
81 MX51_PAD_EIM_D26__UART3_TXD,
82 MX51_PAD_EIM_D27__UART3_RTS,
83 MX51_PAD_EIM_D24__UART3_CTS,
84
85 /* I2C1 */
86 MX51_PAD_EIM_D16__I2C1_SDA,
87 MX51_PAD_EIM_D19__I2C1_SCL,
88
89 /* I2C2 */
90 MX51_PAD_KEY_COL4__I2C2_SCL,
91 MX51_PAD_KEY_COL5__I2C2_SDA,
92
93 /* HSI2C */
94 MX51_PAD_I2C1_CLK__I2C1_CLK,
95 MX51_PAD_I2C1_DAT__I2C1_DAT,
96
97 /* USB HOST1 */
98 MX51_PAD_USBH1_CLK__USBH1_CLK,
99 MX51_PAD_USBH1_DIR__USBH1_DIR,
100 MX51_PAD_USBH1_NXT__USBH1_NXT,
101 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
102 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
103 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
104 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
105 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
106 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
107 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
108 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
109
110 /* USB HUB reset line*/
111 MX51_PAD_GPIO1_7__GPIO1_7,
112
113 /* USB PHY reset line */
114 MX51_PAD_EIM_D21__GPIO2_5,
115
116 /* FEC */
117 MX51_PAD_EIM_EB2__FEC_MDIO,
118 MX51_PAD_EIM_EB3__FEC_RDATA1,
119 MX51_PAD_EIM_CS2__FEC_RDATA2,
120 MX51_PAD_EIM_CS3__FEC_RDATA3,
121 MX51_PAD_EIM_CS4__FEC_RX_ER,
122 MX51_PAD_EIM_CS5__FEC_CRS,
123 MX51_PAD_NANDF_RB2__FEC_COL,
124 MX51_PAD_NANDF_RB3__FEC_RX_CLK,
125 MX51_PAD_NANDF_D9__FEC_RDATA0,
126 MX51_PAD_NANDF_D8__FEC_TDATA0,
127 MX51_PAD_NANDF_CS2__FEC_TX_ER,
128 MX51_PAD_NANDF_CS3__FEC_MDC,
129 MX51_PAD_NANDF_CS4__FEC_TDATA1,
130 MX51_PAD_NANDF_CS5__FEC_TDATA2,
131 MX51_PAD_NANDF_CS6__FEC_TDATA3,
132 MX51_PAD_NANDF_CS7__FEC_TX_EN,
133 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
134
135 /* FEC PHY reset line */
136 MX51_PAD_EIM_A20__GPIO2_14,
137
138 /* SD 1 */
139 MX51_PAD_SD1_CMD__SD1_CMD,
140 MX51_PAD_SD1_CLK__SD1_CLK,
141 MX51_PAD_SD1_DATA0__SD1_DATA0,
142 MX51_PAD_SD1_DATA1__SD1_DATA1,
143 MX51_PAD_SD1_DATA2__SD1_DATA2,
144 MX51_PAD_SD1_DATA3__SD1_DATA3,
145 /* CD/WP from controller */
146 MX51_PAD_GPIO1_0__SD1_CD,
147 MX51_PAD_GPIO1_1__SD1_WP,
148
149 /* SD 2 */
150 MX51_PAD_SD2_CMD__SD2_CMD,
151 MX51_PAD_SD2_CLK__SD2_CLK,
152 MX51_PAD_SD2_DATA0__SD2_DATA0,
153 MX51_PAD_SD2_DATA1__SD2_DATA1,
154 MX51_PAD_SD2_DATA2__SD2_DATA2,
155 MX51_PAD_SD2_DATA3__SD2_DATA3,
156 /* CD/WP gpio */
157 MX51_PAD_GPIO1_6__GPIO1_6,
158 MX51_PAD_GPIO1_5__GPIO1_5,
159
160 /* eCSPI1 */
161 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
162 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
163 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
164 MX51_PAD_CSPI1_SS0__GPIO4_24,
165 MX51_PAD_CSPI1_SS1__GPIO4_25,
166 };
167
168 /* Serial ports */
169 static const struct imxuart_platform_data uart_pdata __initconst = {
170 .flags = IMXUART_HAVE_RTSCTS,
171 };
172
173 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
174 .bitrate = 100000,
175 };
176
177 static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
178 .bitrate = 400000,
179 };
180
181 static struct gpio mx51_babbage_usbh1_gpios[] = {
182 { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
183 { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
184 };
185
gpio_usbh1_active(void)186 static int gpio_usbh1_active(void)
187 {
188 iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
189 int ret;
190
191 /* Set USBH1_STP to GPIO and toggle it */
192 mxc_iomux_v3_setup_pad(usbh1stp_gpio);
193 ret = gpio_request_array(mx51_babbage_usbh1_gpios,
194 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
195
196 if (ret) {
197 pr_debug("failed to get USBH1 pins: %d\n", ret);
198 return ret;
199 }
200
201 msleep(100);
202 gpio_set_value(BABBAGE_USBH1_STP, 1);
203 gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
204 gpio_free_array(mx51_babbage_usbh1_gpios,
205 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
206 return 0;
207 }
208
babbage_usbhub_reset(void)209 static inline void babbage_usbhub_reset(void)
210 {
211 int ret;
212
213 /* Reset USB hub */
214 ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
215 GPIOF_OUT_INIT_LOW, "GPIO1_7");
216 if (ret) {
217 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
218 return;
219 }
220
221 msleep(2);
222 /* Deassert reset */
223 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
224 }
225
babbage_fec_reset(void)226 static inline void babbage_fec_reset(void)
227 {
228 int ret;
229
230 /* reset FEC PHY */
231 ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
232 GPIOF_OUT_INIT_LOW, "fec-phy-reset");
233 if (ret) {
234 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
235 return;
236 }
237 msleep(1);
238 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
239 }
240
241 /* This function is board specific as the bit mask for the plldiv will also
242 be different for other Freescale SoCs, thus a common bitmask is not
243 possible and cannot get place in /plat-mxc/ehci.c.*/
initialize_otg_port(struct platform_device * pdev)244 static int initialize_otg_port(struct platform_device *pdev)
245 {
246 u32 v;
247 void __iomem *usb_base;
248 void __iomem *usbother_base;
249
250 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
251 if (!usb_base)
252 return -ENOMEM;
253 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
254
255 /* Set the PHY clock to 19.2MHz */
256 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
257 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
258 v |= MX51_USB_PLL_DIV_19_2_MHZ;
259 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
260 iounmap(usb_base);
261
262 mdelay(10);
263
264 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
265 }
266
initialize_usbh1_port(struct platform_device * pdev)267 static int initialize_usbh1_port(struct platform_device *pdev)
268 {
269 u32 v;
270 void __iomem *usb_base;
271 void __iomem *usbother_base;
272
273 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
274 if (!usb_base)
275 return -ENOMEM;
276 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
277
278 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
279 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
280 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
281 iounmap(usb_base);
282
283 mdelay(10);
284
285 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
286 MXC_EHCI_ITC_NO_THRESHOLD);
287 }
288
289 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
290 .init = initialize_otg_port,
291 .portsc = MXC_EHCI_UTMI_16BIT,
292 };
293
294 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
295 .operating_mode = FSL_USB2_DR_DEVICE,
296 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
297 };
298
299 static const struct mxc_usbh_platform_data usbh1_config __initconst = {
300 .init = initialize_usbh1_port,
301 .portsc = MXC_EHCI_MODE_ULPI,
302 };
303
304 static int otg_mode_host;
305
babbage_otg_mode(char * options)306 static int __init babbage_otg_mode(char *options)
307 {
308 if (!strcmp(options, "host"))
309 otg_mode_host = 1;
310 else if (!strcmp(options, "device"))
311 otg_mode_host = 0;
312 else
313 pr_info("otg_mode neither \"host\" nor \"device\". "
314 "Defaulting to device\n");
315 return 0;
316 }
317 __setup("otg_mode=", babbage_otg_mode);
318
319 static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
320 {
321 .modalias = "mtd_dataflash",
322 .max_speed_hz = 25000000,
323 .bus_num = 0,
324 .chip_select = 1,
325 .mode = SPI_MODE_0,
326 .platform_data = NULL,
327 },
328 };
329
330 static int mx51_babbage_spi_cs[] = {
331 BABBAGE_ECSPI1_CS0,
332 BABBAGE_ECSPI1_CS1,
333 };
334
335 static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
336 .chipselect = mx51_babbage_spi_cs,
337 .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
338 };
339
340 static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
341 .cd_type = ESDHC_CD_CONTROLLER,
342 .wp_type = ESDHC_WP_CONTROLLER,
343 };
344
345 static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
346 .cd_gpio = BABBAGE_SD2_CD,
347 .wp_gpio = BABBAGE_SD2_WP,
348 .cd_type = ESDHC_CD_GPIO,
349 .wp_type = ESDHC_WP_GPIO,
350 };
351
imx51_babbage_common_init(void)352 void __init imx51_babbage_common_init(void)
353 {
354 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
355 ARRAY_SIZE(mx51babbage_pads));
356 }
357
358 /*
359 * Board specific initialization.
360 */
mx51_babbage_init(void)361 static void __init mx51_babbage_init(void)
362 {
363 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
364 iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
365 PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH);
366
367 imx51_soc_init();
368
369 #if defined(CONFIG_CPU_FREQ_IMX)
370 get_cpu_op = mx51_get_cpu_op;
371 #endif
372 imx51_babbage_common_init();
373
374 imx51_add_imx_uart(0, &uart_pdata);
375 imx51_add_imx_uart(1, NULL);
376 imx51_add_imx_uart(2, &uart_pdata);
377
378 babbage_fec_reset();
379 imx51_add_fec(NULL);
380
381 /* Set the PAD settings for the pwr key. */
382 mxc_iomux_v3_setup_pad(power_key);
383 imx_add_gpio_keys(&imx_button_data);
384
385 imx51_add_imx_i2c(0, &babbage_i2c_data);
386 imx51_add_imx_i2c(1, &babbage_i2c_data);
387 imx51_add_hsi2c(&babbage_hsi2c_data);
388
389 if (otg_mode_host)
390 imx51_add_mxc_ehci_otg(&dr_utmi_config);
391 else {
392 initialize_otg_port(NULL);
393 imx51_add_fsl_usb2_udc(&usb_pdata);
394 }
395
396 gpio_usbh1_active();
397 imx51_add_mxc_ehci_hs(1, &usbh1_config);
398 /* setback USBH1_STP to be function */
399 mxc_iomux_v3_setup_pad(usbh1stp);
400 babbage_usbhub_reset();
401
402 imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
403 imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
404
405 spi_register_board_info(mx51_babbage_spi_board_info,
406 ARRAY_SIZE(mx51_babbage_spi_board_info));
407 imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
408 imx51_add_imx2_wdt(0, NULL);
409 }
410
mx51_babbage_timer_init(void)411 static void __init mx51_babbage_timer_init(void)
412 {
413 mx51_clocks_init(32768, 24000000, 22579200, 0);
414 }
415
416 static struct sys_timer mx51_babbage_timer = {
417 .init = mx51_babbage_timer_init,
418 };
419
420 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
421 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
422 .atag_offset = 0x100,
423 .map_io = mx51_map_io,
424 .init_early = imx51_init_early,
425 .init_irq = mx51_init_irq,
426 .handle_irq = imx51_handle_irq,
427 .timer = &mx51_babbage_timer,
428 .init_machine = mx51_babbage_init,
429 .restart = mxc_restart,
430 MACHINE_END
431