1 /*
2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
6 */
7
8 #include <linux/stddef.h>
9 #include <linux/types.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
13
14 #include <asm/hardirq.h>
15 #include <asm/apic.h>
16
17 #include "perf_event.h"
18
19 /*
20 * Intel PerfMon, used on Core and later.
21 */
22 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
23 {
24 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
25 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
26 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
27 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
28 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
29 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
30 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
31 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
32 };
33
34 static struct event_constraint intel_core_event_constraints[] __read_mostly =
35 {
36 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
37 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
38 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
39 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
40 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
41 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
42 EVENT_CONSTRAINT_END
43 };
44
45 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
46 {
47 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
48 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
49 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
50 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
51 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
52 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
53 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
54 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
55 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
56 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
57 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
58 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
59 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
60 EVENT_CONSTRAINT_END
61 };
62
63 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
64 {
65 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
66 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
67 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
68 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
69 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
70 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
71 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
72 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
73 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
74 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
75 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
76 EVENT_CONSTRAINT_END
77 };
78
79 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
80 {
81 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
82 EVENT_EXTRA_END
83 };
84
85 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
86 {
87 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
88 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
89 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
90 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
91 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
92 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
93 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
94 EVENT_CONSTRAINT_END
95 };
96
97 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
98 {
99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
101 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
102 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
103 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
104 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
105 EVENT_CONSTRAINT_END
106 };
107
108 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
109 {
110 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
111 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
112 EVENT_EXTRA_END
113 };
114
115 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
116 {
117 EVENT_CONSTRAINT_END
118 };
119
120 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
121 {
122 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
123 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
124 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
125 EVENT_CONSTRAINT_END
126 };
127
128 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
129 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
130 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
131 EVENT_EXTRA_END
132 };
133
134 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
135 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
136 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
137 EVENT_EXTRA_END
138 };
139
intel_pmu_event_map(int hw_event)140 static u64 intel_pmu_event_map(int hw_event)
141 {
142 return intel_perfmon_event_map[hw_event];
143 }
144
145 static __initconst const u64 snb_hw_cache_event_ids
146 [PERF_COUNT_HW_CACHE_MAX]
147 [PERF_COUNT_HW_CACHE_OP_MAX]
148 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
149 {
150 [ C(L1D) ] = {
151 [ C(OP_READ) ] = {
152 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
153 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
154 },
155 [ C(OP_WRITE) ] = {
156 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
157 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
158 },
159 [ C(OP_PREFETCH) ] = {
160 [ C(RESULT_ACCESS) ] = 0x0,
161 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
162 },
163 },
164 [ C(L1I ) ] = {
165 [ C(OP_READ) ] = {
166 [ C(RESULT_ACCESS) ] = 0x0,
167 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
168 },
169 [ C(OP_WRITE) ] = {
170 [ C(RESULT_ACCESS) ] = -1,
171 [ C(RESULT_MISS) ] = -1,
172 },
173 [ C(OP_PREFETCH) ] = {
174 [ C(RESULT_ACCESS) ] = 0x0,
175 [ C(RESULT_MISS) ] = 0x0,
176 },
177 },
178 [ C(LL ) ] = {
179 [ C(OP_READ) ] = {
180 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
181 [ C(RESULT_ACCESS) ] = 0x01b7,
182 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
183 [ C(RESULT_MISS) ] = 0x01b7,
184 },
185 [ C(OP_WRITE) ] = {
186 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
187 [ C(RESULT_ACCESS) ] = 0x01b7,
188 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
189 [ C(RESULT_MISS) ] = 0x01b7,
190 },
191 [ C(OP_PREFETCH) ] = {
192 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
193 [ C(RESULT_ACCESS) ] = 0x01b7,
194 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
195 [ C(RESULT_MISS) ] = 0x01b7,
196 },
197 },
198 [ C(DTLB) ] = {
199 [ C(OP_READ) ] = {
200 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
201 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
202 },
203 [ C(OP_WRITE) ] = {
204 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
205 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
206 },
207 [ C(OP_PREFETCH) ] = {
208 [ C(RESULT_ACCESS) ] = 0x0,
209 [ C(RESULT_MISS) ] = 0x0,
210 },
211 },
212 [ C(ITLB) ] = {
213 [ C(OP_READ) ] = {
214 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
215 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
216 },
217 [ C(OP_WRITE) ] = {
218 [ C(RESULT_ACCESS) ] = -1,
219 [ C(RESULT_MISS) ] = -1,
220 },
221 [ C(OP_PREFETCH) ] = {
222 [ C(RESULT_ACCESS) ] = -1,
223 [ C(RESULT_MISS) ] = -1,
224 },
225 },
226 [ C(BPU ) ] = {
227 [ C(OP_READ) ] = {
228 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
229 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
230 },
231 [ C(OP_WRITE) ] = {
232 [ C(RESULT_ACCESS) ] = -1,
233 [ C(RESULT_MISS) ] = -1,
234 },
235 [ C(OP_PREFETCH) ] = {
236 [ C(RESULT_ACCESS) ] = -1,
237 [ C(RESULT_MISS) ] = -1,
238 },
239 },
240 [ C(NODE) ] = {
241 [ C(OP_READ) ] = {
242 [ C(RESULT_ACCESS) ] = -1,
243 [ C(RESULT_MISS) ] = -1,
244 },
245 [ C(OP_WRITE) ] = {
246 [ C(RESULT_ACCESS) ] = -1,
247 [ C(RESULT_MISS) ] = -1,
248 },
249 [ C(OP_PREFETCH) ] = {
250 [ C(RESULT_ACCESS) ] = -1,
251 [ C(RESULT_MISS) ] = -1,
252 },
253 },
254
255 };
256
257 static __initconst const u64 westmere_hw_cache_event_ids
258 [PERF_COUNT_HW_CACHE_MAX]
259 [PERF_COUNT_HW_CACHE_OP_MAX]
260 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
261 {
262 [ C(L1D) ] = {
263 [ C(OP_READ) ] = {
264 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
265 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
266 },
267 [ C(OP_WRITE) ] = {
268 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
269 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
270 },
271 [ C(OP_PREFETCH) ] = {
272 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
273 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
274 },
275 },
276 [ C(L1I ) ] = {
277 [ C(OP_READ) ] = {
278 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
279 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
280 },
281 [ C(OP_WRITE) ] = {
282 [ C(RESULT_ACCESS) ] = -1,
283 [ C(RESULT_MISS) ] = -1,
284 },
285 [ C(OP_PREFETCH) ] = {
286 [ C(RESULT_ACCESS) ] = 0x0,
287 [ C(RESULT_MISS) ] = 0x0,
288 },
289 },
290 [ C(LL ) ] = {
291 [ C(OP_READ) ] = {
292 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
293 [ C(RESULT_ACCESS) ] = 0x01b7,
294 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
295 [ C(RESULT_MISS) ] = 0x01b7,
296 },
297 /*
298 * Use RFO, not WRITEBACK, because a write miss would typically occur
299 * on RFO.
300 */
301 [ C(OP_WRITE) ] = {
302 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
303 [ C(RESULT_ACCESS) ] = 0x01b7,
304 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
305 [ C(RESULT_MISS) ] = 0x01b7,
306 },
307 [ C(OP_PREFETCH) ] = {
308 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
309 [ C(RESULT_ACCESS) ] = 0x01b7,
310 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
311 [ C(RESULT_MISS) ] = 0x01b7,
312 },
313 },
314 [ C(DTLB) ] = {
315 [ C(OP_READ) ] = {
316 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
317 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
318 },
319 [ C(OP_WRITE) ] = {
320 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
321 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
322 },
323 [ C(OP_PREFETCH) ] = {
324 [ C(RESULT_ACCESS) ] = 0x0,
325 [ C(RESULT_MISS) ] = 0x0,
326 },
327 },
328 [ C(ITLB) ] = {
329 [ C(OP_READ) ] = {
330 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
331 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
332 },
333 [ C(OP_WRITE) ] = {
334 [ C(RESULT_ACCESS) ] = -1,
335 [ C(RESULT_MISS) ] = -1,
336 },
337 [ C(OP_PREFETCH) ] = {
338 [ C(RESULT_ACCESS) ] = -1,
339 [ C(RESULT_MISS) ] = -1,
340 },
341 },
342 [ C(BPU ) ] = {
343 [ C(OP_READ) ] = {
344 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
345 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
346 },
347 [ C(OP_WRITE) ] = {
348 [ C(RESULT_ACCESS) ] = -1,
349 [ C(RESULT_MISS) ] = -1,
350 },
351 [ C(OP_PREFETCH) ] = {
352 [ C(RESULT_ACCESS) ] = -1,
353 [ C(RESULT_MISS) ] = -1,
354 },
355 },
356 [ C(NODE) ] = {
357 [ C(OP_READ) ] = {
358 [ C(RESULT_ACCESS) ] = 0x01b7,
359 [ C(RESULT_MISS) ] = 0x01b7,
360 },
361 [ C(OP_WRITE) ] = {
362 [ C(RESULT_ACCESS) ] = 0x01b7,
363 [ C(RESULT_MISS) ] = 0x01b7,
364 },
365 [ C(OP_PREFETCH) ] = {
366 [ C(RESULT_ACCESS) ] = 0x01b7,
367 [ C(RESULT_MISS) ] = 0x01b7,
368 },
369 },
370 };
371
372 /*
373 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
374 * See IA32 SDM Vol 3B 30.6.1.3
375 */
376
377 #define NHM_DMND_DATA_RD (1 << 0)
378 #define NHM_DMND_RFO (1 << 1)
379 #define NHM_DMND_IFETCH (1 << 2)
380 #define NHM_DMND_WB (1 << 3)
381 #define NHM_PF_DATA_RD (1 << 4)
382 #define NHM_PF_DATA_RFO (1 << 5)
383 #define NHM_PF_IFETCH (1 << 6)
384 #define NHM_OFFCORE_OTHER (1 << 7)
385 #define NHM_UNCORE_HIT (1 << 8)
386 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
387 #define NHM_OTHER_CORE_HITM (1 << 10)
388 /* reserved */
389 #define NHM_REMOTE_CACHE_FWD (1 << 12)
390 #define NHM_REMOTE_DRAM (1 << 13)
391 #define NHM_LOCAL_DRAM (1 << 14)
392 #define NHM_NON_DRAM (1 << 15)
393
394 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
395 #define NHM_REMOTE (NHM_REMOTE_DRAM)
396
397 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
398 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
399 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
400
401 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
402 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
403 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
404
405 static __initconst const u64 nehalem_hw_cache_extra_regs
406 [PERF_COUNT_HW_CACHE_MAX]
407 [PERF_COUNT_HW_CACHE_OP_MAX]
408 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
409 {
410 [ C(LL ) ] = {
411 [ C(OP_READ) ] = {
412 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
413 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
414 },
415 [ C(OP_WRITE) ] = {
416 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
417 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
418 },
419 [ C(OP_PREFETCH) ] = {
420 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
421 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
422 },
423 },
424 [ C(NODE) ] = {
425 [ C(OP_READ) ] = {
426 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
427 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
428 },
429 [ C(OP_WRITE) ] = {
430 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
431 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
432 },
433 [ C(OP_PREFETCH) ] = {
434 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
435 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
436 },
437 },
438 };
439
440 static __initconst const u64 nehalem_hw_cache_event_ids
441 [PERF_COUNT_HW_CACHE_MAX]
442 [PERF_COUNT_HW_CACHE_OP_MAX]
443 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
444 {
445 [ C(L1D) ] = {
446 [ C(OP_READ) ] = {
447 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
448 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
449 },
450 [ C(OP_WRITE) ] = {
451 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
452 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
453 },
454 [ C(OP_PREFETCH) ] = {
455 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
456 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
457 },
458 },
459 [ C(L1I ) ] = {
460 [ C(OP_READ) ] = {
461 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
462 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
463 },
464 [ C(OP_WRITE) ] = {
465 [ C(RESULT_ACCESS) ] = -1,
466 [ C(RESULT_MISS) ] = -1,
467 },
468 [ C(OP_PREFETCH) ] = {
469 [ C(RESULT_ACCESS) ] = 0x0,
470 [ C(RESULT_MISS) ] = 0x0,
471 },
472 },
473 [ C(LL ) ] = {
474 [ C(OP_READ) ] = {
475 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
476 [ C(RESULT_ACCESS) ] = 0x01b7,
477 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
478 [ C(RESULT_MISS) ] = 0x01b7,
479 },
480 /*
481 * Use RFO, not WRITEBACK, because a write miss would typically occur
482 * on RFO.
483 */
484 [ C(OP_WRITE) ] = {
485 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
486 [ C(RESULT_ACCESS) ] = 0x01b7,
487 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
488 [ C(RESULT_MISS) ] = 0x01b7,
489 },
490 [ C(OP_PREFETCH) ] = {
491 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
492 [ C(RESULT_ACCESS) ] = 0x01b7,
493 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
494 [ C(RESULT_MISS) ] = 0x01b7,
495 },
496 },
497 [ C(DTLB) ] = {
498 [ C(OP_READ) ] = {
499 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
500 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
501 },
502 [ C(OP_WRITE) ] = {
503 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
504 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
505 },
506 [ C(OP_PREFETCH) ] = {
507 [ C(RESULT_ACCESS) ] = 0x0,
508 [ C(RESULT_MISS) ] = 0x0,
509 },
510 },
511 [ C(ITLB) ] = {
512 [ C(OP_READ) ] = {
513 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
514 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
515 },
516 [ C(OP_WRITE) ] = {
517 [ C(RESULT_ACCESS) ] = -1,
518 [ C(RESULT_MISS) ] = -1,
519 },
520 [ C(OP_PREFETCH) ] = {
521 [ C(RESULT_ACCESS) ] = -1,
522 [ C(RESULT_MISS) ] = -1,
523 },
524 },
525 [ C(BPU ) ] = {
526 [ C(OP_READ) ] = {
527 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
528 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
529 },
530 [ C(OP_WRITE) ] = {
531 [ C(RESULT_ACCESS) ] = -1,
532 [ C(RESULT_MISS) ] = -1,
533 },
534 [ C(OP_PREFETCH) ] = {
535 [ C(RESULT_ACCESS) ] = -1,
536 [ C(RESULT_MISS) ] = -1,
537 },
538 },
539 [ C(NODE) ] = {
540 [ C(OP_READ) ] = {
541 [ C(RESULT_ACCESS) ] = 0x01b7,
542 [ C(RESULT_MISS) ] = 0x01b7,
543 },
544 [ C(OP_WRITE) ] = {
545 [ C(RESULT_ACCESS) ] = 0x01b7,
546 [ C(RESULT_MISS) ] = 0x01b7,
547 },
548 [ C(OP_PREFETCH) ] = {
549 [ C(RESULT_ACCESS) ] = 0x01b7,
550 [ C(RESULT_MISS) ] = 0x01b7,
551 },
552 },
553 };
554
555 static __initconst const u64 core2_hw_cache_event_ids
556 [PERF_COUNT_HW_CACHE_MAX]
557 [PERF_COUNT_HW_CACHE_OP_MAX]
558 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
559 {
560 [ C(L1D) ] = {
561 [ C(OP_READ) ] = {
562 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
563 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
564 },
565 [ C(OP_WRITE) ] = {
566 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
567 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
568 },
569 [ C(OP_PREFETCH) ] = {
570 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
571 [ C(RESULT_MISS) ] = 0,
572 },
573 },
574 [ C(L1I ) ] = {
575 [ C(OP_READ) ] = {
576 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
577 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
578 },
579 [ C(OP_WRITE) ] = {
580 [ C(RESULT_ACCESS) ] = -1,
581 [ C(RESULT_MISS) ] = -1,
582 },
583 [ C(OP_PREFETCH) ] = {
584 [ C(RESULT_ACCESS) ] = 0,
585 [ C(RESULT_MISS) ] = 0,
586 },
587 },
588 [ C(LL ) ] = {
589 [ C(OP_READ) ] = {
590 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
591 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
592 },
593 [ C(OP_WRITE) ] = {
594 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
595 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
596 },
597 [ C(OP_PREFETCH) ] = {
598 [ C(RESULT_ACCESS) ] = 0,
599 [ C(RESULT_MISS) ] = 0,
600 },
601 },
602 [ C(DTLB) ] = {
603 [ C(OP_READ) ] = {
604 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
605 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
606 },
607 [ C(OP_WRITE) ] = {
608 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
609 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
610 },
611 [ C(OP_PREFETCH) ] = {
612 [ C(RESULT_ACCESS) ] = 0,
613 [ C(RESULT_MISS) ] = 0,
614 },
615 },
616 [ C(ITLB) ] = {
617 [ C(OP_READ) ] = {
618 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
619 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
620 },
621 [ C(OP_WRITE) ] = {
622 [ C(RESULT_ACCESS) ] = -1,
623 [ C(RESULT_MISS) ] = -1,
624 },
625 [ C(OP_PREFETCH) ] = {
626 [ C(RESULT_ACCESS) ] = -1,
627 [ C(RESULT_MISS) ] = -1,
628 },
629 },
630 [ C(BPU ) ] = {
631 [ C(OP_READ) ] = {
632 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
633 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
634 },
635 [ C(OP_WRITE) ] = {
636 [ C(RESULT_ACCESS) ] = -1,
637 [ C(RESULT_MISS) ] = -1,
638 },
639 [ C(OP_PREFETCH) ] = {
640 [ C(RESULT_ACCESS) ] = -1,
641 [ C(RESULT_MISS) ] = -1,
642 },
643 },
644 };
645
646 static __initconst const u64 atom_hw_cache_event_ids
647 [PERF_COUNT_HW_CACHE_MAX]
648 [PERF_COUNT_HW_CACHE_OP_MAX]
649 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
650 {
651 [ C(L1D) ] = {
652 [ C(OP_READ) ] = {
653 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
654 [ C(RESULT_MISS) ] = 0,
655 },
656 [ C(OP_WRITE) ] = {
657 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
658 [ C(RESULT_MISS) ] = 0,
659 },
660 [ C(OP_PREFETCH) ] = {
661 [ C(RESULT_ACCESS) ] = 0x0,
662 [ C(RESULT_MISS) ] = 0,
663 },
664 },
665 [ C(L1I ) ] = {
666 [ C(OP_READ) ] = {
667 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
668 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
669 },
670 [ C(OP_WRITE) ] = {
671 [ C(RESULT_ACCESS) ] = -1,
672 [ C(RESULT_MISS) ] = -1,
673 },
674 [ C(OP_PREFETCH) ] = {
675 [ C(RESULT_ACCESS) ] = 0,
676 [ C(RESULT_MISS) ] = 0,
677 },
678 },
679 [ C(LL ) ] = {
680 [ C(OP_READ) ] = {
681 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
682 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
683 },
684 [ C(OP_WRITE) ] = {
685 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
686 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
687 },
688 [ C(OP_PREFETCH) ] = {
689 [ C(RESULT_ACCESS) ] = 0,
690 [ C(RESULT_MISS) ] = 0,
691 },
692 },
693 [ C(DTLB) ] = {
694 [ C(OP_READ) ] = {
695 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
696 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
697 },
698 [ C(OP_WRITE) ] = {
699 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
700 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
701 },
702 [ C(OP_PREFETCH) ] = {
703 [ C(RESULT_ACCESS) ] = 0,
704 [ C(RESULT_MISS) ] = 0,
705 },
706 },
707 [ C(ITLB) ] = {
708 [ C(OP_READ) ] = {
709 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
710 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
711 },
712 [ C(OP_WRITE) ] = {
713 [ C(RESULT_ACCESS) ] = -1,
714 [ C(RESULT_MISS) ] = -1,
715 },
716 [ C(OP_PREFETCH) ] = {
717 [ C(RESULT_ACCESS) ] = -1,
718 [ C(RESULT_MISS) ] = -1,
719 },
720 },
721 [ C(BPU ) ] = {
722 [ C(OP_READ) ] = {
723 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
724 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
725 },
726 [ C(OP_WRITE) ] = {
727 [ C(RESULT_ACCESS) ] = -1,
728 [ C(RESULT_MISS) ] = -1,
729 },
730 [ C(OP_PREFETCH) ] = {
731 [ C(RESULT_ACCESS) ] = -1,
732 [ C(RESULT_MISS) ] = -1,
733 },
734 },
735 };
736
intel_pmu_needs_lbr_smpl(struct perf_event * event)737 static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
738 {
739 /* user explicitly requested branch sampling */
740 if (has_branch_stack(event))
741 return true;
742
743 /* implicit branch sampling to correct PEBS skid */
744 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
745 return true;
746
747 return false;
748 }
749
intel_pmu_disable_all(void)750 static void intel_pmu_disable_all(void)
751 {
752 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
753
754 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
755
756 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
757 intel_pmu_disable_bts();
758
759 intel_pmu_pebs_disable_all();
760 intel_pmu_lbr_disable_all();
761 }
762
intel_pmu_enable_all(int added)763 static void intel_pmu_enable_all(int added)
764 {
765 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
766
767 intel_pmu_pebs_enable_all();
768 intel_pmu_lbr_enable_all();
769 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
770 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
771
772 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
773 struct perf_event *event =
774 cpuc->events[X86_PMC_IDX_FIXED_BTS];
775
776 if (WARN_ON_ONCE(!event))
777 return;
778
779 intel_pmu_enable_bts(event->hw.config);
780 }
781 }
782
783 /*
784 * Workaround for:
785 * Intel Errata AAK100 (model 26)
786 * Intel Errata AAP53 (model 30)
787 * Intel Errata BD53 (model 44)
788 *
789 * The official story:
790 * These chips need to be 'reset' when adding counters by programming the
791 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
792 * in sequence on the same PMC or on different PMCs.
793 *
794 * In practise it appears some of these events do in fact count, and
795 * we need to programm all 4 events.
796 */
intel_pmu_nhm_workaround(void)797 static void intel_pmu_nhm_workaround(void)
798 {
799 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
800 static const unsigned long nhm_magic[4] = {
801 0x4300B5,
802 0x4300D2,
803 0x4300B1,
804 0x4300B1
805 };
806 struct perf_event *event;
807 int i;
808
809 /*
810 * The Errata requires below steps:
811 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
812 * 2) Configure 4 PERFEVTSELx with the magic events and clear
813 * the corresponding PMCx;
814 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
815 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
816 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
817 */
818
819 /*
820 * The real steps we choose are a little different from above.
821 * A) To reduce MSR operations, we don't run step 1) as they
822 * are already cleared before this function is called;
823 * B) Call x86_perf_event_update to save PMCx before configuring
824 * PERFEVTSELx with magic number;
825 * C) With step 5), we do clear only when the PERFEVTSELx is
826 * not used currently.
827 * D) Call x86_perf_event_set_period to restore PMCx;
828 */
829
830 /* We always operate 4 pairs of PERF Counters */
831 for (i = 0; i < 4; i++) {
832 event = cpuc->events[i];
833 if (event)
834 x86_perf_event_update(event);
835 }
836
837 for (i = 0; i < 4; i++) {
838 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
839 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
840 }
841
842 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
843 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
844
845 for (i = 0; i < 4; i++) {
846 event = cpuc->events[i];
847
848 if (event) {
849 x86_perf_event_set_period(event);
850 __x86_pmu_enable_event(&event->hw,
851 ARCH_PERFMON_EVENTSEL_ENABLE);
852 } else
853 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
854 }
855 }
856
intel_pmu_nhm_enable_all(int added)857 static void intel_pmu_nhm_enable_all(int added)
858 {
859 if (added)
860 intel_pmu_nhm_workaround();
861 intel_pmu_enable_all(added);
862 }
863
intel_pmu_get_status(void)864 static inline u64 intel_pmu_get_status(void)
865 {
866 u64 status;
867
868 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
869
870 return status;
871 }
872
intel_pmu_ack_status(u64 ack)873 static inline void intel_pmu_ack_status(u64 ack)
874 {
875 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
876 }
877
intel_pmu_disable_fixed(struct hw_perf_event * hwc)878 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
879 {
880 int idx = hwc->idx - X86_PMC_IDX_FIXED;
881 u64 ctrl_val, mask;
882
883 mask = 0xfULL << (idx * 4);
884
885 rdmsrl(hwc->config_base, ctrl_val);
886 ctrl_val &= ~mask;
887 wrmsrl(hwc->config_base, ctrl_val);
888 }
889
intel_pmu_disable_event(struct perf_event * event)890 static void intel_pmu_disable_event(struct perf_event *event)
891 {
892 struct hw_perf_event *hwc = &event->hw;
893 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
894
895 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
896 intel_pmu_disable_bts();
897 intel_pmu_drain_bts_buffer();
898 return;
899 }
900
901 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
902 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
903
904 /*
905 * must disable before any actual event
906 * because any event may be combined with LBR
907 */
908 if (intel_pmu_needs_lbr_smpl(event))
909 intel_pmu_lbr_disable(event);
910
911 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
912 intel_pmu_disable_fixed(hwc);
913 return;
914 }
915
916 x86_pmu_disable_event(event);
917
918 if (unlikely(event->attr.precise_ip))
919 intel_pmu_pebs_disable(event);
920 }
921
intel_pmu_enable_fixed(struct hw_perf_event * hwc)922 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
923 {
924 int idx = hwc->idx - X86_PMC_IDX_FIXED;
925 u64 ctrl_val, bits, mask;
926
927 /*
928 * Enable IRQ generation (0x8),
929 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
930 * if requested:
931 */
932 bits = 0x8ULL;
933 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
934 bits |= 0x2;
935 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
936 bits |= 0x1;
937
938 /*
939 * ANY bit is supported in v3 and up
940 */
941 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
942 bits |= 0x4;
943
944 bits <<= (idx * 4);
945 mask = 0xfULL << (idx * 4);
946
947 rdmsrl(hwc->config_base, ctrl_val);
948 ctrl_val &= ~mask;
949 ctrl_val |= bits;
950 wrmsrl(hwc->config_base, ctrl_val);
951 }
952
intel_pmu_enable_event(struct perf_event * event)953 static void intel_pmu_enable_event(struct perf_event *event)
954 {
955 struct hw_perf_event *hwc = &event->hw;
956 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
957
958 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
959 if (!__this_cpu_read(cpu_hw_events.enabled))
960 return;
961
962 intel_pmu_enable_bts(hwc->config);
963 return;
964 }
965 /*
966 * must enabled before any actual event
967 * because any event may be combined with LBR
968 */
969 if (intel_pmu_needs_lbr_smpl(event))
970 intel_pmu_lbr_enable(event);
971
972 if (event->attr.exclude_host)
973 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
974 if (event->attr.exclude_guest)
975 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
976
977 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
978 intel_pmu_enable_fixed(hwc);
979 return;
980 }
981
982 if (unlikely(event->attr.precise_ip))
983 intel_pmu_pebs_enable(event);
984
985 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
986 }
987
988 /*
989 * Save and restart an expired event. Called by NMI contexts,
990 * so it has to be careful about preempting normal event ops:
991 */
intel_pmu_save_and_restart(struct perf_event * event)992 int intel_pmu_save_and_restart(struct perf_event *event)
993 {
994 x86_perf_event_update(event);
995 return x86_perf_event_set_period(event);
996 }
997
intel_pmu_reset(void)998 static void intel_pmu_reset(void)
999 {
1000 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1001 unsigned long flags;
1002 int idx;
1003
1004 if (!x86_pmu.num_counters)
1005 return;
1006
1007 local_irq_save(flags);
1008
1009 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1010
1011 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1012 checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
1013 checking_wrmsrl(x86_pmu_event_addr(idx), 0ull);
1014 }
1015 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1016 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1017
1018 if (ds)
1019 ds->bts_index = ds->bts_buffer_base;
1020
1021 local_irq_restore(flags);
1022 }
1023
1024 /*
1025 * This handler is triggered by the local APIC, so the APIC IRQ handling
1026 * rules apply:
1027 */
intel_pmu_handle_irq(struct pt_regs * regs)1028 static int intel_pmu_handle_irq(struct pt_regs *regs)
1029 {
1030 struct perf_sample_data data;
1031 struct cpu_hw_events *cpuc;
1032 int bit, loops;
1033 u64 status;
1034 int handled;
1035
1036 perf_sample_data_init(&data, 0);
1037
1038 cpuc = &__get_cpu_var(cpu_hw_events);
1039
1040 /*
1041 * Some chipsets need to unmask the LVTPC in a particular spot
1042 * inside the nmi handler. As a result, the unmasking was pushed
1043 * into all the nmi handlers.
1044 *
1045 * This handler doesn't seem to have any issues with the unmasking
1046 * so it was left at the top.
1047 */
1048 apic_write(APIC_LVTPC, APIC_DM_NMI);
1049
1050 intel_pmu_disable_all();
1051 handled = intel_pmu_drain_bts_buffer();
1052 status = intel_pmu_get_status();
1053 if (!status) {
1054 intel_pmu_enable_all(0);
1055 return handled;
1056 }
1057
1058 loops = 0;
1059 again:
1060 intel_pmu_ack_status(status);
1061 if (++loops > 100) {
1062 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1063 perf_event_print_debug();
1064 intel_pmu_reset();
1065 goto done;
1066 }
1067
1068 inc_irq_stat(apic_perf_irqs);
1069
1070 intel_pmu_lbr_read();
1071
1072 /*
1073 * PEBS overflow sets bit 62 in the global status register
1074 */
1075 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1076 handled++;
1077 x86_pmu.drain_pebs(regs);
1078 }
1079
1080 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1081 struct perf_event *event = cpuc->events[bit];
1082
1083 handled++;
1084
1085 if (!test_bit(bit, cpuc->active_mask))
1086 continue;
1087
1088 if (!intel_pmu_save_and_restart(event))
1089 continue;
1090
1091 data.period = event->hw.last_period;
1092
1093 if (has_branch_stack(event))
1094 data.br_stack = &cpuc->lbr_stack;
1095
1096 if (perf_event_overflow(event, &data, regs))
1097 x86_pmu_stop(event, 0);
1098 }
1099
1100 /*
1101 * Repeat if there is more work to be done:
1102 */
1103 status = intel_pmu_get_status();
1104 if (status)
1105 goto again;
1106
1107 done:
1108 intel_pmu_enable_all(0);
1109 return handled;
1110 }
1111
1112 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)1113 intel_bts_constraints(struct perf_event *event)
1114 {
1115 struct hw_perf_event *hwc = &event->hw;
1116 unsigned int hw_event, bts_event;
1117
1118 if (event->attr.freq)
1119 return NULL;
1120
1121 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1122 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1123
1124 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1125 return &bts_constraint;
1126
1127 return NULL;
1128 }
1129
intel_try_alt_er(struct perf_event * event,int orig_idx)1130 static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
1131 {
1132 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1133 return false;
1134
1135 if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
1136 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1137 event->hw.config |= 0x01bb;
1138 event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
1139 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1140 } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
1141 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1142 event->hw.config |= 0x01b7;
1143 event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
1144 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1145 }
1146
1147 if (event->hw.extra_reg.idx == orig_idx)
1148 return false;
1149
1150 return true;
1151 }
1152
1153 /*
1154 * manage allocation of shared extra msr for certain events
1155 *
1156 * sharing can be:
1157 * per-cpu: to be shared between the various events on a single PMU
1158 * per-core: per-cpu + shared by HT threads
1159 */
1160 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)1161 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1162 struct perf_event *event,
1163 struct hw_perf_event_extra *reg)
1164 {
1165 struct event_constraint *c = &emptyconstraint;
1166 struct er_account *era;
1167 unsigned long flags;
1168 int orig_idx = reg->idx;
1169
1170 /* already allocated shared msr */
1171 if (reg->alloc)
1172 return NULL; /* call x86_get_event_constraint() */
1173
1174 again:
1175 era = &cpuc->shared_regs->regs[reg->idx];
1176 /*
1177 * we use spin_lock_irqsave() to avoid lockdep issues when
1178 * passing a fake cpuc
1179 */
1180 raw_spin_lock_irqsave(&era->lock, flags);
1181
1182 if (!atomic_read(&era->ref) || era->config == reg->config) {
1183
1184 /* lock in msr value */
1185 era->config = reg->config;
1186 era->reg = reg->reg;
1187
1188 /* one more user */
1189 atomic_inc(&era->ref);
1190
1191 /* no need to reallocate during incremental event scheduling */
1192 reg->alloc = 1;
1193
1194 /*
1195 * need to call x86_get_event_constraint()
1196 * to check if associated event has constraints
1197 */
1198 c = NULL;
1199 } else if (intel_try_alt_er(event, orig_idx)) {
1200 raw_spin_unlock_irqrestore(&era->lock, flags);
1201 goto again;
1202 }
1203 raw_spin_unlock_irqrestore(&era->lock, flags);
1204
1205 return c;
1206 }
1207
1208 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)1209 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1210 struct hw_perf_event_extra *reg)
1211 {
1212 struct er_account *era;
1213
1214 /*
1215 * only put constraint if extra reg was actually
1216 * allocated. Also takes care of event which do
1217 * not use an extra shared reg
1218 */
1219 if (!reg->alloc)
1220 return;
1221
1222 era = &cpuc->shared_regs->regs[reg->idx];
1223
1224 /* one fewer user */
1225 atomic_dec(&era->ref);
1226
1227 /* allocate again next time */
1228 reg->alloc = 0;
1229 }
1230
1231 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)1232 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1233 struct perf_event *event)
1234 {
1235 struct event_constraint *c = NULL, *d;
1236 struct hw_perf_event_extra *xreg, *breg;
1237
1238 xreg = &event->hw.extra_reg;
1239 if (xreg->idx != EXTRA_REG_NONE) {
1240 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1241 if (c == &emptyconstraint)
1242 return c;
1243 }
1244 breg = &event->hw.branch_reg;
1245 if (breg->idx != EXTRA_REG_NONE) {
1246 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1247 if (d == &emptyconstraint) {
1248 __intel_shared_reg_put_constraints(cpuc, xreg);
1249 c = d;
1250 }
1251 }
1252 return c;
1253 }
1254
1255 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)1256 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1257 {
1258 struct event_constraint *c;
1259
1260 if (x86_pmu.event_constraints) {
1261 for_each_event_constraint(c, x86_pmu.event_constraints) {
1262 if ((event->hw.config & c->cmask) == c->code)
1263 return c;
1264 }
1265 }
1266
1267 return &unconstrained;
1268 }
1269
1270 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)1271 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1272 {
1273 struct event_constraint *c;
1274
1275 c = intel_bts_constraints(event);
1276 if (c)
1277 return c;
1278
1279 c = intel_pebs_constraints(event);
1280 if (c)
1281 return c;
1282
1283 c = intel_shared_regs_constraints(cpuc, event);
1284 if (c)
1285 return c;
1286
1287 return x86_get_event_constraints(cpuc, event);
1288 }
1289
1290 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)1291 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1292 struct perf_event *event)
1293 {
1294 struct hw_perf_event_extra *reg;
1295
1296 reg = &event->hw.extra_reg;
1297 if (reg->idx != EXTRA_REG_NONE)
1298 __intel_shared_reg_put_constraints(cpuc, reg);
1299
1300 reg = &event->hw.branch_reg;
1301 if (reg->idx != EXTRA_REG_NONE)
1302 __intel_shared_reg_put_constraints(cpuc, reg);
1303 }
1304
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)1305 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1306 struct perf_event *event)
1307 {
1308 intel_put_shared_regs_event_constraints(cpuc, event);
1309 }
1310
intel_pmu_hw_config(struct perf_event * event)1311 static int intel_pmu_hw_config(struct perf_event *event)
1312 {
1313 int ret = x86_pmu_hw_config(event);
1314
1315 if (ret)
1316 return ret;
1317
1318 if (event->attr.precise_ip &&
1319 (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1320 /*
1321 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1322 * (0x003c) so that we can use it with PEBS.
1323 *
1324 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1325 * PEBS capable. However we can use INST_RETIRED.ANY_P
1326 * (0x00c0), which is a PEBS capable event, to get the same
1327 * count.
1328 *
1329 * INST_RETIRED.ANY_P counts the number of cycles that retires
1330 * CNTMASK instructions. By setting CNTMASK to a value (16)
1331 * larger than the maximum number of instructions that can be
1332 * retired per cycle (4) and then inverting the condition, we
1333 * count all cycles that retire 16 or less instructions, which
1334 * is every cycle.
1335 *
1336 * Thereby we gain a PEBS capable cycle counter.
1337 */
1338 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1339
1340
1341 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1342 event->hw.config = alt_config;
1343 }
1344
1345 if (intel_pmu_needs_lbr_smpl(event)) {
1346 ret = intel_pmu_setup_lbr_filter(event);
1347 if (ret)
1348 return ret;
1349 }
1350
1351 if (event->attr.type != PERF_TYPE_RAW)
1352 return 0;
1353
1354 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1355 return 0;
1356
1357 if (x86_pmu.version < 3)
1358 return -EINVAL;
1359
1360 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1361 return -EACCES;
1362
1363 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1364
1365 return 0;
1366 }
1367
perf_guest_get_msrs(int * nr)1368 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1369 {
1370 if (x86_pmu.guest_get_msrs)
1371 return x86_pmu.guest_get_msrs(nr);
1372 *nr = 0;
1373 return NULL;
1374 }
1375 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1376
intel_guest_get_msrs(int * nr)1377 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1378 {
1379 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1380 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1381
1382 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1383 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1384 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1385
1386 *nr = 1;
1387 return arr;
1388 }
1389
core_guest_get_msrs(int * nr)1390 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1391 {
1392 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1393 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1394 int idx;
1395
1396 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1397 struct perf_event *event = cpuc->events[idx];
1398
1399 arr[idx].msr = x86_pmu_config_addr(idx);
1400 arr[idx].host = arr[idx].guest = 0;
1401
1402 if (!test_bit(idx, cpuc->active_mask))
1403 continue;
1404
1405 arr[idx].host = arr[idx].guest =
1406 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1407
1408 if (event->attr.exclude_host)
1409 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1410 else if (event->attr.exclude_guest)
1411 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1412 }
1413
1414 *nr = x86_pmu.num_counters;
1415 return arr;
1416 }
1417
core_pmu_enable_event(struct perf_event * event)1418 static void core_pmu_enable_event(struct perf_event *event)
1419 {
1420 if (!event->attr.exclude_host)
1421 x86_pmu_enable_event(event);
1422 }
1423
core_pmu_enable_all(int added)1424 static void core_pmu_enable_all(int added)
1425 {
1426 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1427 int idx;
1428
1429 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1430 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1431
1432 if (!test_bit(idx, cpuc->active_mask) ||
1433 cpuc->events[idx]->attr.exclude_host)
1434 continue;
1435
1436 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1437 }
1438 }
1439
1440 PMU_FORMAT_ATTR(event, "config:0-7" );
1441 PMU_FORMAT_ATTR(umask, "config:8-15" );
1442 PMU_FORMAT_ATTR(edge, "config:18" );
1443 PMU_FORMAT_ATTR(pc, "config:19" );
1444 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1445 PMU_FORMAT_ATTR(inv, "config:23" );
1446 PMU_FORMAT_ATTR(cmask, "config:24-31" );
1447
1448 static struct attribute *intel_arch_formats_attr[] = {
1449 &format_attr_event.attr,
1450 &format_attr_umask.attr,
1451 &format_attr_edge.attr,
1452 &format_attr_pc.attr,
1453 &format_attr_inv.attr,
1454 &format_attr_cmask.attr,
1455 NULL,
1456 };
1457
1458 static __initconst const struct x86_pmu core_pmu = {
1459 .name = "core",
1460 .handle_irq = x86_pmu_handle_irq,
1461 .disable_all = x86_pmu_disable_all,
1462 .enable_all = core_pmu_enable_all,
1463 .enable = core_pmu_enable_event,
1464 .disable = x86_pmu_disable_event,
1465 .hw_config = x86_pmu_hw_config,
1466 .schedule_events = x86_schedule_events,
1467 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1468 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1469 .event_map = intel_pmu_event_map,
1470 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1471 .apic = 1,
1472 /*
1473 * Intel PMCs cannot be accessed sanely above 32 bit width,
1474 * so we install an artificial 1<<31 period regardless of
1475 * the generic event period:
1476 */
1477 .max_period = (1ULL << 31) - 1,
1478 .get_event_constraints = intel_get_event_constraints,
1479 .put_event_constraints = intel_put_event_constraints,
1480 .event_constraints = intel_core_event_constraints,
1481 .guest_get_msrs = core_guest_get_msrs,
1482 .format_attrs = intel_arch_formats_attr,
1483 };
1484
allocate_shared_regs(int cpu)1485 struct intel_shared_regs *allocate_shared_regs(int cpu)
1486 {
1487 struct intel_shared_regs *regs;
1488 int i;
1489
1490 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1491 GFP_KERNEL, cpu_to_node(cpu));
1492 if (regs) {
1493 /*
1494 * initialize the locks to keep lockdep happy
1495 */
1496 for (i = 0; i < EXTRA_REG_MAX; i++)
1497 raw_spin_lock_init(®s->regs[i].lock);
1498
1499 regs->core_id = -1;
1500 }
1501 return regs;
1502 }
1503
intel_pmu_cpu_prepare(int cpu)1504 static int intel_pmu_cpu_prepare(int cpu)
1505 {
1506 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1507
1508 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
1509 return NOTIFY_OK;
1510
1511 cpuc->shared_regs = allocate_shared_regs(cpu);
1512 if (!cpuc->shared_regs)
1513 return NOTIFY_BAD;
1514
1515 return NOTIFY_OK;
1516 }
1517
intel_pmu_cpu_starting(int cpu)1518 static void intel_pmu_cpu_starting(int cpu)
1519 {
1520 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1521 int core_id = topology_core_id(cpu);
1522 int i;
1523
1524 init_debug_store_on_cpu(cpu);
1525 /*
1526 * Deal with CPUs that don't clear their LBRs on power-up.
1527 */
1528 intel_pmu_lbr_reset();
1529
1530 cpuc->lbr_sel = NULL;
1531
1532 if (!cpuc->shared_regs)
1533 return;
1534
1535 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1536 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1537 struct intel_shared_regs *pc;
1538
1539 pc = per_cpu(cpu_hw_events, i).shared_regs;
1540 if (pc && pc->core_id == core_id) {
1541 cpuc->kfree_on_online = cpuc->shared_regs;
1542 cpuc->shared_regs = pc;
1543 break;
1544 }
1545 }
1546 cpuc->shared_regs->core_id = core_id;
1547 cpuc->shared_regs->refcnt++;
1548 }
1549
1550 if (x86_pmu.lbr_sel_map)
1551 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
1552 }
1553
intel_pmu_cpu_dying(int cpu)1554 static void intel_pmu_cpu_dying(int cpu)
1555 {
1556 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1557 struct intel_shared_regs *pc;
1558
1559 pc = cpuc->shared_regs;
1560 if (pc) {
1561 if (pc->core_id == -1 || --pc->refcnt == 0)
1562 kfree(pc);
1563 cpuc->shared_regs = NULL;
1564 }
1565
1566 fini_debug_store_on_cpu(cpu);
1567 }
1568
intel_pmu_flush_branch_stack(void)1569 static void intel_pmu_flush_branch_stack(void)
1570 {
1571 /*
1572 * Intel LBR does not tag entries with the
1573 * PID of the current task, then we need to
1574 * flush it on ctxsw
1575 * For now, we simply reset it
1576 */
1577 if (x86_pmu.lbr_nr)
1578 intel_pmu_lbr_reset();
1579 }
1580
1581 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1582
1583 static struct attribute *intel_arch3_formats_attr[] = {
1584 &format_attr_event.attr,
1585 &format_attr_umask.attr,
1586 &format_attr_edge.attr,
1587 &format_attr_pc.attr,
1588 &format_attr_any.attr,
1589 &format_attr_inv.attr,
1590 &format_attr_cmask.attr,
1591
1592 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
1593 NULL,
1594 };
1595
1596 static __initconst const struct x86_pmu intel_pmu = {
1597 .name = "Intel",
1598 .handle_irq = intel_pmu_handle_irq,
1599 .disable_all = intel_pmu_disable_all,
1600 .enable_all = intel_pmu_enable_all,
1601 .enable = intel_pmu_enable_event,
1602 .disable = intel_pmu_disable_event,
1603 .hw_config = intel_pmu_hw_config,
1604 .schedule_events = x86_schedule_events,
1605 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1606 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1607 .event_map = intel_pmu_event_map,
1608 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1609 .apic = 1,
1610 /*
1611 * Intel PMCs cannot be accessed sanely above 32 bit width,
1612 * so we install an artificial 1<<31 period regardless of
1613 * the generic event period:
1614 */
1615 .max_period = (1ULL << 31) - 1,
1616 .get_event_constraints = intel_get_event_constraints,
1617 .put_event_constraints = intel_put_event_constraints,
1618
1619 .format_attrs = intel_arch3_formats_attr,
1620
1621 .cpu_prepare = intel_pmu_cpu_prepare,
1622 .cpu_starting = intel_pmu_cpu_starting,
1623 .cpu_dying = intel_pmu_cpu_dying,
1624 .guest_get_msrs = intel_guest_get_msrs,
1625 .flush_branch_stack = intel_pmu_flush_branch_stack,
1626 };
1627
intel_clovertown_quirk(void)1628 static __init void intel_clovertown_quirk(void)
1629 {
1630 /*
1631 * PEBS is unreliable due to:
1632 *
1633 * AJ67 - PEBS may experience CPL leaks
1634 * AJ68 - PEBS PMI may be delayed by one event
1635 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1636 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1637 *
1638 * AJ67 could be worked around by restricting the OS/USR flags.
1639 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1640 *
1641 * AJ106 could possibly be worked around by not allowing LBR
1642 * usage from PEBS, including the fixup.
1643 * AJ68 could possibly be worked around by always programming
1644 * a pebs_event_reset[0] value and coping with the lost events.
1645 *
1646 * But taken together it might just make sense to not enable PEBS on
1647 * these chips.
1648 */
1649 printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
1650 x86_pmu.pebs = 0;
1651 x86_pmu.pebs_constraints = NULL;
1652 }
1653
intel_sandybridge_quirk(void)1654 static __init void intel_sandybridge_quirk(void)
1655 {
1656 printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
1657 x86_pmu.pebs = 0;
1658 x86_pmu.pebs_constraints = NULL;
1659 }
1660
1661 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1662 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1663 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1664 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
1665 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
1666 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
1667 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
1668 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
1669 };
1670
intel_arch_events_quirk(void)1671 static __init void intel_arch_events_quirk(void)
1672 {
1673 int bit;
1674
1675 /* disable event that reported as not presend by cpuid */
1676 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
1677 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
1678 printk(KERN_WARNING "CPUID marked event: \'%s\' unavailable\n",
1679 intel_arch_events_map[bit].name);
1680 }
1681 }
1682
intel_nehalem_quirk(void)1683 static __init void intel_nehalem_quirk(void)
1684 {
1685 union cpuid10_ebx ebx;
1686
1687 ebx.full = x86_pmu.events_maskl;
1688 if (ebx.split.no_branch_misses_retired) {
1689 /*
1690 * Erratum AAJ80 detected, we work it around by using
1691 * the BR_MISP_EXEC.ANY event. This will over-count
1692 * branch-misses, but it's still much better than the
1693 * architectural event which is often completely bogus:
1694 */
1695 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1696 ebx.split.no_branch_misses_retired = 0;
1697 x86_pmu.events_maskl = ebx.full;
1698 printk(KERN_INFO "CPU erratum AAJ80 worked around\n");
1699 }
1700 }
1701
intel_pmu_init(void)1702 __init int intel_pmu_init(void)
1703 {
1704 union cpuid10_edx edx;
1705 union cpuid10_eax eax;
1706 union cpuid10_ebx ebx;
1707 unsigned int unused;
1708 int version;
1709
1710 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
1711 switch (boot_cpu_data.x86) {
1712 case 0x6:
1713 return p6_pmu_init();
1714 case 0xf:
1715 return p4_pmu_init();
1716 }
1717 return -ENODEV;
1718 }
1719
1720 /*
1721 * Check whether the Architectural PerfMon supports
1722 * Branch Misses Retired hw_event or not.
1723 */
1724 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
1725 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
1726 return -ENODEV;
1727
1728 version = eax.split.version_id;
1729 if (version < 2)
1730 x86_pmu = core_pmu;
1731 else
1732 x86_pmu = intel_pmu;
1733
1734 x86_pmu.version = version;
1735 x86_pmu.num_counters = eax.split.num_counters;
1736 x86_pmu.cntval_bits = eax.split.bit_width;
1737 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
1738
1739 x86_pmu.events_maskl = ebx.full;
1740 x86_pmu.events_mask_len = eax.split.mask_length;
1741
1742 /*
1743 * Quirk: v2 perfmon does not report fixed-purpose events, so
1744 * assume at least 3 events:
1745 */
1746 if (version > 1)
1747 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
1748
1749 /*
1750 * v2 and above have a perf capabilities MSR
1751 */
1752 if (version > 1) {
1753 u64 capabilities;
1754
1755 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
1756 x86_pmu.intel_cap.capabilities = capabilities;
1757 }
1758
1759 intel_ds_init();
1760
1761 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
1762
1763 /*
1764 * Install the hw-cache-events table:
1765 */
1766 switch (boot_cpu_data.x86_model) {
1767 case 14: /* 65 nm core solo/duo, "Yonah" */
1768 pr_cont("Core events, ");
1769 break;
1770
1771 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1772 x86_add_quirk(intel_clovertown_quirk);
1773 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1774 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1775 case 29: /* six-core 45 nm xeon "Dunnington" */
1776 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1777 sizeof(hw_cache_event_ids));
1778
1779 intel_pmu_lbr_init_core();
1780
1781 x86_pmu.event_constraints = intel_core2_event_constraints;
1782 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
1783 pr_cont("Core2 events, ");
1784 break;
1785
1786 case 26: /* 45 nm nehalem, "Bloomfield" */
1787 case 30: /* 45 nm nehalem, "Lynnfield" */
1788 case 46: /* 45 nm nehalem-ex, "Beckton" */
1789 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1790 sizeof(hw_cache_event_ids));
1791 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1792 sizeof(hw_cache_extra_regs));
1793
1794 intel_pmu_lbr_init_nhm();
1795
1796 x86_pmu.event_constraints = intel_nehalem_event_constraints;
1797 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
1798 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
1799 x86_pmu.extra_regs = intel_nehalem_extra_regs;
1800
1801 /* UOPS_ISSUED.STALLED_CYCLES */
1802 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
1803 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
1804 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
1805 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
1806 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
1807
1808 x86_add_quirk(intel_nehalem_quirk);
1809
1810 pr_cont("Nehalem events, ");
1811 break;
1812
1813 case 28: /* Atom */
1814 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1815 sizeof(hw_cache_event_ids));
1816
1817 intel_pmu_lbr_init_atom();
1818
1819 x86_pmu.event_constraints = intel_gen_event_constraints;
1820 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
1821 pr_cont("Atom events, ");
1822 break;
1823
1824 case 37: /* 32 nm nehalem, "Clarkdale" */
1825 case 44: /* 32 nm nehalem, "Gulftown" */
1826 case 47: /* 32 nm Xeon E7 */
1827 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
1828 sizeof(hw_cache_event_ids));
1829 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1830 sizeof(hw_cache_extra_regs));
1831
1832 intel_pmu_lbr_init_nhm();
1833
1834 x86_pmu.event_constraints = intel_westmere_event_constraints;
1835 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
1836 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
1837 x86_pmu.extra_regs = intel_westmere_extra_regs;
1838 x86_pmu.er_flags |= ERF_HAS_RSP_1;
1839
1840 /* UOPS_ISSUED.STALLED_CYCLES */
1841 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
1842 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
1843 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
1844 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
1845 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
1846
1847 pr_cont("Westmere events, ");
1848 break;
1849
1850 case 42: /* SandyBridge */
1851 x86_add_quirk(intel_sandybridge_quirk);
1852 case 45: /* SandyBridge, "Romely-EP" */
1853 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
1854 sizeof(hw_cache_event_ids));
1855
1856 intel_pmu_lbr_init_snb();
1857
1858 x86_pmu.event_constraints = intel_snb_event_constraints;
1859 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
1860 if (boot_cpu_data.x86_model == 45)
1861 x86_pmu.extra_regs = intel_snbep_extra_regs;
1862 else
1863 x86_pmu.extra_regs = intel_snb_extra_regs;
1864 /* all extra regs are per-cpu when HT is on */
1865 x86_pmu.er_flags |= ERF_HAS_RSP_1;
1866 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
1867
1868 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
1869 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
1870 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
1871 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
1872 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
1873 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
1874
1875 pr_cont("SandyBridge events, ");
1876 break;
1877
1878 default:
1879 switch (x86_pmu.version) {
1880 case 1:
1881 x86_pmu.event_constraints = intel_v1_event_constraints;
1882 pr_cont("generic architected perfmon v1, ");
1883 break;
1884 default:
1885 /*
1886 * default constraints for v2 and up
1887 */
1888 x86_pmu.event_constraints = intel_gen_event_constraints;
1889 pr_cont("generic architected perfmon, ");
1890 break;
1891 }
1892 }
1893
1894 return 0;
1895 }
1896