1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #ifndef _IXGBE_H_
29 #define _IXGBE_H_
30
31 #include <linux/bitops.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/cpumask.h>
36 #include <linux/aer.h>
37 #include <linux/if_vlan.h>
38
39 #include "ixgbe_type.h"
40 #include "ixgbe_common.h"
41 #include "ixgbe_dcb.h"
42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
43 #define IXGBE_FCOE
44 #include "ixgbe_fcoe.h"
45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
46 #ifdef CONFIG_IXGBE_DCA
47 #include <linux/dca.h>
48 #endif
49
50 /* common prefix used by pr_<> macros */
51 #undef pr_fmt
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
53
54 /* TX/RX descriptor defines */
55 #define IXGBE_DEFAULT_TXD 512
56 #define IXGBE_DEFAULT_TX_WORK 256
57 #define IXGBE_MAX_TXD 4096
58 #define IXGBE_MIN_TXD 64
59
60 #define IXGBE_DEFAULT_RXD 512
61 #define IXGBE_MAX_RXD 4096
62 #define IXGBE_MIN_RXD 64
63
64 /* flow control */
65 #define IXGBE_MIN_FCRTL 0x40
66 #define IXGBE_MAX_FCRTL 0x7FF80
67 #define IXGBE_MIN_FCRTH 0x600
68 #define IXGBE_MAX_FCRTH 0x7FFF0
69 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
70 #define IXGBE_MIN_FCPAUSE 0
71 #define IXGBE_MAX_FCPAUSE 0xFFFF
72
73 /* Supported Rx Buffer Sizes */
74 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */
75 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
76
77 /*
78 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
79 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
80 * this adds up to 512 bytes of extra data meaning the smallest allocation
81 * we could have is 1K.
82 * i.e. RXBUFFER_512 --> size-1024 slab
83 */
84 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
85
86 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
87
88 /* How many Rx Buffers do we bundle into one write to the hardware ? */
89 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
90
91 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
92 #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
93 #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
94 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
95 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
96 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
97 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
98 #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
99 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
100 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
101 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
102 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
103
104 #define IXGBE_MAX_VF_MC_ENTRIES 30
105 #define IXGBE_MAX_VF_FUNCTIONS 64
106 #define IXGBE_MAX_VFTA_ENTRIES 128
107 #define MAX_EMULATION_MAC_ADDRS 16
108 #define IXGBE_MAX_PF_MACVLANS 15
109 #define VMDQ_P(p) ((p) + adapter->num_vfs)
110 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
111 #define IXGBE_X540_VF_DEVICE_ID 0x1515
112
113 struct vf_data_storage {
114 unsigned char vf_mac_addresses[ETH_ALEN];
115 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
116 u16 num_vf_mc_hashes;
117 u16 default_vf_vlan_id;
118 u16 vlans_enabled;
119 bool clear_to_send;
120 bool pf_set_mac;
121 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
122 u16 pf_qos;
123 u16 tx_rate;
124 u16 vlan_count;
125 u8 spoofchk_enabled;
126 struct pci_dev *vfdev;
127 };
128
129 struct vf_macvlans {
130 struct list_head l;
131 int vf;
132 int rar_entry;
133 bool free;
134 bool is_macvlan;
135 u8 vf_macvlan[ETH_ALEN];
136 };
137
138 #define IXGBE_MAX_TXD_PWR 14
139 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
140
141 /* Tx Descriptors needed, worst case */
142 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
143 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
144
145 /* wrapper around a pointer to a socket buffer,
146 * so a DMA handle can be stored along with the buffer */
147 struct ixgbe_tx_buffer {
148 union ixgbe_adv_tx_desc *next_to_watch;
149 unsigned long time_stamp;
150 struct sk_buff *skb;
151 unsigned int bytecount;
152 unsigned short gso_segs;
153 __be16 protocol;
154 DEFINE_DMA_UNMAP_ADDR(dma);
155 DEFINE_DMA_UNMAP_LEN(len);
156 u32 tx_flags;
157 };
158
159 struct ixgbe_rx_buffer {
160 struct sk_buff *skb;
161 dma_addr_t dma;
162 struct page *page;
163 unsigned int page_offset;
164 };
165
166 struct ixgbe_queue_stats {
167 u64 packets;
168 u64 bytes;
169 };
170
171 struct ixgbe_tx_queue_stats {
172 u64 restart_queue;
173 u64 tx_busy;
174 u64 tx_done_old;
175 };
176
177 struct ixgbe_rx_queue_stats {
178 u64 rsc_count;
179 u64 rsc_flush;
180 u64 non_eop_descs;
181 u64 alloc_rx_page_failed;
182 u64 alloc_rx_buff_failed;
183 u64 csum_err;
184 };
185
186 enum ixgbe_ring_state_t {
187 __IXGBE_TX_FDIR_INIT_DONE,
188 __IXGBE_TX_DETECT_HANG,
189 __IXGBE_HANG_CHECK_ARMED,
190 __IXGBE_RX_RSC_ENABLED,
191 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
192 __IXGBE_RX_FCOE,
193 };
194
195 #define check_for_tx_hang(ring) \
196 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
197 #define set_check_for_tx_hang(ring) \
198 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
199 #define clear_check_for_tx_hang(ring) \
200 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
201 #define ring_is_rsc_enabled(ring) \
202 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
203 #define set_ring_rsc_enabled(ring) \
204 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
205 #define clear_ring_rsc_enabled(ring) \
206 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
207 struct ixgbe_ring {
208 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
209 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
210 struct net_device *netdev; /* netdev ring belongs to */
211 struct device *dev; /* device for DMA mapping */
212 void *desc; /* descriptor ring memory */
213 union {
214 struct ixgbe_tx_buffer *tx_buffer_info;
215 struct ixgbe_rx_buffer *rx_buffer_info;
216 };
217 unsigned long state;
218 u8 __iomem *tail;
219 dma_addr_t dma; /* phys. address of descriptor ring */
220 unsigned int size; /* length in bytes */
221
222 u16 count; /* amount of descriptors */
223
224 u8 queue_index; /* needed for multiqueue queue management */
225 u8 reg_idx; /* holds the special value that gets
226 * the hardware register offset
227 * associated with this ring, which is
228 * different for DCB and RSS modes
229 */
230 u16 next_to_use;
231 u16 next_to_clean;
232
233 union {
234 u16 next_to_alloc;
235 struct {
236 u8 atr_sample_rate;
237 u8 atr_count;
238 };
239 };
240
241 u8 dcb_tc;
242 struct ixgbe_queue_stats stats;
243 struct u64_stats_sync syncp;
244 union {
245 struct ixgbe_tx_queue_stats tx_stats;
246 struct ixgbe_rx_queue_stats rx_stats;
247 };
248 } ____cacheline_internodealigned_in_smp;
249
250 enum ixgbe_ring_f_enum {
251 RING_F_NONE = 0,
252 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
253 RING_F_RSS,
254 RING_F_FDIR,
255 #ifdef IXGBE_FCOE
256 RING_F_FCOE,
257 #endif /* IXGBE_FCOE */
258
259 RING_F_ARRAY_SIZE /* must be last in enum set */
260 };
261
262 #define IXGBE_MAX_RSS_INDICES 16
263 #define IXGBE_MAX_VMDQ_INDICES 64
264 #define IXGBE_MAX_FDIR_INDICES 64
265 #ifdef IXGBE_FCOE
266 #define IXGBE_MAX_FCOE_INDICES 8
267 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
268 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
269 #else
270 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
271 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
272 #endif /* IXGBE_FCOE */
273 struct ixgbe_ring_feature {
274 int indices;
275 int mask;
276 } ____cacheline_internodealigned_in_smp;
277
278 /*
279 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
280 * this is twice the size of a half page we need to double the page order
281 * for FCoE enabled Rx queues.
282 */
283 #if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
ixgbe_rx_pg_order(struct ixgbe_ring * ring)284 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
285 {
286 return test_bit(__IXGBE_RX_FCOE, &ring->state) ? 1 : 0;
287 }
288 #else
289 #define ixgbe_rx_pg_order(_ring) 0
290 #endif
291 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
292 #define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
293
294 struct ixgbe_ring_container {
295 struct ixgbe_ring *ring; /* pointer to linked list of rings */
296 unsigned int total_bytes; /* total bytes processed this int */
297 unsigned int total_packets; /* total packets processed this int */
298 u16 work_limit; /* total work allowed per interrupt */
299 u8 count; /* total number of rings in vector */
300 u8 itr; /* current ITR setting for ring */
301 };
302
303 /* iterator for handling rings in ring container */
304 #define ixgbe_for_each_ring(pos, head) \
305 for (pos = (head).ring; pos != NULL; pos = pos->next)
306
307 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
308 ? 8 : 1)
309 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
310
311 /* MAX_MSIX_Q_VECTORS of these are allocated,
312 * but we only use one per queue-specific vector.
313 */
314 struct ixgbe_q_vector {
315 struct ixgbe_adapter *adapter;
316 #ifdef CONFIG_IXGBE_DCA
317 int cpu; /* CPU for DCA */
318 #endif
319 u16 v_idx; /* index of q_vector within array, also used for
320 * finding the bit in EICR and friends that
321 * represents the vector for this ring */
322 u16 itr; /* Interrupt throttle rate written to EITR */
323 struct ixgbe_ring_container rx, tx;
324
325 struct napi_struct napi;
326 cpumask_t affinity_mask;
327 int numa_node;
328 struct rcu_head rcu; /* to avoid race with update stats on free */
329 char name[IFNAMSIZ + 9];
330
331 /* for dynamic allocation of rings associated with this q_vector */
332 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
333 };
334
335 /*
336 * microsecond values for various ITR rates shifted by 2 to fit itr register
337 * with the first 3 bits reserved 0
338 */
339 #define IXGBE_MIN_RSC_ITR 24
340 #define IXGBE_100K_ITR 40
341 #define IXGBE_20K_ITR 200
342 #define IXGBE_10K_ITR 400
343 #define IXGBE_8K_ITR 500
344
345 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
ixgbe_test_staterr(union ixgbe_adv_rx_desc * rx_desc,const u32 stat_err_bits)346 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
347 const u32 stat_err_bits)
348 {
349 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
350 }
351
ixgbe_desc_unused(struct ixgbe_ring * ring)352 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
353 {
354 u16 ntc = ring->next_to_clean;
355 u16 ntu = ring->next_to_use;
356
357 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
358 }
359
360 #define IXGBE_RX_DESC(R, i) \
361 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
362 #define IXGBE_TX_DESC(R, i) \
363 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
364 #define IXGBE_TX_CTXTDESC(R, i) \
365 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
366
367 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
368 #ifdef IXGBE_FCOE
369 /* Use 3K as the baby jumbo frame size for FCoE */
370 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
371 #endif /* IXGBE_FCOE */
372
373 #define OTHER_VECTOR 1
374 #define NON_Q_VECTORS (OTHER_VECTOR)
375
376 #define MAX_MSIX_VECTORS_82599 64
377 #define MAX_MSIX_Q_VECTORS_82599 64
378 #define MAX_MSIX_VECTORS_82598 18
379 #define MAX_MSIX_Q_VECTORS_82598 16
380
381 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
382 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
383
384 #define MIN_MSIX_Q_VECTORS 1
385 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
386
387 /* default to trying for four seconds */
388 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
389
390 /* board specific private data structure */
391 struct ixgbe_adapter {
392 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
393 /* OS defined structs */
394 struct net_device *netdev;
395 struct pci_dev *pdev;
396
397 unsigned long state;
398
399 /* Some features need tri-state capability,
400 * thus the additional *_CAPABLE flags.
401 */
402 u32 flags;
403 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
404 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
405 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
406 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
407 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
408 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
409 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
410 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
411 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
412 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
413 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
414 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
415 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
416 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
417 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
418 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
419 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
420 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
421 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
422 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
423 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
424 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
425 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
426 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
427 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
428 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
429
430 u32 flags2;
431 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
432 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
433 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
434 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
435 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
436 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
437 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
438 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
439 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
440 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
441
442 /* Tx fast path data */
443 int num_tx_queues;
444 u16 tx_itr_setting;
445 u16 tx_work_limit;
446
447 /* Rx fast path data */
448 int num_rx_queues;
449 u16 rx_itr_setting;
450
451 /* TX */
452 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
453
454 u64 restart_queue;
455 u64 lsc_int;
456 u32 tx_timeout_count;
457
458 /* RX */
459 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
460 int num_rx_pools; /* == num_rx_queues in 82598 */
461 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
462 u64 hw_csum_rx_error;
463 u64 hw_rx_no_dma_resources;
464 u64 rsc_total_count;
465 u64 rsc_total_flush;
466 u64 non_eop_descs;
467 u32 alloc_rx_page_failed;
468 u32 alloc_rx_buff_failed;
469
470 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
471
472 /* DCB parameters */
473 struct ieee_pfc *ixgbe_ieee_pfc;
474 struct ieee_ets *ixgbe_ieee_ets;
475 struct ixgbe_dcb_config dcb_cfg;
476 struct ixgbe_dcb_config temp_dcb_cfg;
477 u8 dcb_set_bitmap;
478 u8 dcbx_cap;
479 enum ixgbe_fc_mode last_lfc_mode;
480
481 int num_msix_vectors;
482 int max_msix_q_vectors; /* true count of q_vectors for device */
483 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
484 struct msix_entry *msix_entries;
485
486 u32 test_icr;
487 struct ixgbe_ring test_tx_ring;
488 struct ixgbe_ring test_rx_ring;
489
490 /* structs defined in ixgbe_hw.h */
491 struct ixgbe_hw hw;
492 u16 msg_enable;
493 struct ixgbe_hw_stats stats;
494
495 u64 tx_busy;
496 unsigned int tx_ring_count;
497 unsigned int rx_ring_count;
498
499 u32 link_speed;
500 bool link_up;
501 unsigned long link_check_timeout;
502
503 struct timer_list service_timer;
504 struct work_struct service_task;
505
506 struct hlist_head fdir_filter_list;
507 unsigned long fdir_overflow; /* number of times ATR was backed off */
508 union ixgbe_atr_input fdir_mask;
509 int fdir_filter_count;
510 u32 fdir_pballoc;
511 u32 atr_sample_rate;
512 spinlock_t fdir_perfect_lock;
513
514 #ifdef IXGBE_FCOE
515 struct ixgbe_fcoe fcoe;
516 #endif /* IXGBE_FCOE */
517 u32 wol;
518
519 u16 bd_number;
520
521 u16 eeprom_verh;
522 u16 eeprom_verl;
523 u16 eeprom_cap;
524
525 u32 interrupt_event;
526 u32 led_reg;
527
528 /* SR-IOV */
529 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
530 unsigned int num_vfs;
531 struct vf_data_storage *vfinfo;
532 int vf_rate_link_speed;
533 struct vf_macvlans vf_mvs;
534 struct vf_macvlans *mv_list;
535
536 u32 timer_event_accumulator;
537 u32 vferr_refcount;
538 };
539
540 struct ixgbe_fdir_filter {
541 struct hlist_node fdir_node;
542 union ixgbe_atr_input filter;
543 u16 sw_idx;
544 u16 action;
545 };
546
547 enum ixgbe_state_t {
548 __IXGBE_TESTING,
549 __IXGBE_RESETTING,
550 __IXGBE_DOWN,
551 __IXGBE_SERVICE_SCHED,
552 __IXGBE_IN_SFP_INIT,
553 };
554
555 struct ixgbe_cb {
556 union { /* Union defining head/tail partner */
557 struct sk_buff *head;
558 struct sk_buff *tail;
559 };
560 dma_addr_t dma;
561 u16 append_cnt;
562 bool page_released;
563 };
564 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
565
566 enum ixgbe_boards {
567 board_82598,
568 board_82599,
569 board_X540,
570 };
571
572 extern struct ixgbe_info ixgbe_82598_info;
573 extern struct ixgbe_info ixgbe_82599_info;
574 extern struct ixgbe_info ixgbe_X540_info;
575 #ifdef CONFIG_IXGBE_DCB
576 extern const struct dcbnl_rtnl_ops dcbnl_ops;
577 #endif
578
579 extern char ixgbe_driver_name[];
580 extern const char ixgbe_driver_version[];
581 #ifdef IXGBE_FCOE
582 extern char ixgbe_default_device_descr[];
583 #endif /* IXGBE_FCOE */
584
585 extern void ixgbe_up(struct ixgbe_adapter *adapter);
586 extern void ixgbe_down(struct ixgbe_adapter *adapter);
587 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
588 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
589 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
590 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
591 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
592 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
593 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
594 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
595 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
596 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
597 struct ixgbe_ring *);
598 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
599 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
600 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
601 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
602 struct ixgbe_adapter *,
603 struct ixgbe_ring *);
604 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
605 struct ixgbe_tx_buffer *);
606 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
607 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
608 extern int ixgbe_poll(struct napi_struct *napi, int budget);
609 extern int ethtool_ioctl(struct ifreq *ifr);
610 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
611 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
612 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
613 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
614 union ixgbe_atr_hash_dword input,
615 union ixgbe_atr_hash_dword common,
616 u8 queue);
617 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
618 union ixgbe_atr_input *input_mask);
619 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
620 union ixgbe_atr_input *input,
621 u16 soft_id, u8 queue);
622 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
623 union ixgbe_atr_input *input,
624 u16 soft_id);
625 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
626 union ixgbe_atr_input *mask);
627 extern void ixgbe_set_rx_mode(struct net_device *netdev);
628 #ifdef CONFIG_IXGBE_DCB
629 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
630 #endif
631 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
632 extern void ixgbe_do_reset(struct net_device *netdev);
633 #ifdef IXGBE_FCOE
634 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
635 extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
636 struct ixgbe_tx_buffer *first,
637 u8 *hdr_len);
638 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
639 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
640 union ixgbe_adv_rx_desc *rx_desc,
641 struct sk_buff *skb);
642 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
643 struct scatterlist *sgl, unsigned int sgc);
644 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
645 struct scatterlist *sgl, unsigned int sgc);
646 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
647 extern int ixgbe_fcoe_enable(struct net_device *netdev);
648 extern int ixgbe_fcoe_disable(struct net_device *netdev);
649 #ifdef CONFIG_IXGBE_DCB
650 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
651 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
652 #endif /* CONFIG_IXGBE_DCB */
653 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
654 extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
655 struct netdev_fcoe_hbainfo *info);
656 #endif /* IXGBE_FCOE */
657
txring_txq(const struct ixgbe_ring * ring)658 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
659 {
660 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
661 }
662
663 #endif /* _IXGBE_H_ */
664