1 /*
2 * arch/arm/mach-kirkwood/pcie.c
3 *
4 * PCIe functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <video/vga.h>
15 #include <asm/irq.h>
16 #include <asm/mach/pci.h>
17 #include <plat/pcie.h>
18 #include <mach/bridge-regs.h>
19 #include <plat/addr-map.h>
20 #include "common.h"
21
kirkwood_enable_pcie(void)22 void kirkwood_enable_pcie(void)
23 {
24 u32 curr = readl(CLOCK_GATING_CTRL);
25 if (!(curr & CGC_PEX0))
26 writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
27 }
28
kirkwood_pcie_id(u32 * dev,u32 * rev)29 void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
30 {
31 kirkwood_enable_pcie();
32 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
33 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
34 }
35
36 struct pcie_port {
37 u8 root_bus_nr;
38 void __iomem *base;
39 spinlock_t conf_lock;
40 int irq;
41 struct resource res[2];
42 };
43
44 static int pcie_port_map[2];
45 static int num_pcie_ports;
46
bus_to_port(struct pci_bus * bus)47 static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
48 {
49 struct pci_sys_data *sys = bus->sysdata;
50 return sys->private_data;
51 }
52
pcie_valid_config(struct pcie_port * pp,int bus,int dev)53 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
54 {
55 /*
56 * Don't go out when trying to access --
57 * 1. nonexisting device on local bus
58 * 2. where there's no device connected (no link)
59 */
60 if (bus == pp->root_bus_nr && dev == 0)
61 return 1;
62
63 if (!orion_pcie_link_up(pp->base))
64 return 0;
65
66 if (bus == pp->root_bus_nr && dev != 1)
67 return 0;
68
69 return 1;
70 }
71
72
73 /*
74 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
75 * and then reading the PCIE_CONF_DATA register. Need to make sure these
76 * transactions are atomic.
77 */
78
pcie_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)79 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
80 int size, u32 *val)
81 {
82 struct pcie_port *pp = bus_to_port(bus);
83 unsigned long flags;
84 int ret;
85
86 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
87 *val = 0xffffffff;
88 return PCIBIOS_DEVICE_NOT_FOUND;
89 }
90
91 spin_lock_irqsave(&pp->conf_lock, flags);
92 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
93 spin_unlock_irqrestore(&pp->conf_lock, flags);
94
95 return ret;
96 }
97
pcie_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)98 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
99 int where, int size, u32 val)
100 {
101 struct pcie_port *pp = bus_to_port(bus);
102 unsigned long flags;
103 int ret;
104
105 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
106 return PCIBIOS_DEVICE_NOT_FOUND;
107
108 spin_lock_irqsave(&pp->conf_lock, flags);
109 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
110 spin_unlock_irqrestore(&pp->conf_lock, flags);
111
112 return ret;
113 }
114
115 static struct pci_ops pcie_ops = {
116 .read = pcie_rd_conf,
117 .write = pcie_wr_conf,
118 };
119
pcie0_ioresources_init(struct pcie_port * pp)120 static void __init pcie0_ioresources_init(struct pcie_port *pp)
121 {
122 pp->base = (void __iomem *)PCIE_VIRT_BASE;
123 pp->irq = IRQ_KIRKWOOD_PCIE;
124
125 /*
126 * IORESOURCE_IO
127 */
128 pp->res[0].name = "PCIe 0 I/O Space";
129 pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
130 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
131 pp->res[0].flags = IORESOURCE_IO;
132
133 /*
134 * IORESOURCE_MEM
135 */
136 pp->res[1].name = "PCIe 0 MEM";
137 pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
138 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
139 pp->res[1].flags = IORESOURCE_MEM;
140 }
141
pcie1_ioresources_init(struct pcie_port * pp)142 static void __init pcie1_ioresources_init(struct pcie_port *pp)
143 {
144 pp->base = (void __iomem *)PCIE1_VIRT_BASE;
145 pp->irq = IRQ_KIRKWOOD_PCIE1;
146
147 /*
148 * IORESOURCE_IO
149 */
150 pp->res[0].name = "PCIe 1 I/O Space";
151 pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
152 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
153 pp->res[0].flags = IORESOURCE_IO;
154
155 /*
156 * IORESOURCE_MEM
157 */
158 pp->res[1].name = "PCIe 1 MEM";
159 pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
160 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
161 pp->res[1].flags = IORESOURCE_MEM;
162 }
163
kirkwood_pcie_setup(int nr,struct pci_sys_data * sys)164 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
165 {
166 extern unsigned int kirkwood_clk_ctrl;
167 struct pcie_port *pp;
168 int index;
169
170 if (nr >= num_pcie_ports)
171 return 0;
172
173 index = pcie_port_map[nr];
174 printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
175
176 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
177 if (!pp)
178 panic("PCIe: failed to allocate pcie_port data");
179 sys->private_data = pp;
180 pp->root_bus_nr = sys->busnr;
181 spin_lock_init(&pp->conf_lock);
182
183 switch (index) {
184 case 0:
185 kirkwood_clk_ctrl |= CGC_PEX0;
186 pcie0_ioresources_init(pp);
187 break;
188 case 1:
189 kirkwood_clk_ctrl |= CGC_PEX1;
190 pcie1_ioresources_init(pp);
191 break;
192 default:
193 panic("PCIe setup: invalid controller %d", index);
194 }
195
196 if (request_resource(&ioport_resource, &pp->res[0]))
197 panic("Request PCIe%d IO resource failed\n", index);
198 if (request_resource(&iomem_resource, &pp->res[1]))
199 panic("Request PCIe%d Memory resource failed\n", index);
200
201 sys->io_offset = 0;
202 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
203 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
204
205 /*
206 * Generic PCIe unit setup.
207 */
208 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
209
210 orion_pcie_setup(pp->base);
211
212 return 1;
213 }
214
215 /*
216 * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
217 * is operating as a root complex this needs to be switched to
218 * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
219 * the device. Decoding setup is handled by the orion code.
220 */
rc_pci_fixup(struct pci_dev * dev)221 static void __devinit rc_pci_fixup(struct pci_dev *dev)
222 {
223 if (dev->bus->parent == NULL && dev->devfn == 0) {
224 int i;
225
226 dev->class &= 0xff;
227 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
228 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
229 dev->resource[i].start = 0;
230 dev->resource[i].end = 0;
231 dev->resource[i].flags = 0;
232 }
233 }
234 }
235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
236
237 static struct pci_bus __init *
kirkwood_pcie_scan_bus(int nr,struct pci_sys_data * sys)238 kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
239 {
240 struct pci_bus *bus;
241
242 if (nr < num_pcie_ports) {
243 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
244 &sys->resources);
245 } else {
246 bus = NULL;
247 BUG();
248 }
249
250 return bus;
251 }
252
kirkwood_pcie_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)253 static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
254 u8 pin)
255 {
256 struct pcie_port *pp = bus_to_port(dev->bus);
257
258 return pp->irq;
259 }
260
261 static struct hw_pci kirkwood_pci __initdata = {
262 .swizzle = pci_std_swizzle,
263 .setup = kirkwood_pcie_setup,
264 .scan = kirkwood_pcie_scan_bus,
265 .map_irq = kirkwood_pcie_map_irq,
266 };
267
add_pcie_port(int index,unsigned long base)268 static void __init add_pcie_port(int index, unsigned long base)
269 {
270 printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
271
272 if (orion_pcie_link_up((void __iomem *)base)) {
273 printk(KERN_INFO "link up\n");
274 pcie_port_map[num_pcie_ports++] = index;
275 } else
276 printk(KERN_INFO "link down, ignoring\n");
277 }
278
kirkwood_pcie_init(unsigned int portmask)279 void __init kirkwood_pcie_init(unsigned int portmask)
280 {
281 vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
282
283 if (portmask & KW_PCIE0)
284 add_pcie_port(0, PCIE_VIRT_BASE);
285
286 if (portmask & KW_PCIE1)
287 add_pcie_port(1, PCIE1_VIRT_BASE);
288
289 kirkwood_pci.nr_controllers = num_pcie_ports;
290 pci_common_init(&kirkwood_pci);
291 }
292