1 /*
2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_address.h>
25
26 #include <asm/cacheflush.h>
27 #include <asm/hardware/cache-l2x0.h>
28
29 #define CACHE_LINE_SIZE 32
30
31 static void __iomem *l2x0_base;
32 static DEFINE_RAW_SPINLOCK(l2x0_lock);
33 static u32 l2x0_way_mask; /* Bitmask of active ways */
34 static u32 l2x0_size;
35 static u32 l2x0_cache_id;
36 static unsigned int l2x0_sets;
37 static unsigned int l2x0_ways;
38 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
39
is_pl310_rev(int rev)40 static inline bool is_pl310_rev(int rev)
41 {
42 return (l2x0_cache_id &
43 (L2X0_CACHE_ID_PART_MASK | L2X0_CACHE_ID_REV_MASK)) ==
44 (L2X0_CACHE_ID_PART_L310 | rev);
45 }
46
47 struct l2x0_regs l2x0_saved_regs;
48
49 struct l2x0_of_data {
50 void (*setup)(const struct device_node *, u32 *, u32 *);
51 void (*save)(void);
52 void (*resume)(void);
53 };
54
cache_wait_way(void __iomem * reg,unsigned long mask)55 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
56 {
57 /* wait for cache operation by line or way to complete */
58 while (readl_relaxed(reg) & mask)
59 cpu_relax();
60 }
61
62 #ifdef CONFIG_CACHE_PL310
cache_wait(void __iomem * reg,unsigned long mask)63 static inline void cache_wait(void __iomem *reg, unsigned long mask)
64 {
65 /* cache operations by line are atomic on PL310 */
66 }
67 #else
68 #define cache_wait cache_wait_way
69 #endif
70
cache_sync(void)71 static inline void cache_sync(void)
72 {
73 void __iomem *base = l2x0_base;
74
75 writel_relaxed(0, base + sync_reg_offset);
76 cache_wait(base + L2X0_CACHE_SYNC, 1);
77 }
78
l2x0_clean_line(unsigned long addr)79 static inline void l2x0_clean_line(unsigned long addr)
80 {
81 void __iomem *base = l2x0_base;
82 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
83 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
84 }
85
l2x0_inv_line(unsigned long addr)86 static inline void l2x0_inv_line(unsigned long addr)
87 {
88 void __iomem *base = l2x0_base;
89 cache_wait(base + L2X0_INV_LINE_PA, 1);
90 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
91 }
92
93 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
debug_writel(unsigned long val)94 static inline void debug_writel(unsigned long val)
95 {
96 if (outer_cache.set_debug)
97 outer_cache.set_debug(val);
98 }
99
pl310_set_debug(unsigned long val)100 static void pl310_set_debug(unsigned long val)
101 {
102 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
103 }
104 #else
105 /* Optimised out for non-errata case */
debug_writel(unsigned long val)106 static inline void debug_writel(unsigned long val)
107 {
108 }
109
110 #define pl310_set_debug NULL
111 #endif
112
113 #ifdef CONFIG_PL310_ERRATA_588369
l2x0_flush_line(unsigned long addr)114 static inline void l2x0_flush_line(unsigned long addr)
115 {
116 void __iomem *base = l2x0_base;
117
118 /* Clean by PA followed by Invalidate by PA */
119 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
120 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
121 cache_wait(base + L2X0_INV_LINE_PA, 1);
122 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
123 }
124 #else
125
l2x0_flush_line(unsigned long addr)126 static inline void l2x0_flush_line(unsigned long addr)
127 {
128 void __iomem *base = l2x0_base;
129 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
130 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
131 }
132 #endif
133
l2x0_cache_sync(void)134 static void l2x0_cache_sync(void)
135 {
136 unsigned long flags;
137
138 raw_spin_lock_irqsave(&l2x0_lock, flags);
139 cache_sync();
140 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
141 }
142
143 #ifdef CONFIG_PL310_ERRATA_727915
l2x0_for_each_set_way(void __iomem * reg)144 static void l2x0_for_each_set_way(void __iomem *reg)
145 {
146 int set;
147 int way;
148 unsigned long flags;
149
150 for (way = 0; way < l2x0_ways; way++) {
151 raw_spin_lock_irqsave(&l2x0_lock, flags);
152 for (set = 0; set < l2x0_sets; set++)
153 writel_relaxed((way << 28) | (set << 5), reg);
154 cache_sync();
155 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
156 }
157 }
158 #endif
159
__l2x0_flush_all(void)160 static void __l2x0_flush_all(void)
161 {
162 debug_writel(0x03);
163 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
164 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
165 cache_sync();
166 debug_writel(0x00);
167 }
168
l2x0_flush_all(void)169 static void l2x0_flush_all(void)
170 {
171 unsigned long flags;
172
173 #ifdef CONFIG_PL310_ERRATA_727915
174 if (is_pl310_rev(REV_PL310_R2P0)) {
175 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX);
176 return;
177 }
178 #endif
179
180 /* clean all ways */
181 raw_spin_lock_irqsave(&l2x0_lock, flags);
182 __l2x0_flush_all();
183 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
184 }
185
l2x0_clean_all(void)186 static void l2x0_clean_all(void)
187 {
188 unsigned long flags;
189
190 #ifdef CONFIG_PL310_ERRATA_727915
191 if (is_pl310_rev(REV_PL310_R2P0)) {
192 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX);
193 return;
194 }
195 #endif
196
197 /* clean all ways */
198 raw_spin_lock_irqsave(&l2x0_lock, flags);
199 debug_writel(0x03);
200 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
201 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
202 cache_sync();
203 debug_writel(0x00);
204 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
205 }
206
l2x0_inv_all(void)207 static void l2x0_inv_all(void)
208 {
209 unsigned long flags;
210
211 /* invalidate all ways */
212 raw_spin_lock_irqsave(&l2x0_lock, flags);
213 /* Invalidating when L2 is enabled is a nono */
214 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
215 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
216 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
217 cache_sync();
218 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
219 }
220
l2x0_inv_range(unsigned long start,unsigned long end)221 static void l2x0_inv_range(unsigned long start, unsigned long end)
222 {
223 void __iomem *base = l2x0_base;
224 unsigned long flags;
225
226 raw_spin_lock_irqsave(&l2x0_lock, flags);
227 if (start & (CACHE_LINE_SIZE - 1)) {
228 start &= ~(CACHE_LINE_SIZE - 1);
229 debug_writel(0x03);
230 l2x0_flush_line(start);
231 debug_writel(0x00);
232 start += CACHE_LINE_SIZE;
233 }
234
235 if (end & (CACHE_LINE_SIZE - 1)) {
236 end &= ~(CACHE_LINE_SIZE - 1);
237 debug_writel(0x03);
238 l2x0_flush_line(end);
239 debug_writel(0x00);
240 }
241
242 while (start < end) {
243 unsigned long blk_end = start + min(end - start, 4096UL);
244
245 while (start < blk_end) {
246 l2x0_inv_line(start);
247 start += CACHE_LINE_SIZE;
248 }
249
250 if (blk_end < end) {
251 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
252 raw_spin_lock_irqsave(&l2x0_lock, flags);
253 }
254 }
255 cache_wait(base + L2X0_INV_LINE_PA, 1);
256 cache_sync();
257 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
258 }
259
l2x0_clean_range(unsigned long start,unsigned long end)260 static void l2x0_clean_range(unsigned long start, unsigned long end)
261 {
262 void __iomem *base = l2x0_base;
263 unsigned long flags;
264
265 if ((end - start) >= l2x0_size) {
266 l2x0_clean_all();
267 return;
268 }
269
270 raw_spin_lock_irqsave(&l2x0_lock, flags);
271 start &= ~(CACHE_LINE_SIZE - 1);
272 while (start < end) {
273 unsigned long blk_end = start + min(end - start, 4096UL);
274
275 while (start < blk_end) {
276 l2x0_clean_line(start);
277 start += CACHE_LINE_SIZE;
278 }
279
280 if (blk_end < end) {
281 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
282 raw_spin_lock_irqsave(&l2x0_lock, flags);
283 }
284 }
285 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
286 cache_sync();
287 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
288 }
289
l2x0_flush_range(unsigned long start,unsigned long end)290 static void l2x0_flush_range(unsigned long start, unsigned long end)
291 {
292 void __iomem *base = l2x0_base;
293 unsigned long flags;
294
295 if ((end - start) >= l2x0_size) {
296 l2x0_flush_all();
297 return;
298 }
299
300 raw_spin_lock_irqsave(&l2x0_lock, flags);
301 start &= ~(CACHE_LINE_SIZE - 1);
302 while (start < end) {
303 unsigned long blk_end = start + min(end - start, 4096UL);
304
305 debug_writel(0x03);
306 while (start < blk_end) {
307 l2x0_flush_line(start);
308 start += CACHE_LINE_SIZE;
309 }
310 debug_writel(0x00);
311
312 if (blk_end < end) {
313 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
314 raw_spin_lock_irqsave(&l2x0_lock, flags);
315 }
316 }
317 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
318 cache_sync();
319 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
320 }
321
l2x0_disable(void)322 static void l2x0_disable(void)
323 {
324 unsigned long flags;
325
326 raw_spin_lock_irqsave(&l2x0_lock, flags);
327 __l2x0_flush_all();
328 writel_relaxed(0, l2x0_base + L2X0_CTRL);
329 dsb();
330 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
331 }
332
l2x0_unlock(u32 cache_id)333 static void l2x0_unlock(u32 cache_id)
334 {
335 int lockregs;
336 int i;
337
338 if (cache_id == L2X0_CACHE_ID_PART_L310)
339 lockregs = 8;
340 else
341 /* L210 and unknown types */
342 lockregs = 1;
343
344 for (i = 0; i < lockregs; i++) {
345 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
346 i * L2X0_LOCKDOWN_STRIDE);
347 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
348 i * L2X0_LOCKDOWN_STRIDE);
349 }
350 }
351
l2x0_init(void __iomem * base,u32 aux_val,u32 aux_mask)352 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
353 {
354 u32 aux;
355 u32 way_size = 0;
356 const char *type;
357
358 l2x0_base = base;
359
360 l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
361 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
362
363 aux &= aux_mask;
364 aux |= aux_val;
365
366 /* Determine the number of ways */
367 switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) {
368 case L2X0_CACHE_ID_PART_L310:
369 if (aux & (1 << 16))
370 l2x0_ways = 16;
371 else
372 l2x0_ways = 8;
373 type = "L310";
374 #ifdef CONFIG_PL310_ERRATA_753970
375 /* Unmapped register. */
376 sync_reg_offset = L2X0_DUMMY_REG;
377 #endif
378 outer_cache.set_debug = pl310_set_debug;
379 break;
380 case L2X0_CACHE_ID_PART_L210:
381 l2x0_ways = (aux >> 13) & 0xf;
382 type = "L210";
383 break;
384 default:
385 /* Assume unknown chips have 8 ways */
386 l2x0_ways = 8;
387 type = "L2x0 series";
388 break;
389 }
390
391 l2x0_way_mask = (1 << l2x0_ways) - 1;
392
393 /*
394 * L2 cache Size = Way size * Number of ways
395 */
396 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
397 way_size = SZ_1K << (way_size + 3);
398 l2x0_size = l2x0_ways * way_size;
399 l2x0_sets = way_size / CACHE_LINE_SIZE;
400
401 /*
402 * Check if l2x0 controller is already enabled.
403 * If you are booting from non-secure mode
404 * accessing the below registers will fault.
405 */
406 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
407 /* Make sure that I&D is not locked down when starting */
408 l2x0_unlock(l2x0_cache_id);
409
410 /* l2x0 controller is disabled */
411 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
412
413 l2x0_saved_regs.aux_ctrl = aux;
414
415 l2x0_inv_all();
416
417 /* enable L2X0 */
418 writel_relaxed(1, l2x0_base + L2X0_CTRL);
419 }
420
421 outer_cache.inv_range = l2x0_inv_range;
422 outer_cache.clean_range = l2x0_clean_range;
423 outer_cache.flush_range = l2x0_flush_range;
424 outer_cache.sync = l2x0_cache_sync;
425 outer_cache.flush_all = l2x0_flush_all;
426 outer_cache.inv_all = l2x0_inv_all;
427 outer_cache.disable = l2x0_disable;
428
429 printk(KERN_INFO "%s cache controller enabled\n", type);
430 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
431 l2x0_ways, l2x0_cache_id, aux, l2x0_size);
432 }
433
434 #ifdef CONFIG_OF
l2x0_of_setup(const struct device_node * np,u32 * aux_val,u32 * aux_mask)435 static void __init l2x0_of_setup(const struct device_node *np,
436 u32 *aux_val, u32 *aux_mask)
437 {
438 u32 data[2] = { 0, 0 };
439 u32 tag = 0;
440 u32 dirty = 0;
441 u32 val = 0, mask = 0;
442
443 of_property_read_u32(np, "arm,tag-latency", &tag);
444 if (tag) {
445 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
446 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
447 }
448
449 of_property_read_u32_array(np, "arm,data-latency",
450 data, ARRAY_SIZE(data));
451 if (data[0] && data[1]) {
452 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
453 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
454 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
455 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
456 }
457
458 of_property_read_u32(np, "arm,dirty-latency", &dirty);
459 if (dirty) {
460 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
461 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
462 }
463
464 *aux_val &= ~mask;
465 *aux_val |= val;
466 *aux_mask &= ~mask;
467 }
468
pl310_of_setup(const struct device_node * np,u32 * aux_val,u32 * aux_mask)469 static void __init pl310_of_setup(const struct device_node *np,
470 u32 *aux_val, u32 *aux_mask)
471 {
472 u32 data[3] = { 0, 0, 0 };
473 u32 tag[3] = { 0, 0, 0 };
474 u32 filter[2] = { 0, 0 };
475
476 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
477 if (tag[0] && tag[1] && tag[2])
478 writel_relaxed(
479 ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
480 ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
481 ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
482 l2x0_base + L2X0_TAG_LATENCY_CTRL);
483
484 of_property_read_u32_array(np, "arm,data-latency",
485 data, ARRAY_SIZE(data));
486 if (data[0] && data[1] && data[2])
487 writel_relaxed(
488 ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
489 ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
490 ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
491 l2x0_base + L2X0_DATA_LATENCY_CTRL);
492
493 of_property_read_u32_array(np, "arm,filter-ranges",
494 filter, ARRAY_SIZE(filter));
495 if (filter[1]) {
496 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
497 l2x0_base + L2X0_ADDR_FILTER_END);
498 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
499 l2x0_base + L2X0_ADDR_FILTER_START);
500 }
501 }
502
pl310_save(void)503 static void __init pl310_save(void)
504 {
505 u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
506 L2X0_CACHE_ID_RTL_MASK;
507
508 l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
509 L2X0_TAG_LATENCY_CTRL);
510 l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
511 L2X0_DATA_LATENCY_CTRL);
512 l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
513 L2X0_ADDR_FILTER_END);
514 l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
515 L2X0_ADDR_FILTER_START);
516
517 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
518 /*
519 * From r2p0, there is Prefetch offset/control register
520 */
521 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
522 L2X0_PREFETCH_CTRL);
523 /*
524 * From r3p0, there is Power control register
525 */
526 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
527 l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
528 L2X0_POWER_CTRL);
529 }
530 }
531
l2x0_resume(void)532 static void l2x0_resume(void)
533 {
534 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
535 /* restore aux ctrl and enable l2 */
536 l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
537
538 writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
539 L2X0_AUX_CTRL);
540
541 l2x0_inv_all();
542
543 writel_relaxed(1, l2x0_base + L2X0_CTRL);
544 }
545 }
546
pl310_resume(void)547 static void pl310_resume(void)
548 {
549 u32 l2x0_revision;
550
551 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
552 /* restore pl310 setup */
553 writel_relaxed(l2x0_saved_regs.tag_latency,
554 l2x0_base + L2X0_TAG_LATENCY_CTRL);
555 writel_relaxed(l2x0_saved_regs.data_latency,
556 l2x0_base + L2X0_DATA_LATENCY_CTRL);
557 writel_relaxed(l2x0_saved_regs.filter_end,
558 l2x0_base + L2X0_ADDR_FILTER_END);
559 writel_relaxed(l2x0_saved_regs.filter_start,
560 l2x0_base + L2X0_ADDR_FILTER_START);
561
562 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
563 L2X0_CACHE_ID_RTL_MASK;
564
565 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
566 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
567 l2x0_base + L2X0_PREFETCH_CTRL);
568 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
569 writel_relaxed(l2x0_saved_regs.pwr_ctrl,
570 l2x0_base + L2X0_POWER_CTRL);
571 }
572 }
573
574 l2x0_resume();
575 }
576
577 static const struct l2x0_of_data pl310_data = {
578 pl310_of_setup,
579 pl310_save,
580 pl310_resume,
581 };
582
583 static const struct l2x0_of_data l2x0_data = {
584 l2x0_of_setup,
585 NULL,
586 l2x0_resume,
587 };
588
589 static const struct of_device_id l2x0_ids[] __initconst = {
590 { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
591 { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
592 { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
593 {}
594 };
595
l2x0_of_init(u32 aux_val,u32 aux_mask)596 int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
597 {
598 struct device_node *np;
599 struct l2x0_of_data *data;
600 struct resource res;
601
602 np = of_find_matching_node(NULL, l2x0_ids);
603 if (!np)
604 return -ENODEV;
605
606 if (of_address_to_resource(np, 0, &res))
607 return -ENODEV;
608
609 l2x0_base = ioremap(res.start, resource_size(&res));
610 if (!l2x0_base)
611 return -ENOMEM;
612
613 l2x0_saved_regs.phy_base = res.start;
614
615 data = of_match_node(l2x0_ids, np)->data;
616
617 /* L2 configuration can only be changed if the cache is disabled */
618 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
619 if (data->setup)
620 data->setup(np, &aux_val, &aux_mask);
621 }
622
623 if (data->save)
624 data->save();
625
626 l2x0_init(l2x0_base, aux_val, aux_mask);
627
628 outer_cache.resume = data->resume;
629 return 0;
630 }
631 #endif
632