1 /*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/serial_8250.h>
21 #include <linux/gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/irq.h>
24
25 #include <asm/mach-types.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/time.h>
28 #include <asm/memory.h>
29 #include <asm/mach/map.h>
30 #include <mach/common.h>
31 #include <mach/iomux-mx3.h>
32
33 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
34 #include <linux/mfd/wm8350/audio.h>
35 #include <linux/mfd/wm8350/core.h>
36 #include <linux/mfd/wm8350/pmic.h>
37 #endif
38
39 #include "devices-imx31.h"
40
41 /* Base address of PBC controller */
42 #define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
43
44 /* PBC Board interrupt status register */
45 #define PBC_INTSTATUS 0x000016
46
47 /* PBC Board interrupt current status register */
48 #define PBC_INTCURR_STATUS 0x000018
49
50 /* PBC Interrupt mask register set address */
51 #define PBC_INTMASK_SET 0x00001A
52
53 /* PBC Interrupt mask register clear address */
54 #define PBC_INTMASK_CLEAR 0x00001C
55
56 /* External UART A */
57 #define PBC_SC16C652_UARTA 0x010000
58
59 /* External UART B */
60 #define PBC_SC16C652_UARTB 0x010010
61
62 #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
63 #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
64 #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
65 #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
66
67 #define MXC_EXP_IO_BASE MXC_BOARD_IRQ_START
68 #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
69
70 #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
71 #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
72
73 #define MXC_MAX_EXP_IO_LINES 16
74
75 /* CS8900 */
76 #define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
77 #define CS4_CS8900_MMIO_START 0x20000
78
79 /*
80 * The serial port definition structure.
81 */
82 static struct plat_serial8250_port serial_platform_data[] = {
83 {
84 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
85 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
86 .irq = EXPIO_INT_XUART_INTA,
87 .uartclk = 14745600,
88 .regshift = 0,
89 .iotype = UPIO_MEM,
90 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
91 }, {
92 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
93 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
94 .irq = EXPIO_INT_XUART_INTB,
95 .uartclk = 14745600,
96 .regshift = 0,
97 .iotype = UPIO_MEM,
98 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
99 },
100 {},
101 };
102
103 static struct platform_device serial_device = {
104 .name = "serial8250",
105 .id = 0,
106 .dev = {
107 .platform_data = serial_platform_data,
108 },
109 };
110
111 static const struct resource mx31ads_cs8900_resources[] __initconst = {
112 DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
113 DEFINE_RES_IRQ(EXPIO_INT_ENET_INT),
114 };
115
116 static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
117 .name = "cs89x0",
118 .id = 0,
119 .res = mx31ads_cs8900_resources,
120 .num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
121 };
122
mxc_init_extuart(void)123 static int __init mxc_init_extuart(void)
124 {
125 return platform_device_register(&serial_device);
126 }
127
mxc_init_ext_ethernet(void)128 static void __init mxc_init_ext_ethernet(void)
129 {
130 platform_device_register_full(
131 (struct platform_device_info *)&mx31ads_cs8900_devinfo);
132 }
133
134 static const struct imxuart_platform_data uart_pdata __initconst = {
135 .flags = IMXUART_HAVE_RTSCTS,
136 };
137
138 static unsigned int uart_pins[] = {
139 MX31_PIN_CTS1__CTS1,
140 MX31_PIN_RTS1__RTS1,
141 MX31_PIN_TXD1__TXD1,
142 MX31_PIN_RXD1__RXD1
143 };
144
mxc_init_imx_uart(void)145 static inline void mxc_init_imx_uart(void)
146 {
147 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
148 imx31_add_imx_uart0(&uart_pdata);
149 }
150
mx31ads_expio_irq_handler(u32 irq,struct irq_desc * desc)151 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
152 {
153 u32 imr_val;
154 u32 int_valid;
155 u32 expio_irq;
156
157 imr_val = __raw_readw(PBC_INTMASK_SET_REG);
158 int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
159
160 expio_irq = MXC_EXP_IO_BASE;
161 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
162 if ((int_valid & 1) == 0)
163 continue;
164
165 generic_handle_irq(expio_irq);
166 }
167 }
168
169 /*
170 * Disable an expio pin's interrupt by setting the bit in the imr.
171 * @param d an expio virtual irq description
172 */
expio_mask_irq(struct irq_data * d)173 static void expio_mask_irq(struct irq_data *d)
174 {
175 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
176 /* mask the interrupt */
177 __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
178 __raw_readw(PBC_INTMASK_CLEAR_REG);
179 }
180
181 /*
182 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
183 * @param d an expio virtual irq description
184 */
expio_ack_irq(struct irq_data * d)185 static void expio_ack_irq(struct irq_data *d)
186 {
187 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
188 /* clear the interrupt status */
189 __raw_writew(1 << expio, PBC_INTSTATUS_REG);
190 }
191
192 /*
193 * Enable a expio pin's interrupt by clearing the bit in the imr.
194 * @param d an expio virtual irq description
195 */
expio_unmask_irq(struct irq_data * d)196 static void expio_unmask_irq(struct irq_data *d)
197 {
198 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
199 /* unmask the interrupt */
200 __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
201 }
202
203 static struct irq_chip expio_irq_chip = {
204 .name = "EXPIO(CPLD)",
205 .irq_ack = expio_ack_irq,
206 .irq_mask = expio_mask_irq,
207 .irq_unmask = expio_unmask_irq,
208 };
209
mx31ads_init_expio(void)210 static void __init mx31ads_init_expio(void)
211 {
212 int i;
213
214 printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
215
216 /*
217 * Configure INT line as GPIO input
218 */
219 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
220
221 /* disable the interrupt and clear the status */
222 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
223 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
224 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
225 i++) {
226 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
227 set_irq_flags(i, IRQF_VALID);
228 }
229 irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
230 irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
231 }
232
233 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
234 /* This section defines setup for the Wolfson Microelectronics
235 * 1133-EV1 PMU/audio board. When other PMU boards are supported the
236 * regulator definitions may be shared with them, but for now they can
237 * only be used with this board so would generate warnings about
238 * unused statics and some of the configuration is specific to this
239 * module.
240 */
241
242 /* CPU */
243 static struct regulator_consumer_supply sw1a_consumers[] = {
244 {
245 .supply = "cpu_vcc",
246 }
247 };
248
249 static struct regulator_init_data sw1a_data = {
250 .constraints = {
251 .name = "SW1A",
252 .min_uV = 1275000,
253 .max_uV = 1600000,
254 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
255 REGULATOR_CHANGE_MODE,
256 .valid_modes_mask = REGULATOR_MODE_NORMAL |
257 REGULATOR_MODE_FAST,
258 .state_mem = {
259 .uV = 1400000,
260 .mode = REGULATOR_MODE_NORMAL,
261 .enabled = 1,
262 },
263 .initial_state = PM_SUSPEND_MEM,
264 .always_on = 1,
265 .boot_on = 1,
266 },
267 .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
268 .consumer_supplies = sw1a_consumers,
269 };
270
271 /* System IO - High */
272 static struct regulator_init_data viohi_data = {
273 .constraints = {
274 .name = "VIOHO",
275 .min_uV = 2800000,
276 .max_uV = 2800000,
277 .state_mem = {
278 .uV = 2800000,
279 .mode = REGULATOR_MODE_NORMAL,
280 .enabled = 1,
281 },
282 .initial_state = PM_SUSPEND_MEM,
283 .always_on = 1,
284 .boot_on = 1,
285 },
286 };
287
288 /* System IO - Low */
289 static struct regulator_init_data violo_data = {
290 .constraints = {
291 .name = "VIOLO",
292 .min_uV = 1800000,
293 .max_uV = 1800000,
294 .state_mem = {
295 .uV = 1800000,
296 .mode = REGULATOR_MODE_NORMAL,
297 .enabled = 1,
298 },
299 .initial_state = PM_SUSPEND_MEM,
300 .always_on = 1,
301 .boot_on = 1,
302 },
303 };
304
305 /* DDR RAM */
306 static struct regulator_init_data sw2a_data = {
307 .constraints = {
308 .name = "SW2A",
309 .min_uV = 1800000,
310 .max_uV = 1800000,
311 .valid_modes_mask = REGULATOR_MODE_NORMAL,
312 .state_mem = {
313 .uV = 1800000,
314 .mode = REGULATOR_MODE_NORMAL,
315 .enabled = 1,
316 },
317 .state_disk = {
318 .mode = REGULATOR_MODE_NORMAL,
319 .enabled = 0,
320 },
321 .always_on = 1,
322 .boot_on = 1,
323 .initial_state = PM_SUSPEND_MEM,
324 },
325 };
326
327 static struct regulator_init_data ldo1_data = {
328 .constraints = {
329 .name = "VCAM/VMMC1/VMMC2",
330 .min_uV = 2800000,
331 .max_uV = 2800000,
332 .valid_modes_mask = REGULATOR_MODE_NORMAL,
333 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
334 .apply_uV = 1,
335 },
336 };
337
338 static struct regulator_consumer_supply ldo2_consumers[] = {
339 { .supply = "AVDD", .dev_name = "1-001a" },
340 { .supply = "HPVDD", .dev_name = "1-001a" },
341 };
342
343 /* CODEC and SIM */
344 static struct regulator_init_data ldo2_data = {
345 .constraints = {
346 .name = "VESIM/VSIM/AVDD",
347 .min_uV = 3300000,
348 .max_uV = 3300000,
349 .valid_modes_mask = REGULATOR_MODE_NORMAL,
350 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
351 .apply_uV = 1,
352 },
353 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
354 .consumer_supplies = ldo2_consumers,
355 };
356
357 /* General */
358 static struct regulator_init_data vdig_data = {
359 .constraints = {
360 .name = "VDIG",
361 .min_uV = 1500000,
362 .max_uV = 1500000,
363 .valid_modes_mask = REGULATOR_MODE_NORMAL,
364 .apply_uV = 1,
365 .always_on = 1,
366 .boot_on = 1,
367 },
368 };
369
370 /* Tranceivers */
371 static struct regulator_init_data ldo4_data = {
372 .constraints = {
373 .name = "VRF1/CVDD_2.775",
374 .min_uV = 2500000,
375 .max_uV = 2500000,
376 .valid_modes_mask = REGULATOR_MODE_NORMAL,
377 .apply_uV = 1,
378 .always_on = 1,
379 .boot_on = 1,
380 },
381 };
382
383 static struct wm8350_led_platform_data wm8350_led_data = {
384 .name = "wm8350:white",
385 .default_trigger = "heartbeat",
386 .max_uA = 27899,
387 };
388
389 static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
390 .vmid_discharge_msecs = 1000,
391 .drain_msecs = 30,
392 .cap_discharge_msecs = 700,
393 .vmid_charge_msecs = 700,
394 .vmid_s_curve = WM8350_S_CURVE_SLOW,
395 .dis_out4 = WM8350_DISCHARGE_SLOW,
396 .dis_out3 = WM8350_DISCHARGE_SLOW,
397 .dis_out2 = WM8350_DISCHARGE_SLOW,
398 .dis_out1 = WM8350_DISCHARGE_SLOW,
399 .vroi_out4 = WM8350_TIE_OFF_500R,
400 .vroi_out3 = WM8350_TIE_OFF_500R,
401 .vroi_out2 = WM8350_TIE_OFF_500R,
402 .vroi_out1 = WM8350_TIE_OFF_500R,
403 .vroi_enable = 0,
404 .codec_current_on = WM8350_CODEC_ISEL_1_0,
405 .codec_current_standby = WM8350_CODEC_ISEL_0_5,
406 .codec_current_charge = WM8350_CODEC_ISEL_1_5,
407 };
408
mx31_wm8350_init(struct wm8350 * wm8350)409 static int mx31_wm8350_init(struct wm8350 *wm8350)
410 {
411 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
412 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
413 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
414 WM8350_GPIO_DEBOUNCE_ON);
415
416 wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
417 WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
418 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
419 WM8350_GPIO_DEBOUNCE_ON);
420
421 wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
422 WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
423 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
424 WM8350_GPIO_DEBOUNCE_OFF);
425
426 wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
427 WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
428 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
429 WM8350_GPIO_DEBOUNCE_OFF);
430
431 wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
432 WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
433 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
434 WM8350_GPIO_DEBOUNCE_OFF);
435
436 wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
437 WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
438 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
439 WM8350_GPIO_DEBOUNCE_OFF);
440
441 wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
442 WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
443 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
444 WM8350_GPIO_DEBOUNCE_OFF);
445
446 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
447 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
448 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
449 wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
450 wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
451 wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
452 wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
453 wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
454
455 /* LEDs */
456 wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
457 WM8350_DC5_ERRACT_SHUTDOWN_CONV);
458 wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
459 WM8350_ISINK_FLASH_DISABLE,
460 WM8350_ISINK_FLASH_TRIG_BIT,
461 WM8350_ISINK_FLASH_DUR_32MS,
462 WM8350_ISINK_FLASH_ON_INSTANT,
463 WM8350_ISINK_FLASH_OFF_INSTANT,
464 WM8350_ISINK_FLASH_MODE_EN);
465 wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
466 WM8350_ISINK_MODE_BOOST,
467 WM8350_ISINK_ILIM_NORMAL,
468 WM8350_DC5_RMP_20V,
469 WM8350_DC5_FBSRC_ISINKA);
470 wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
471 &wm8350_led_data);
472
473 wm8350->codec.platform_data = &imx32ads_wm8350_setup;
474
475 regulator_has_full_constraints();
476
477 return 0;
478 }
479
480 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
481 .init = mx31_wm8350_init,
482 .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
483 };
484 #endif
485
486 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
487 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
488 {
489 I2C_BOARD_INFO("wm8350", 0x1a),
490 .platform_data = &mx31_wm8350_pdata,
491 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
492 },
493 #endif
494 };
495
mxc_init_i2c(void)496 static void __init mxc_init_i2c(void)
497 {
498 i2c_register_board_info(1, mx31ads_i2c1_devices,
499 ARRAY_SIZE(mx31ads_i2c1_devices));
500
501 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
502 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
503
504 imx31_add_imx_i2c1(NULL);
505 }
506
507 static unsigned int ssi_pins[] = {
508 MX31_PIN_SFS5__SFS5,
509 MX31_PIN_SCK5__SCK5,
510 MX31_PIN_SRXD5__SRXD5,
511 MX31_PIN_STXD5__STXD5,
512 };
513
mxc_init_audio(void)514 static void __init mxc_init_audio(void)
515 {
516 imx31_add_imx_ssi(0, NULL);
517 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
518 }
519
520 /*
521 * Static mappings, starting from the CS4 start address up to the start address
522 * of the CS8900.
523 */
524 static struct map_desc mx31ads_io_desc[] __initdata = {
525 {
526 .virtual = MX31_CS4_BASE_ADDR_VIRT,
527 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
528 .length = CS4_CS8900_MMIO_START,
529 .type = MT_DEVICE
530 },
531 };
532
mx31ads_map_io(void)533 static void __init mx31ads_map_io(void)
534 {
535 mx31_map_io();
536 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
537 }
538
mx31ads_init_irq(void)539 static void __init mx31ads_init_irq(void)
540 {
541 mx31_init_irq();
542 mx31ads_init_expio();
543 }
544
mx31ads_init(void)545 static void __init mx31ads_init(void)
546 {
547 imx31_soc_init();
548
549 mxc_init_extuart();
550 mxc_init_imx_uart();
551 mxc_init_i2c();
552 mxc_init_audio();
553 mxc_init_ext_ethernet();
554 }
555
mx31ads_timer_init(void)556 static void __init mx31ads_timer_init(void)
557 {
558 mx31_clocks_init(26000000);
559 }
560
561 static struct sys_timer mx31ads_timer = {
562 .init = mx31ads_timer_init,
563 };
564
565 MACHINE_START(MX31ADS, "Freescale MX31ADS")
566 /* Maintainer: Freescale Semiconductor, Inc. */
567 .atag_offset = 0x100,
568 .map_io = mx31ads_map_io,
569 .init_early = imx31_init_early,
570 .init_irq = mx31ads_init_irq,
571 .handle_irq = imx31_handle_irq,
572 .timer = &mx31ads_timer,
573 .init_machine = mx31ads_init,
574 .restart = mxc_restart,
575 MACHINE_END
576