1 /*
2 * OMAP4-specific DPLL control functions
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Rajendra Nayak
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/clk.h>
15 #include <linux/io.h>
16 #include <linux/bitops.h>
17
18 #include <plat/cpu.h>
19 #include <plat/clock.h>
20
21 #include "clock.h"
22 #include "clock44xx.h"
23 #include "cm-regbits-44xx.h"
24
25 /* Supported only on OMAP4 */
omap4_dpllmx_gatectrl_read(struct clk * clk)26 int omap4_dpllmx_gatectrl_read(struct clk *clk)
27 {
28 u32 v;
29 u32 mask;
30
31 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
32 return -EINVAL;
33
34 mask = clk->flags & CLOCK_CLKOUTX2 ?
35 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
36 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
37
38 v = __raw_readl(clk->clksel_reg);
39 v &= mask;
40 v >>= __ffs(mask);
41
42 return v;
43 }
44
omap4_dpllmx_allow_gatectrl(struct clk * clk)45 void omap4_dpllmx_allow_gatectrl(struct clk *clk)
46 {
47 u32 v;
48 u32 mask;
49
50 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
51 return;
52
53 mask = clk->flags & CLOCK_CLKOUTX2 ?
54 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
55 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
56
57 v = __raw_readl(clk->clksel_reg);
58 /* Clear the bit to allow gatectrl */
59 v &= ~mask;
60 __raw_writel(v, clk->clksel_reg);
61 }
62
omap4_dpllmx_deny_gatectrl(struct clk * clk)63 void omap4_dpllmx_deny_gatectrl(struct clk *clk)
64 {
65 u32 v;
66 u32 mask;
67
68 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
69 return;
70
71 mask = clk->flags & CLOCK_CLKOUTX2 ?
72 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
73 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
74
75 v = __raw_readl(clk->clksel_reg);
76 /* Set the bit to deny gatectrl */
77 v |= mask;
78 __raw_writel(v, clk->clksel_reg);
79 }
80
81 const struct clkops clkops_omap4_dpllmx_ops = {
82 .allow_idle = omap4_dpllmx_allow_gatectrl,
83 .deny_idle = omap4_dpllmx_deny_gatectrl,
84 };
85
86 /**
87 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
88 * @clk: struct clk * of the DPLL to compute the rate for
89 *
90 * Compute the output rate for the OMAP4 DPLL represented by @clk.
91 * Takes the REGM4XEN bit into consideration, which is needed for the
92 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
93 * upon success, or 0 upon error.
94 */
omap4_dpll_regm4xen_recalc(struct clk * clk)95 unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
96 {
97 u32 v;
98 unsigned long rate;
99 struct dpll_data *dd;
100
101 if (!clk || !clk->dpll_data)
102 return 0;
103
104 dd = clk->dpll_data;
105
106 rate = omap2_get_dpll_rate(clk);
107
108 /* regm4xen adds a multiplier of 4 to DPLL calculations */
109 v = __raw_readl(dd->control_reg);
110 if (v & OMAP4430_DPLL_REGM4XEN_MASK)
111 rate *= OMAP4430_REGM4XEN_MULT;
112
113 return rate;
114 }
115
116 /**
117 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
118 * @clk: struct clk * of the DPLL to round a rate for
119 * @target_rate: the desired rate of the DPLL
120 *
121 * Compute the rate that would be programmed into the DPLL hardware
122 * for @clk if set_rate() were to be provided with the rate
123 * @target_rate. Takes the REGM4XEN bit into consideration, which is
124 * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
125 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
126 * ~0 if an error occurred in omap2_dpll_round_rate().
127 */
omap4_dpll_regm4xen_round_rate(struct clk * clk,unsigned long target_rate)128 long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
129 {
130 u32 v;
131 struct dpll_data *dd;
132 long r;
133
134 if (!clk || !clk->dpll_data)
135 return -EINVAL;
136
137 dd = clk->dpll_data;
138
139 /* regm4xen adds a multiplier of 4 to DPLL calculations */
140 v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
141
142 if (v)
143 target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
144
145 r = omap2_dpll_round_rate(clk, target_rate);
146 if (r == ~0)
147 return r;
148
149 if (v)
150 clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
151
152 return clk->dpll_data->last_rounded_rate;
153 }
154