1 /*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27 #include "drmP.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
39
40 /* from radeon_encoder.c */
41 extern uint32_t
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46 /* from radeon_connector.c */
47 extern void
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
55
56 /* from radeon_legacy_encoder.c */
57 extern void
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
60
61 /* old legacy ATI BIOS routines */
62
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112 };
113
114 enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122 };
123
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133 };
134
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144 };
145
combios_get_table_offset(struct drm_device * dev,enum radeon_combios_table_offset table)146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148 {
149 struct radeon_device *rdev = dev->dev_private;
150 int rev, size;
151 uint16_t offset = 0, check_offset;
152
153 if (!rdev->bios)
154 return 0;
155
156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = 0xc;
160 break;
161 case COMBIOS_BIOS_SUPPORT_TABLE:
162 check_offset = 0x14;
163 break;
164 case COMBIOS_DAC_PROGRAMMING_TABLE:
165 check_offset = 0x2a;
166 break;
167 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
168 check_offset = 0x2c;
169 break;
170 case COMBIOS_CRTC_INFO_TABLE:
171 check_offset = 0x2e;
172 break;
173 case COMBIOS_PLL_INFO_TABLE:
174 check_offset = 0x30;
175 break;
176 case COMBIOS_TV_INFO_TABLE:
177 check_offset = 0x32;
178 break;
179 case COMBIOS_DFP_INFO_TABLE:
180 check_offset = 0x34;
181 break;
182 case COMBIOS_HW_CONFIG_INFO_TABLE:
183 check_offset = 0x36;
184 break;
185 case COMBIOS_MULTIMEDIA_INFO_TABLE:
186 check_offset = 0x38;
187 break;
188 case COMBIOS_TV_STD_PATCH_TABLE:
189 check_offset = 0x3e;
190 break;
191 case COMBIOS_LCD_INFO_TABLE:
192 check_offset = 0x40;
193 break;
194 case COMBIOS_MOBILE_INFO_TABLE:
195 check_offset = 0x42;
196 break;
197 case COMBIOS_PLL_INIT_TABLE:
198 check_offset = 0x46;
199 break;
200 case COMBIOS_MEM_CONFIG_TABLE:
201 check_offset = 0x48;
202 break;
203 case COMBIOS_SAVE_MASK_TABLE:
204 check_offset = 0x4a;
205 break;
206 case COMBIOS_HARDCODED_EDID_TABLE:
207 check_offset = 0x4c;
208 break;
209 case COMBIOS_ASIC_INIT_2_TABLE:
210 check_offset = 0x4e;
211 break;
212 case COMBIOS_CONNECTOR_INFO_TABLE:
213 check_offset = 0x50;
214 break;
215 case COMBIOS_DYN_CLK_1_TABLE:
216 check_offset = 0x52;
217 break;
218 case COMBIOS_RESERVED_MEM_TABLE:
219 check_offset = 0x54;
220 break;
221 case COMBIOS_EXT_TMDS_INFO_TABLE:
222 check_offset = 0x58;
223 break;
224 case COMBIOS_MEM_CLK_INFO_TABLE:
225 check_offset = 0x5a;
226 break;
227 case COMBIOS_EXT_DAC_INFO_TABLE:
228 check_offset = 0x5c;
229 break;
230 case COMBIOS_MISC_INFO_TABLE:
231 check_offset = 0x5e;
232 break;
233 case COMBIOS_CRT_INFO_TABLE:
234 check_offset = 0x60;
235 break;
236 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
237 check_offset = 0x62;
238 break;
239 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
240 check_offset = 0x64;
241 break;
242 case COMBIOS_FAN_SPEED_INFO_TABLE:
243 check_offset = 0x66;
244 break;
245 case COMBIOS_OVERDRIVE_INFO_TABLE:
246 check_offset = 0x68;
247 break;
248 case COMBIOS_OEM_INFO_TABLE:
249 check_offset = 0x6a;
250 break;
251 case COMBIOS_DYN_CLK_2_TABLE:
252 check_offset = 0x6c;
253 break;
254 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
255 check_offset = 0x6e;
256 break;
257 case COMBIOS_I2C_INFO_TABLE:
258 check_offset = 0x70;
259 break;
260 /* relative offset tables */
261 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
262 check_offset =
263 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
264 if (check_offset) {
265 rev = RBIOS8(check_offset);
266 if (rev > 0) {
267 check_offset = RBIOS16(check_offset + 0x3);
268 if (check_offset)
269 offset = check_offset;
270 }
271 }
272 break;
273 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
274 check_offset =
275 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
276 if (check_offset) {
277 rev = RBIOS8(check_offset);
278 if (rev > 0) {
279 check_offset = RBIOS16(check_offset + 0x5);
280 if (check_offset)
281 offset = check_offset;
282 }
283 }
284 break;
285 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
286 check_offset =
287 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
288 if (check_offset) {
289 rev = RBIOS8(check_offset);
290 if (rev > 0) {
291 check_offset = RBIOS16(check_offset + 0x7);
292 if (check_offset)
293 offset = check_offset;
294 }
295 }
296 break;
297 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
298 check_offset =
299 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
300 if (check_offset) {
301 rev = RBIOS8(check_offset);
302 if (rev == 2) {
303 check_offset = RBIOS16(check_offset + 0x9);
304 if (check_offset)
305 offset = check_offset;
306 }
307 }
308 break;
309 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
310 check_offset =
311 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
312 if (check_offset) {
313 while (RBIOS8(check_offset++));
314 check_offset += 2;
315 if (check_offset)
316 offset = check_offset;
317 }
318 break;
319 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
320 check_offset =
321 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
322 if (check_offset) {
323 check_offset = RBIOS16(check_offset + 0x11);
324 if (check_offset)
325 offset = check_offset;
326 }
327 break;
328 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
329 check_offset =
330 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
331 if (check_offset) {
332 check_offset = RBIOS16(check_offset + 0x13);
333 if (check_offset)
334 offset = check_offset;
335 }
336 break;
337 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
338 check_offset =
339 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
340 if (check_offset) {
341 check_offset = RBIOS16(check_offset + 0x15);
342 if (check_offset)
343 offset = check_offset;
344 }
345 break;
346 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
347 check_offset =
348 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
349 if (check_offset) {
350 check_offset = RBIOS16(check_offset + 0x17);
351 if (check_offset)
352 offset = check_offset;
353 }
354 break;
355 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
356 check_offset =
357 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
358 if (check_offset) {
359 check_offset = RBIOS16(check_offset + 0x2);
360 if (check_offset)
361 offset = check_offset;
362 }
363 break;
364 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
365 check_offset =
366 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
367 if (check_offset) {
368 check_offset = RBIOS16(check_offset + 0x4);
369 if (check_offset)
370 offset = check_offset;
371 }
372 break;
373 default:
374 check_offset = 0;
375 break;
376 }
377
378 size = RBIOS8(rdev->bios_header_start + 0x6);
379 /* check absolute offset tables */
380 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
381 offset = RBIOS16(rdev->bios_header_start + check_offset);
382
383 return offset;
384 }
385
radeon_combios_check_hardcoded_edid(struct radeon_device * rdev)386 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
387 {
388 int edid_info, size;
389 struct edid *edid;
390 unsigned char *raw;
391 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
392 if (!edid_info)
393 return false;
394
395 raw = rdev->bios + edid_info;
396 size = EDID_LENGTH * (raw[0x7e] + 1);
397 edid = kmalloc(size, GFP_KERNEL);
398 if (edid == NULL)
399 return false;
400
401 memcpy((unsigned char *)edid, raw, size);
402
403 if (!drm_edid_is_valid(edid)) {
404 kfree(edid);
405 return false;
406 }
407
408 rdev->mode_info.bios_hardcoded_edid = edid;
409 rdev->mode_info.bios_hardcoded_edid_size = size;
410 return true;
411 }
412
413 /* this is used for atom LCDs as well */
414 struct edid *
radeon_bios_get_hardcoded_edid(struct radeon_device * rdev)415 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
416 {
417 struct edid *edid;
418
419 if (rdev->mode_info.bios_hardcoded_edid) {
420 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
421 if (edid) {
422 memcpy((unsigned char *)edid,
423 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
424 rdev->mode_info.bios_hardcoded_edid_size);
425 return edid;
426 }
427 }
428 return NULL;
429 }
430
combios_setup_i2c_bus(struct radeon_device * rdev,enum radeon_combios_ddc ddc,u32 clk_mask,u32 data_mask)431 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
432 enum radeon_combios_ddc ddc,
433 u32 clk_mask,
434 u32 data_mask)
435 {
436 struct radeon_i2c_bus_rec i2c;
437 int ddc_line = 0;
438
439 /* ddc id = mask reg
440 * DDC_NONE_DETECTED = none
441 * DDC_DVI = RADEON_GPIO_DVI_DDC
442 * DDC_VGA = RADEON_GPIO_VGA_DDC
443 * DDC_LCD = RADEON_GPIOPAD_MASK
444 * DDC_GPIO = RADEON_MDGPIO_MASK
445 * r1xx
446 * DDC_MONID = RADEON_GPIO_MONID
447 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
448 * r200
449 * DDC_MONID = RADEON_GPIO_MONID
450 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
451 * r300/r350
452 * DDC_MONID = RADEON_GPIO_DVI_DDC
453 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
454 * rv2xx/rv3xx
455 * DDC_MONID = RADEON_GPIO_MONID
456 * DDC_CRT2 = RADEON_GPIO_MONID
457 * rs3xx/rs4xx
458 * DDC_MONID = RADEON_GPIOPAD_MASK
459 * DDC_CRT2 = RADEON_GPIO_MONID
460 */
461 switch (ddc) {
462 case DDC_NONE_DETECTED:
463 default:
464 ddc_line = 0;
465 break;
466 case DDC_DVI:
467 ddc_line = RADEON_GPIO_DVI_DDC;
468 break;
469 case DDC_VGA:
470 ddc_line = RADEON_GPIO_VGA_DDC;
471 break;
472 case DDC_LCD:
473 ddc_line = RADEON_GPIOPAD_MASK;
474 break;
475 case DDC_GPIO:
476 ddc_line = RADEON_MDGPIO_MASK;
477 break;
478 case DDC_MONID:
479 if (rdev->family == CHIP_RS300 ||
480 rdev->family == CHIP_RS400 ||
481 rdev->family == CHIP_RS480)
482 ddc_line = RADEON_GPIOPAD_MASK;
483 else if (rdev->family == CHIP_R300 ||
484 rdev->family == CHIP_R350) {
485 ddc_line = RADEON_GPIO_DVI_DDC;
486 ddc = DDC_DVI;
487 } else
488 ddc_line = RADEON_GPIO_MONID;
489 break;
490 case DDC_CRT2:
491 if (rdev->family == CHIP_R200 ||
492 rdev->family == CHIP_R300 ||
493 rdev->family == CHIP_R350) {
494 ddc_line = RADEON_GPIO_DVI_DDC;
495 ddc = DDC_DVI;
496 } else if (rdev->family == CHIP_RS300 ||
497 rdev->family == CHIP_RS400 ||
498 rdev->family == CHIP_RS480)
499 ddc_line = RADEON_GPIO_MONID;
500 else if (rdev->family >= CHIP_RV350) {
501 ddc_line = RADEON_GPIO_MONID;
502 ddc = DDC_MONID;
503 } else
504 ddc_line = RADEON_GPIO_CRT2_DDC;
505 break;
506 }
507
508 if (ddc_line == RADEON_GPIOPAD_MASK) {
509 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
510 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
511 i2c.a_clk_reg = RADEON_GPIOPAD_A;
512 i2c.a_data_reg = RADEON_GPIOPAD_A;
513 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
514 i2c.en_data_reg = RADEON_GPIOPAD_EN;
515 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
516 i2c.y_data_reg = RADEON_GPIOPAD_Y;
517 } else if (ddc_line == RADEON_MDGPIO_MASK) {
518 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
519 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
520 i2c.a_clk_reg = RADEON_MDGPIO_A;
521 i2c.a_data_reg = RADEON_MDGPIO_A;
522 i2c.en_clk_reg = RADEON_MDGPIO_EN;
523 i2c.en_data_reg = RADEON_MDGPIO_EN;
524 i2c.y_clk_reg = RADEON_MDGPIO_Y;
525 i2c.y_data_reg = RADEON_MDGPIO_Y;
526 } else {
527 i2c.mask_clk_reg = ddc_line;
528 i2c.mask_data_reg = ddc_line;
529 i2c.a_clk_reg = ddc_line;
530 i2c.a_data_reg = ddc_line;
531 i2c.en_clk_reg = ddc_line;
532 i2c.en_data_reg = ddc_line;
533 i2c.y_clk_reg = ddc_line;
534 i2c.y_data_reg = ddc_line;
535 }
536
537 if (clk_mask && data_mask) {
538 /* system specific masks */
539 i2c.mask_clk_mask = clk_mask;
540 i2c.mask_data_mask = data_mask;
541 i2c.a_clk_mask = clk_mask;
542 i2c.a_data_mask = data_mask;
543 i2c.en_clk_mask = clk_mask;
544 i2c.en_data_mask = data_mask;
545 i2c.y_clk_mask = clk_mask;
546 i2c.y_data_mask = data_mask;
547 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
548 (ddc_line == RADEON_MDGPIO_MASK)) {
549 /* default gpiopad masks */
550 i2c.mask_clk_mask = (0x20 << 8);
551 i2c.mask_data_mask = 0x80;
552 i2c.a_clk_mask = (0x20 << 8);
553 i2c.a_data_mask = 0x80;
554 i2c.en_clk_mask = (0x20 << 8);
555 i2c.en_data_mask = 0x80;
556 i2c.y_clk_mask = (0x20 << 8);
557 i2c.y_data_mask = 0x80;
558 } else {
559 /* default masks for ddc pads */
560 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
561 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
562 i2c.a_clk_mask = RADEON_GPIO_A_1;
563 i2c.a_data_mask = RADEON_GPIO_A_0;
564 i2c.en_clk_mask = RADEON_GPIO_EN_1;
565 i2c.en_data_mask = RADEON_GPIO_EN_0;
566 i2c.y_clk_mask = RADEON_GPIO_Y_1;
567 i2c.y_data_mask = RADEON_GPIO_Y_0;
568 }
569
570 switch (rdev->family) {
571 case CHIP_R100:
572 case CHIP_RV100:
573 case CHIP_RS100:
574 case CHIP_RV200:
575 case CHIP_RS200:
576 case CHIP_RS300:
577 switch (ddc_line) {
578 case RADEON_GPIO_DVI_DDC:
579 i2c.hw_capable = true;
580 break;
581 default:
582 i2c.hw_capable = false;
583 break;
584 }
585 break;
586 case CHIP_R200:
587 switch (ddc_line) {
588 case RADEON_GPIO_DVI_DDC:
589 case RADEON_GPIO_MONID:
590 i2c.hw_capable = true;
591 break;
592 default:
593 i2c.hw_capable = false;
594 break;
595 }
596 break;
597 case CHIP_RV250:
598 case CHIP_RV280:
599 switch (ddc_line) {
600 case RADEON_GPIO_VGA_DDC:
601 case RADEON_GPIO_DVI_DDC:
602 case RADEON_GPIO_CRT2_DDC:
603 i2c.hw_capable = true;
604 break;
605 default:
606 i2c.hw_capable = false;
607 break;
608 }
609 break;
610 case CHIP_R300:
611 case CHIP_R350:
612 switch (ddc_line) {
613 case RADEON_GPIO_VGA_DDC:
614 case RADEON_GPIO_DVI_DDC:
615 i2c.hw_capable = true;
616 break;
617 default:
618 i2c.hw_capable = false;
619 break;
620 }
621 break;
622 case CHIP_RV350:
623 case CHIP_RV380:
624 case CHIP_RS400:
625 case CHIP_RS480:
626 switch (ddc_line) {
627 case RADEON_GPIO_VGA_DDC:
628 case RADEON_GPIO_DVI_DDC:
629 i2c.hw_capable = true;
630 break;
631 case RADEON_GPIO_MONID:
632 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
633 * reliably on some pre-r4xx hardware; not sure why.
634 */
635 i2c.hw_capable = false;
636 break;
637 default:
638 i2c.hw_capable = false;
639 break;
640 }
641 break;
642 default:
643 i2c.hw_capable = false;
644 break;
645 }
646 i2c.mm_i2c = false;
647
648 i2c.i2c_id = ddc;
649 i2c.hpd = RADEON_HPD_NONE;
650
651 if (ddc_line)
652 i2c.valid = true;
653 else
654 i2c.valid = false;
655
656 return i2c;
657 }
658
radeon_combios_i2c_init(struct radeon_device * rdev)659 void radeon_combios_i2c_init(struct radeon_device *rdev)
660 {
661 struct drm_device *dev = rdev->ddev;
662 struct radeon_i2c_bus_rec i2c;
663
664 /* actual hw pads
665 * r1xx/rs2xx/rs3xx
666 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
667 * r200
668 * 0x60, 0x64, 0x68, mm
669 * r300/r350
670 * 0x60, 0x64, mm
671 * rv2xx/rv3xx/rs4xx
672 * 0x60, 0x64, 0x68, gpiopads, mm
673 */
674
675 /* 0x60 */
676 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
677 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
678 /* 0x64 */
679 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
680 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
681
682 /* mm i2c */
683 i2c.valid = true;
684 i2c.hw_capable = true;
685 i2c.mm_i2c = true;
686 i2c.i2c_id = 0xa0;
687 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
688
689 if (rdev->family == CHIP_R300 ||
690 rdev->family == CHIP_R350) {
691 /* only 2 sw i2c pads */
692 } else if (rdev->family == CHIP_RS300 ||
693 rdev->family == CHIP_RS400 ||
694 rdev->family == CHIP_RS480) {
695 u16 offset;
696 u8 id, blocks, clk, data;
697 int i;
698
699 /* 0x68 */
700 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
701 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
702
703 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
704 if (offset) {
705 blocks = RBIOS8(offset + 2);
706 for (i = 0; i < blocks; i++) {
707 id = RBIOS8(offset + 3 + (i * 5) + 0);
708 if (id == 136) {
709 clk = RBIOS8(offset + 3 + (i * 5) + 3);
710 data = RBIOS8(offset + 3 + (i * 5) + 4);
711 /* gpiopad */
712 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
713 (1 << clk), (1 << data));
714 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
715 break;
716 }
717 }
718 }
719 } else if ((rdev->family == CHIP_R200) ||
720 (rdev->family >= CHIP_R300)) {
721 /* 0x68 */
722 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
723 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
724 } else {
725 /* 0x68 */
726 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
727 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
728 /* 0x6c */
729 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
730 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
731 }
732 }
733
radeon_combios_get_clock_info(struct drm_device * dev)734 bool radeon_combios_get_clock_info(struct drm_device *dev)
735 {
736 struct radeon_device *rdev = dev->dev_private;
737 uint16_t pll_info;
738 struct radeon_pll *p1pll = &rdev->clock.p1pll;
739 struct radeon_pll *p2pll = &rdev->clock.p2pll;
740 struct radeon_pll *spll = &rdev->clock.spll;
741 struct radeon_pll *mpll = &rdev->clock.mpll;
742 int8_t rev;
743 uint16_t sclk, mclk;
744
745 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
746 if (pll_info) {
747 rev = RBIOS8(pll_info);
748
749 /* pixel clocks */
750 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
751 p1pll->reference_div = RBIOS16(pll_info + 0x10);
752 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
753 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
754 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
755 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
756
757 if (rev > 9) {
758 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
759 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
760 } else {
761 p1pll->pll_in_min = 40;
762 p1pll->pll_in_max = 500;
763 }
764 *p2pll = *p1pll;
765
766 /* system clock */
767 spll->reference_freq = RBIOS16(pll_info + 0x1a);
768 spll->reference_div = RBIOS16(pll_info + 0x1c);
769 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
770 spll->pll_out_max = RBIOS32(pll_info + 0x22);
771
772 if (rev > 10) {
773 spll->pll_in_min = RBIOS32(pll_info + 0x48);
774 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
775 } else {
776 /* ??? */
777 spll->pll_in_min = 40;
778 spll->pll_in_max = 500;
779 }
780
781 /* memory clock */
782 mpll->reference_freq = RBIOS16(pll_info + 0x26);
783 mpll->reference_div = RBIOS16(pll_info + 0x28);
784 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
785 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
786
787 if (rev > 10) {
788 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
789 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
790 } else {
791 /* ??? */
792 mpll->pll_in_min = 40;
793 mpll->pll_in_max = 500;
794 }
795
796 /* default sclk/mclk */
797 sclk = RBIOS16(pll_info + 0xa);
798 mclk = RBIOS16(pll_info + 0x8);
799 if (sclk == 0)
800 sclk = 200 * 100;
801 if (mclk == 0)
802 mclk = 200 * 100;
803
804 rdev->clock.default_sclk = sclk;
805 rdev->clock.default_mclk = mclk;
806
807 if (RBIOS32(pll_info + 0x16))
808 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
809 else
810 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
811
812 return true;
813 }
814 return false;
815 }
816
radeon_combios_sideport_present(struct radeon_device * rdev)817 bool radeon_combios_sideport_present(struct radeon_device *rdev)
818 {
819 struct drm_device *dev = rdev->ddev;
820 u16 igp_info;
821
822 /* sideport is AMD only */
823 if (rdev->family == CHIP_RS400)
824 return false;
825
826 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
827
828 if (igp_info) {
829 if (RBIOS16(igp_info + 0x4))
830 return true;
831 }
832 return false;
833 }
834
835 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
836 0x00000808, /* r100 */
837 0x00000808, /* rv100 */
838 0x00000808, /* rs100 */
839 0x00000808, /* rv200 */
840 0x00000808, /* rs200 */
841 0x00000808, /* r200 */
842 0x00000808, /* rv250 */
843 0x00000000, /* rs300 */
844 0x00000808, /* rv280 */
845 0x00000808, /* r300 */
846 0x00000808, /* r350 */
847 0x00000808, /* rv350 */
848 0x00000808, /* rv380 */
849 0x00000808, /* r420 */
850 0x00000808, /* r423 */
851 0x00000808, /* rv410 */
852 0x00000000, /* rs400 */
853 0x00000000, /* rs480 */
854 };
855
radeon_legacy_get_primary_dac_info_from_table(struct radeon_device * rdev,struct radeon_encoder_primary_dac * p_dac)856 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
857 struct radeon_encoder_primary_dac *p_dac)
858 {
859 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
860 return;
861 }
862
radeon_combios_get_primary_dac_info(struct radeon_encoder * encoder)863 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
864 radeon_encoder
865 *encoder)
866 {
867 struct drm_device *dev = encoder->base.dev;
868 struct radeon_device *rdev = dev->dev_private;
869 uint16_t dac_info;
870 uint8_t rev, bg, dac;
871 struct radeon_encoder_primary_dac *p_dac = NULL;
872 int found = 0;
873
874 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
875 GFP_KERNEL);
876
877 if (!p_dac)
878 return NULL;
879
880 /* check CRT table */
881 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
882 if (dac_info) {
883 rev = RBIOS8(dac_info) & 0x3;
884 if (rev < 2) {
885 bg = RBIOS8(dac_info + 0x2) & 0xf;
886 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
887 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
888 } else {
889 bg = RBIOS8(dac_info + 0x2) & 0xf;
890 dac = RBIOS8(dac_info + 0x3) & 0xf;
891 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
892 }
893 /* if the values are zeros, use the table */
894 if ((dac == 0) || (bg == 0))
895 found = 0;
896 else
897 found = 1;
898 }
899
900 /* quirks */
901 /* Radeon 9100 (R200) */
902 if ((dev->pdev->device == 0x514D) &&
903 (dev->pdev->subsystem_vendor == 0x174B) &&
904 (dev->pdev->subsystem_device == 0x7149)) {
905 /* vbios value is bad, use the default */
906 found = 0;
907 }
908
909 if (!found) /* fallback to defaults */
910 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
911
912 return p_dac;
913 }
914
915 enum radeon_tv_std
radeon_combios_get_tv_info(struct radeon_device * rdev)916 radeon_combios_get_tv_info(struct radeon_device *rdev)
917 {
918 struct drm_device *dev = rdev->ddev;
919 uint16_t tv_info;
920 enum radeon_tv_std tv_std = TV_STD_NTSC;
921
922 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
923 if (tv_info) {
924 if (RBIOS8(tv_info + 6) == 'T') {
925 switch (RBIOS8(tv_info + 7) & 0xf) {
926 case 1:
927 tv_std = TV_STD_NTSC;
928 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
929 break;
930 case 2:
931 tv_std = TV_STD_PAL;
932 DRM_DEBUG_KMS("Default TV standard: PAL\n");
933 break;
934 case 3:
935 tv_std = TV_STD_PAL_M;
936 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
937 break;
938 case 4:
939 tv_std = TV_STD_PAL_60;
940 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
941 break;
942 case 5:
943 tv_std = TV_STD_NTSC_J;
944 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
945 break;
946 case 6:
947 tv_std = TV_STD_SCART_PAL;
948 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
949 break;
950 default:
951 tv_std = TV_STD_NTSC;
952 DRM_DEBUG_KMS
953 ("Unknown TV standard; defaulting to NTSC\n");
954 break;
955 }
956
957 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
958 case 0:
959 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
960 break;
961 case 1:
962 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
963 break;
964 case 2:
965 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
966 break;
967 case 3:
968 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
969 break;
970 default:
971 break;
972 }
973 }
974 }
975 return tv_std;
976 }
977
978 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
979 0x00000000, /* r100 */
980 0x00280000, /* rv100 */
981 0x00000000, /* rs100 */
982 0x00880000, /* rv200 */
983 0x00000000, /* rs200 */
984 0x00000000, /* r200 */
985 0x00770000, /* rv250 */
986 0x00290000, /* rs300 */
987 0x00560000, /* rv280 */
988 0x00780000, /* r300 */
989 0x00770000, /* r350 */
990 0x00780000, /* rv350 */
991 0x00780000, /* rv380 */
992 0x01080000, /* r420 */
993 0x01080000, /* r423 */
994 0x01080000, /* rv410 */
995 0x00780000, /* rs400 */
996 0x00780000, /* rs480 */
997 };
998
radeon_legacy_get_tv_dac_info_from_table(struct radeon_device * rdev,struct radeon_encoder_tv_dac * tv_dac)999 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1000 struct radeon_encoder_tv_dac *tv_dac)
1001 {
1002 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1003 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1004 tv_dac->ps2_tvdac_adj = 0x00880000;
1005 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1006 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1007 return;
1008 }
1009
radeon_combios_get_tv_dac_info(struct radeon_encoder * encoder)1010 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1011 radeon_encoder
1012 *encoder)
1013 {
1014 struct drm_device *dev = encoder->base.dev;
1015 struct radeon_device *rdev = dev->dev_private;
1016 uint16_t dac_info;
1017 uint8_t rev, bg, dac;
1018 struct radeon_encoder_tv_dac *tv_dac = NULL;
1019 int found = 0;
1020
1021 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1022 if (!tv_dac)
1023 return NULL;
1024
1025 /* first check TV table */
1026 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1027 if (dac_info) {
1028 rev = RBIOS8(dac_info + 0x3);
1029 if (rev > 4) {
1030 bg = RBIOS8(dac_info + 0xc) & 0xf;
1031 dac = RBIOS8(dac_info + 0xd) & 0xf;
1032 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1033
1034 bg = RBIOS8(dac_info + 0xe) & 0xf;
1035 dac = RBIOS8(dac_info + 0xf) & 0xf;
1036 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1037
1038 bg = RBIOS8(dac_info + 0x10) & 0xf;
1039 dac = RBIOS8(dac_info + 0x11) & 0xf;
1040 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1041 /* if the values are all zeros, use the table */
1042 if (tv_dac->ps2_tvdac_adj)
1043 found = 1;
1044 } else if (rev > 1) {
1045 bg = RBIOS8(dac_info + 0xc) & 0xf;
1046 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1047 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1048
1049 bg = RBIOS8(dac_info + 0xd) & 0xf;
1050 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1051 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1052
1053 bg = RBIOS8(dac_info + 0xe) & 0xf;
1054 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1055 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1056 /* if the values are all zeros, use the table */
1057 if (tv_dac->ps2_tvdac_adj)
1058 found = 1;
1059 }
1060 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1061 }
1062 if (!found) {
1063 /* then check CRT table */
1064 dac_info =
1065 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1066 if (dac_info) {
1067 rev = RBIOS8(dac_info) & 0x3;
1068 if (rev < 2) {
1069 bg = RBIOS8(dac_info + 0x3) & 0xf;
1070 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1071 tv_dac->ps2_tvdac_adj =
1072 (bg << 16) | (dac << 20);
1073 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1074 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1075 /* if the values are all zeros, use the table */
1076 if (tv_dac->ps2_tvdac_adj)
1077 found = 1;
1078 } else {
1079 bg = RBIOS8(dac_info + 0x4) & 0xf;
1080 dac = RBIOS8(dac_info + 0x5) & 0xf;
1081 tv_dac->ps2_tvdac_adj =
1082 (bg << 16) | (dac << 20);
1083 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1084 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1085 /* if the values are all zeros, use the table */
1086 if (tv_dac->ps2_tvdac_adj)
1087 found = 1;
1088 }
1089 } else {
1090 DRM_INFO("No TV DAC info found in BIOS\n");
1091 }
1092 }
1093
1094 if (!found) /* fallback to defaults */
1095 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1096
1097 return tv_dac;
1098 }
1099
radeon_legacy_get_lvds_info_from_regs(struct radeon_device * rdev)1100 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1101 radeon_device
1102 *rdev)
1103 {
1104 struct radeon_encoder_lvds *lvds = NULL;
1105 uint32_t fp_vert_stretch, fp_horz_stretch;
1106 uint32_t ppll_div_sel, ppll_val;
1107 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1108
1109 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1110
1111 if (!lvds)
1112 return NULL;
1113
1114 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1115 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1116
1117 /* These should be fail-safe defaults, fingers crossed */
1118 lvds->panel_pwr_delay = 200;
1119 lvds->panel_vcc_delay = 2000;
1120
1121 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1122 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1123 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1124
1125 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1126 lvds->native_mode.vdisplay =
1127 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1128 RADEON_VERT_PANEL_SHIFT) + 1;
1129 else
1130 lvds->native_mode.vdisplay =
1131 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1132
1133 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1134 lvds->native_mode.hdisplay =
1135 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1136 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1137 else
1138 lvds->native_mode.hdisplay =
1139 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1140
1141 if ((lvds->native_mode.hdisplay < 640) ||
1142 (lvds->native_mode.vdisplay < 480)) {
1143 lvds->native_mode.hdisplay = 640;
1144 lvds->native_mode.vdisplay = 480;
1145 }
1146
1147 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1148 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1149 if ((ppll_val & 0x000707ff) == 0x1bb)
1150 lvds->use_bios_dividers = false;
1151 else {
1152 lvds->panel_ref_divider =
1153 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1154 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1155 lvds->panel_fb_divider = ppll_val & 0x7ff;
1156
1157 if ((lvds->panel_ref_divider != 0) &&
1158 (lvds->panel_fb_divider > 3))
1159 lvds->use_bios_dividers = true;
1160 }
1161 lvds->panel_vcc_delay = 200;
1162
1163 DRM_INFO("Panel info derived from registers\n");
1164 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1165 lvds->native_mode.vdisplay);
1166
1167 return lvds;
1168 }
1169
radeon_combios_get_lvds_info(struct radeon_encoder * encoder)1170 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1171 *encoder)
1172 {
1173 struct drm_device *dev = encoder->base.dev;
1174 struct radeon_device *rdev = dev->dev_private;
1175 uint16_t lcd_info;
1176 uint32_t panel_setup;
1177 char stmp[30];
1178 int tmp, i;
1179 struct radeon_encoder_lvds *lvds = NULL;
1180
1181 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1182
1183 if (lcd_info) {
1184 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1185
1186 if (!lvds)
1187 return NULL;
1188
1189 for (i = 0; i < 24; i++)
1190 stmp[i] = RBIOS8(lcd_info + i + 1);
1191 stmp[24] = 0;
1192
1193 DRM_INFO("Panel ID String: %s\n", stmp);
1194
1195 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1196 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1197
1198 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1199 lvds->native_mode.vdisplay);
1200
1201 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1202 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1203
1204 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1205 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1206 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1207
1208 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1209 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1210 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1211 if ((lvds->panel_ref_divider != 0) &&
1212 (lvds->panel_fb_divider > 3))
1213 lvds->use_bios_dividers = true;
1214
1215 panel_setup = RBIOS32(lcd_info + 0x39);
1216 lvds->lvds_gen_cntl = 0xff00;
1217 if (panel_setup & 0x1)
1218 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1219
1220 if ((panel_setup >> 4) & 0x1)
1221 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1222
1223 switch ((panel_setup >> 8) & 0x7) {
1224 case 0:
1225 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1226 break;
1227 case 1:
1228 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1229 break;
1230 case 2:
1231 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1232 break;
1233 default:
1234 break;
1235 }
1236
1237 if ((panel_setup >> 16) & 0x1)
1238 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1239
1240 if ((panel_setup >> 17) & 0x1)
1241 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1242
1243 if ((panel_setup >> 18) & 0x1)
1244 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1245
1246 if ((panel_setup >> 23) & 0x1)
1247 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1248
1249 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1250
1251 for (i = 0; i < 32; i++) {
1252 tmp = RBIOS16(lcd_info + 64 + i * 2);
1253 if (tmp == 0)
1254 break;
1255
1256 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1257 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1258 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1259 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1260 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1261 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1262 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1263 (RBIOS8(tmp + 23) * 8);
1264
1265 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1266 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1267 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1268 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1269 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1270 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1271
1272 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1273 lvds->native_mode.flags = 0;
1274 /* set crtc values */
1275 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1276
1277 }
1278 }
1279 } else {
1280 DRM_INFO("No panel info found in BIOS\n");
1281 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1282 }
1283
1284 if (lvds)
1285 encoder->native_mode = lvds->native_mode;
1286 return lvds;
1287 }
1288
1289 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1290 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1291 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1292 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1293 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1294 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1295 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1296 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1297 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1298 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1299 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1300 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1301 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1302 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1303 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1306 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1307 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1308 };
1309
radeon_legacy_get_tmds_info_from_table(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1310 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1311 struct radeon_encoder_int_tmds *tmds)
1312 {
1313 struct drm_device *dev = encoder->base.dev;
1314 struct radeon_device *rdev = dev->dev_private;
1315 int i;
1316
1317 for (i = 0; i < 4; i++) {
1318 tmds->tmds_pll[i].value =
1319 default_tmds_pll[rdev->family][i].value;
1320 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1321 }
1322
1323 return true;
1324 }
1325
radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1326 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1327 struct radeon_encoder_int_tmds *tmds)
1328 {
1329 struct drm_device *dev = encoder->base.dev;
1330 struct radeon_device *rdev = dev->dev_private;
1331 uint16_t tmds_info;
1332 int i, n;
1333 uint8_t ver;
1334
1335 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1336
1337 if (tmds_info) {
1338 ver = RBIOS8(tmds_info);
1339 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1340 if (ver == 3) {
1341 n = RBIOS8(tmds_info + 5) + 1;
1342 if (n > 4)
1343 n = 4;
1344 for (i = 0; i < n; i++) {
1345 tmds->tmds_pll[i].value =
1346 RBIOS32(tmds_info + i * 10 + 0x08);
1347 tmds->tmds_pll[i].freq =
1348 RBIOS16(tmds_info + i * 10 + 0x10);
1349 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1350 tmds->tmds_pll[i].freq,
1351 tmds->tmds_pll[i].value);
1352 }
1353 } else if (ver == 4) {
1354 int stride = 0;
1355 n = RBIOS8(tmds_info + 5) + 1;
1356 if (n > 4)
1357 n = 4;
1358 for (i = 0; i < n; i++) {
1359 tmds->tmds_pll[i].value =
1360 RBIOS32(tmds_info + stride + 0x08);
1361 tmds->tmds_pll[i].freq =
1362 RBIOS16(tmds_info + stride + 0x10);
1363 if (i == 0)
1364 stride += 10;
1365 else
1366 stride += 6;
1367 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1368 tmds->tmds_pll[i].freq,
1369 tmds->tmds_pll[i].value);
1370 }
1371 }
1372 } else {
1373 DRM_INFO("No TMDS info found in BIOS\n");
1374 return false;
1375 }
1376 return true;
1377 }
1378
radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder * encoder,struct radeon_encoder_ext_tmds * tmds)1379 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1380 struct radeon_encoder_ext_tmds *tmds)
1381 {
1382 struct drm_device *dev = encoder->base.dev;
1383 struct radeon_device *rdev = dev->dev_private;
1384 struct radeon_i2c_bus_rec i2c_bus;
1385
1386 /* default for macs */
1387 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1388 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1389
1390 /* XXX some macs have duallink chips */
1391 switch (rdev->mode_info.connector_table) {
1392 case CT_POWERBOOK_EXTERNAL:
1393 case CT_MINI_EXTERNAL:
1394 default:
1395 tmds->dvo_chip = DVO_SIL164;
1396 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1397 break;
1398 }
1399
1400 return true;
1401 }
1402
radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder * encoder,struct radeon_encoder_ext_tmds * tmds)1403 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1404 struct radeon_encoder_ext_tmds *tmds)
1405 {
1406 struct drm_device *dev = encoder->base.dev;
1407 struct radeon_device *rdev = dev->dev_private;
1408 uint16_t offset;
1409 uint8_t ver;
1410 enum radeon_combios_ddc gpio;
1411 struct radeon_i2c_bus_rec i2c_bus;
1412
1413 tmds->i2c_bus = NULL;
1414 if (rdev->flags & RADEON_IS_IGP) {
1415 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1416 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1417 tmds->dvo_chip = DVO_SIL164;
1418 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1419 } else {
1420 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1421 if (offset) {
1422 ver = RBIOS8(offset);
1423 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1424 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1425 tmds->slave_addr >>= 1; /* 7 bit addressing */
1426 gpio = RBIOS8(offset + 4 + 3);
1427 if (gpio == DDC_LCD) {
1428 /* MM i2c */
1429 i2c_bus.valid = true;
1430 i2c_bus.hw_capable = true;
1431 i2c_bus.mm_i2c = true;
1432 i2c_bus.i2c_id = 0xa0;
1433 } else
1434 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1435 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1436 }
1437 }
1438
1439 if (!tmds->i2c_bus) {
1440 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1441 return false;
1442 }
1443
1444 return true;
1445 }
1446
radeon_get_legacy_connector_info_from_table(struct drm_device * dev)1447 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1448 {
1449 struct radeon_device *rdev = dev->dev_private;
1450 struct radeon_i2c_bus_rec ddc_i2c;
1451 struct radeon_hpd hpd;
1452
1453 rdev->mode_info.connector_table = radeon_connector_table;
1454 if (rdev->mode_info.connector_table == CT_NONE) {
1455 #ifdef CONFIG_PPC_PMAC
1456 if (of_machine_is_compatible("PowerBook3,3")) {
1457 /* powerbook with VGA */
1458 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1459 } else if (of_machine_is_compatible("PowerBook3,4") ||
1460 of_machine_is_compatible("PowerBook3,5")) {
1461 /* powerbook with internal tmds */
1462 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1463 } else if (of_machine_is_compatible("PowerBook5,1") ||
1464 of_machine_is_compatible("PowerBook5,2") ||
1465 of_machine_is_compatible("PowerBook5,3") ||
1466 of_machine_is_compatible("PowerBook5,4") ||
1467 of_machine_is_compatible("PowerBook5,5")) {
1468 /* powerbook with external single link tmds (sil164) */
1469 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1470 } else if (of_machine_is_compatible("PowerBook5,6")) {
1471 /* powerbook with external dual or single link tmds */
1472 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1473 } else if (of_machine_is_compatible("PowerBook5,7") ||
1474 of_machine_is_compatible("PowerBook5,8") ||
1475 of_machine_is_compatible("PowerBook5,9")) {
1476 /* PowerBook6,2 ? */
1477 /* powerbook with external dual link tmds (sil1178?) */
1478 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1479 } else if (of_machine_is_compatible("PowerBook4,1") ||
1480 of_machine_is_compatible("PowerBook4,2") ||
1481 of_machine_is_compatible("PowerBook4,3") ||
1482 of_machine_is_compatible("PowerBook6,3") ||
1483 of_machine_is_compatible("PowerBook6,5") ||
1484 of_machine_is_compatible("PowerBook6,7")) {
1485 /* ibook */
1486 rdev->mode_info.connector_table = CT_IBOOK;
1487 } else if (of_machine_is_compatible("PowerMac4,4")) {
1488 /* emac */
1489 rdev->mode_info.connector_table = CT_EMAC;
1490 } else if (of_machine_is_compatible("PowerMac10,1")) {
1491 /* mini with internal tmds */
1492 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1493 } else if (of_machine_is_compatible("PowerMac10,2")) {
1494 /* mini with external tmds */
1495 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1496 } else if (of_machine_is_compatible("PowerMac12,1")) {
1497 /* PowerMac8,1 ? */
1498 /* imac g5 isight */
1499 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1500 } else if ((rdev->pdev->device == 0x4a48) &&
1501 (rdev->pdev->subsystem_vendor == 0x1002) &&
1502 (rdev->pdev->subsystem_device == 0x4a48)) {
1503 /* Mac X800 */
1504 rdev->mode_info.connector_table = CT_MAC_X800;
1505 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1506 of_machine_is_compatible("PowerMac7,3")) &&
1507 (rdev->pdev->device == 0x4150) &&
1508 (rdev->pdev->subsystem_vendor == 0x1002) &&
1509 (rdev->pdev->subsystem_device == 0x4150)) {
1510 /* Mac G5 tower 9600 */
1511 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1512 } else
1513 #endif /* CONFIG_PPC_PMAC */
1514 #ifdef CONFIG_PPC64
1515 if (ASIC_IS_RN50(rdev))
1516 rdev->mode_info.connector_table = CT_RN50_POWER;
1517 else
1518 #endif
1519 rdev->mode_info.connector_table = CT_GENERIC;
1520 }
1521
1522 switch (rdev->mode_info.connector_table) {
1523 case CT_GENERIC:
1524 DRM_INFO("Connector Table: %d (generic)\n",
1525 rdev->mode_info.connector_table);
1526 /* these are the most common settings */
1527 if (rdev->flags & RADEON_SINGLE_CRTC) {
1528 /* VGA - primary dac */
1529 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1530 hpd.hpd = RADEON_HPD_NONE;
1531 radeon_add_legacy_encoder(dev,
1532 radeon_get_encoder_enum(dev,
1533 ATOM_DEVICE_CRT1_SUPPORT,
1534 1),
1535 ATOM_DEVICE_CRT1_SUPPORT);
1536 radeon_add_legacy_connector(dev, 0,
1537 ATOM_DEVICE_CRT1_SUPPORT,
1538 DRM_MODE_CONNECTOR_VGA,
1539 &ddc_i2c,
1540 CONNECTOR_OBJECT_ID_VGA,
1541 &hpd);
1542 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1543 /* LVDS */
1544 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1545 hpd.hpd = RADEON_HPD_NONE;
1546 radeon_add_legacy_encoder(dev,
1547 radeon_get_encoder_enum(dev,
1548 ATOM_DEVICE_LCD1_SUPPORT,
1549 0),
1550 ATOM_DEVICE_LCD1_SUPPORT);
1551 radeon_add_legacy_connector(dev, 0,
1552 ATOM_DEVICE_LCD1_SUPPORT,
1553 DRM_MODE_CONNECTOR_LVDS,
1554 &ddc_i2c,
1555 CONNECTOR_OBJECT_ID_LVDS,
1556 &hpd);
1557
1558 /* VGA - primary dac */
1559 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1560 hpd.hpd = RADEON_HPD_NONE;
1561 radeon_add_legacy_encoder(dev,
1562 radeon_get_encoder_enum(dev,
1563 ATOM_DEVICE_CRT1_SUPPORT,
1564 1),
1565 ATOM_DEVICE_CRT1_SUPPORT);
1566 radeon_add_legacy_connector(dev, 1,
1567 ATOM_DEVICE_CRT1_SUPPORT,
1568 DRM_MODE_CONNECTOR_VGA,
1569 &ddc_i2c,
1570 CONNECTOR_OBJECT_ID_VGA,
1571 &hpd);
1572 } else {
1573 /* DVI-I - tv dac, int tmds */
1574 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1575 hpd.hpd = RADEON_HPD_1;
1576 radeon_add_legacy_encoder(dev,
1577 radeon_get_encoder_enum(dev,
1578 ATOM_DEVICE_DFP1_SUPPORT,
1579 0),
1580 ATOM_DEVICE_DFP1_SUPPORT);
1581 radeon_add_legacy_encoder(dev,
1582 radeon_get_encoder_enum(dev,
1583 ATOM_DEVICE_CRT2_SUPPORT,
1584 2),
1585 ATOM_DEVICE_CRT2_SUPPORT);
1586 radeon_add_legacy_connector(dev, 0,
1587 ATOM_DEVICE_DFP1_SUPPORT |
1588 ATOM_DEVICE_CRT2_SUPPORT,
1589 DRM_MODE_CONNECTOR_DVII,
1590 &ddc_i2c,
1591 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1592 &hpd);
1593
1594 /* VGA - primary dac */
1595 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1596 hpd.hpd = RADEON_HPD_NONE;
1597 radeon_add_legacy_encoder(dev,
1598 radeon_get_encoder_enum(dev,
1599 ATOM_DEVICE_CRT1_SUPPORT,
1600 1),
1601 ATOM_DEVICE_CRT1_SUPPORT);
1602 radeon_add_legacy_connector(dev, 1,
1603 ATOM_DEVICE_CRT1_SUPPORT,
1604 DRM_MODE_CONNECTOR_VGA,
1605 &ddc_i2c,
1606 CONNECTOR_OBJECT_ID_VGA,
1607 &hpd);
1608 }
1609
1610 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1611 /* TV - tv dac */
1612 ddc_i2c.valid = false;
1613 hpd.hpd = RADEON_HPD_NONE;
1614 radeon_add_legacy_encoder(dev,
1615 radeon_get_encoder_enum(dev,
1616 ATOM_DEVICE_TV1_SUPPORT,
1617 2),
1618 ATOM_DEVICE_TV1_SUPPORT);
1619 radeon_add_legacy_connector(dev, 2,
1620 ATOM_DEVICE_TV1_SUPPORT,
1621 DRM_MODE_CONNECTOR_SVIDEO,
1622 &ddc_i2c,
1623 CONNECTOR_OBJECT_ID_SVIDEO,
1624 &hpd);
1625 }
1626 break;
1627 case CT_IBOOK:
1628 DRM_INFO("Connector Table: %d (ibook)\n",
1629 rdev->mode_info.connector_table);
1630 /* LVDS */
1631 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1632 hpd.hpd = RADEON_HPD_NONE;
1633 radeon_add_legacy_encoder(dev,
1634 radeon_get_encoder_enum(dev,
1635 ATOM_DEVICE_LCD1_SUPPORT,
1636 0),
1637 ATOM_DEVICE_LCD1_SUPPORT);
1638 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1639 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1640 CONNECTOR_OBJECT_ID_LVDS,
1641 &hpd);
1642 /* VGA - TV DAC */
1643 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1644 hpd.hpd = RADEON_HPD_NONE;
1645 radeon_add_legacy_encoder(dev,
1646 radeon_get_encoder_enum(dev,
1647 ATOM_DEVICE_CRT2_SUPPORT,
1648 2),
1649 ATOM_DEVICE_CRT2_SUPPORT);
1650 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1651 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1652 CONNECTOR_OBJECT_ID_VGA,
1653 &hpd);
1654 /* TV - TV DAC */
1655 ddc_i2c.valid = false;
1656 hpd.hpd = RADEON_HPD_NONE;
1657 radeon_add_legacy_encoder(dev,
1658 radeon_get_encoder_enum(dev,
1659 ATOM_DEVICE_TV1_SUPPORT,
1660 2),
1661 ATOM_DEVICE_TV1_SUPPORT);
1662 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1663 DRM_MODE_CONNECTOR_SVIDEO,
1664 &ddc_i2c,
1665 CONNECTOR_OBJECT_ID_SVIDEO,
1666 &hpd);
1667 break;
1668 case CT_POWERBOOK_EXTERNAL:
1669 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1670 rdev->mode_info.connector_table);
1671 /* LVDS */
1672 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1673 hpd.hpd = RADEON_HPD_NONE;
1674 radeon_add_legacy_encoder(dev,
1675 radeon_get_encoder_enum(dev,
1676 ATOM_DEVICE_LCD1_SUPPORT,
1677 0),
1678 ATOM_DEVICE_LCD1_SUPPORT);
1679 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1680 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1681 CONNECTOR_OBJECT_ID_LVDS,
1682 &hpd);
1683 /* DVI-I - primary dac, ext tmds */
1684 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1685 hpd.hpd = RADEON_HPD_2; /* ??? */
1686 radeon_add_legacy_encoder(dev,
1687 radeon_get_encoder_enum(dev,
1688 ATOM_DEVICE_DFP2_SUPPORT,
1689 0),
1690 ATOM_DEVICE_DFP2_SUPPORT);
1691 radeon_add_legacy_encoder(dev,
1692 radeon_get_encoder_enum(dev,
1693 ATOM_DEVICE_CRT1_SUPPORT,
1694 1),
1695 ATOM_DEVICE_CRT1_SUPPORT);
1696 /* XXX some are SL */
1697 radeon_add_legacy_connector(dev, 1,
1698 ATOM_DEVICE_DFP2_SUPPORT |
1699 ATOM_DEVICE_CRT1_SUPPORT,
1700 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1701 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1702 &hpd);
1703 /* TV - TV DAC */
1704 ddc_i2c.valid = false;
1705 hpd.hpd = RADEON_HPD_NONE;
1706 radeon_add_legacy_encoder(dev,
1707 radeon_get_encoder_enum(dev,
1708 ATOM_DEVICE_TV1_SUPPORT,
1709 2),
1710 ATOM_DEVICE_TV1_SUPPORT);
1711 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1712 DRM_MODE_CONNECTOR_SVIDEO,
1713 &ddc_i2c,
1714 CONNECTOR_OBJECT_ID_SVIDEO,
1715 &hpd);
1716 break;
1717 case CT_POWERBOOK_INTERNAL:
1718 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1719 rdev->mode_info.connector_table);
1720 /* LVDS */
1721 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1722 hpd.hpd = RADEON_HPD_NONE;
1723 radeon_add_legacy_encoder(dev,
1724 radeon_get_encoder_enum(dev,
1725 ATOM_DEVICE_LCD1_SUPPORT,
1726 0),
1727 ATOM_DEVICE_LCD1_SUPPORT);
1728 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1729 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1730 CONNECTOR_OBJECT_ID_LVDS,
1731 &hpd);
1732 /* DVI-I - primary dac, int tmds */
1733 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1734 hpd.hpd = RADEON_HPD_1; /* ??? */
1735 radeon_add_legacy_encoder(dev,
1736 radeon_get_encoder_enum(dev,
1737 ATOM_DEVICE_DFP1_SUPPORT,
1738 0),
1739 ATOM_DEVICE_DFP1_SUPPORT);
1740 radeon_add_legacy_encoder(dev,
1741 radeon_get_encoder_enum(dev,
1742 ATOM_DEVICE_CRT1_SUPPORT,
1743 1),
1744 ATOM_DEVICE_CRT1_SUPPORT);
1745 radeon_add_legacy_connector(dev, 1,
1746 ATOM_DEVICE_DFP1_SUPPORT |
1747 ATOM_DEVICE_CRT1_SUPPORT,
1748 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1749 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1750 &hpd);
1751 /* TV - TV DAC */
1752 ddc_i2c.valid = false;
1753 hpd.hpd = RADEON_HPD_NONE;
1754 radeon_add_legacy_encoder(dev,
1755 radeon_get_encoder_enum(dev,
1756 ATOM_DEVICE_TV1_SUPPORT,
1757 2),
1758 ATOM_DEVICE_TV1_SUPPORT);
1759 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1760 DRM_MODE_CONNECTOR_SVIDEO,
1761 &ddc_i2c,
1762 CONNECTOR_OBJECT_ID_SVIDEO,
1763 &hpd);
1764 break;
1765 case CT_POWERBOOK_VGA:
1766 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1767 rdev->mode_info.connector_table);
1768 /* LVDS */
1769 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1770 hpd.hpd = RADEON_HPD_NONE;
1771 radeon_add_legacy_encoder(dev,
1772 radeon_get_encoder_enum(dev,
1773 ATOM_DEVICE_LCD1_SUPPORT,
1774 0),
1775 ATOM_DEVICE_LCD1_SUPPORT);
1776 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1777 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1778 CONNECTOR_OBJECT_ID_LVDS,
1779 &hpd);
1780 /* VGA - primary dac */
1781 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1782 hpd.hpd = RADEON_HPD_NONE;
1783 radeon_add_legacy_encoder(dev,
1784 radeon_get_encoder_enum(dev,
1785 ATOM_DEVICE_CRT1_SUPPORT,
1786 1),
1787 ATOM_DEVICE_CRT1_SUPPORT);
1788 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1789 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1790 CONNECTOR_OBJECT_ID_VGA,
1791 &hpd);
1792 /* TV - TV DAC */
1793 ddc_i2c.valid = false;
1794 hpd.hpd = RADEON_HPD_NONE;
1795 radeon_add_legacy_encoder(dev,
1796 radeon_get_encoder_enum(dev,
1797 ATOM_DEVICE_TV1_SUPPORT,
1798 2),
1799 ATOM_DEVICE_TV1_SUPPORT);
1800 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1801 DRM_MODE_CONNECTOR_SVIDEO,
1802 &ddc_i2c,
1803 CONNECTOR_OBJECT_ID_SVIDEO,
1804 &hpd);
1805 break;
1806 case CT_MINI_EXTERNAL:
1807 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1808 rdev->mode_info.connector_table);
1809 /* DVI-I - tv dac, ext tmds */
1810 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1811 hpd.hpd = RADEON_HPD_2; /* ??? */
1812 radeon_add_legacy_encoder(dev,
1813 radeon_get_encoder_enum(dev,
1814 ATOM_DEVICE_DFP2_SUPPORT,
1815 0),
1816 ATOM_DEVICE_DFP2_SUPPORT);
1817 radeon_add_legacy_encoder(dev,
1818 radeon_get_encoder_enum(dev,
1819 ATOM_DEVICE_CRT2_SUPPORT,
1820 2),
1821 ATOM_DEVICE_CRT2_SUPPORT);
1822 /* XXX are any DL? */
1823 radeon_add_legacy_connector(dev, 0,
1824 ATOM_DEVICE_DFP2_SUPPORT |
1825 ATOM_DEVICE_CRT2_SUPPORT,
1826 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1827 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1828 &hpd);
1829 /* TV - TV DAC */
1830 ddc_i2c.valid = false;
1831 hpd.hpd = RADEON_HPD_NONE;
1832 radeon_add_legacy_encoder(dev,
1833 radeon_get_encoder_enum(dev,
1834 ATOM_DEVICE_TV1_SUPPORT,
1835 2),
1836 ATOM_DEVICE_TV1_SUPPORT);
1837 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1838 DRM_MODE_CONNECTOR_SVIDEO,
1839 &ddc_i2c,
1840 CONNECTOR_OBJECT_ID_SVIDEO,
1841 &hpd);
1842 break;
1843 case CT_MINI_INTERNAL:
1844 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1845 rdev->mode_info.connector_table);
1846 /* DVI-I - tv dac, int tmds */
1847 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1848 hpd.hpd = RADEON_HPD_1; /* ??? */
1849 radeon_add_legacy_encoder(dev,
1850 radeon_get_encoder_enum(dev,
1851 ATOM_DEVICE_DFP1_SUPPORT,
1852 0),
1853 ATOM_DEVICE_DFP1_SUPPORT);
1854 radeon_add_legacy_encoder(dev,
1855 radeon_get_encoder_enum(dev,
1856 ATOM_DEVICE_CRT2_SUPPORT,
1857 2),
1858 ATOM_DEVICE_CRT2_SUPPORT);
1859 radeon_add_legacy_connector(dev, 0,
1860 ATOM_DEVICE_DFP1_SUPPORT |
1861 ATOM_DEVICE_CRT2_SUPPORT,
1862 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1863 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1864 &hpd);
1865 /* TV - TV DAC */
1866 ddc_i2c.valid = false;
1867 hpd.hpd = RADEON_HPD_NONE;
1868 radeon_add_legacy_encoder(dev,
1869 radeon_get_encoder_enum(dev,
1870 ATOM_DEVICE_TV1_SUPPORT,
1871 2),
1872 ATOM_DEVICE_TV1_SUPPORT);
1873 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1874 DRM_MODE_CONNECTOR_SVIDEO,
1875 &ddc_i2c,
1876 CONNECTOR_OBJECT_ID_SVIDEO,
1877 &hpd);
1878 break;
1879 case CT_IMAC_G5_ISIGHT:
1880 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1881 rdev->mode_info.connector_table);
1882 /* DVI-D - int tmds */
1883 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1884 hpd.hpd = RADEON_HPD_1; /* ??? */
1885 radeon_add_legacy_encoder(dev,
1886 radeon_get_encoder_enum(dev,
1887 ATOM_DEVICE_DFP1_SUPPORT,
1888 0),
1889 ATOM_DEVICE_DFP1_SUPPORT);
1890 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1891 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1892 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1893 &hpd);
1894 /* VGA - tv dac */
1895 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1896 hpd.hpd = RADEON_HPD_NONE;
1897 radeon_add_legacy_encoder(dev,
1898 radeon_get_encoder_enum(dev,
1899 ATOM_DEVICE_CRT2_SUPPORT,
1900 2),
1901 ATOM_DEVICE_CRT2_SUPPORT);
1902 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1903 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1904 CONNECTOR_OBJECT_ID_VGA,
1905 &hpd);
1906 /* TV - TV DAC */
1907 ddc_i2c.valid = false;
1908 hpd.hpd = RADEON_HPD_NONE;
1909 radeon_add_legacy_encoder(dev,
1910 radeon_get_encoder_enum(dev,
1911 ATOM_DEVICE_TV1_SUPPORT,
1912 2),
1913 ATOM_DEVICE_TV1_SUPPORT);
1914 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1915 DRM_MODE_CONNECTOR_SVIDEO,
1916 &ddc_i2c,
1917 CONNECTOR_OBJECT_ID_SVIDEO,
1918 &hpd);
1919 break;
1920 case CT_EMAC:
1921 DRM_INFO("Connector Table: %d (emac)\n",
1922 rdev->mode_info.connector_table);
1923 /* VGA - primary dac */
1924 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1925 hpd.hpd = RADEON_HPD_NONE;
1926 radeon_add_legacy_encoder(dev,
1927 radeon_get_encoder_enum(dev,
1928 ATOM_DEVICE_CRT1_SUPPORT,
1929 1),
1930 ATOM_DEVICE_CRT1_SUPPORT);
1931 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1932 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1933 CONNECTOR_OBJECT_ID_VGA,
1934 &hpd);
1935 /* VGA - tv dac */
1936 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1937 hpd.hpd = RADEON_HPD_NONE;
1938 radeon_add_legacy_encoder(dev,
1939 radeon_get_encoder_enum(dev,
1940 ATOM_DEVICE_CRT2_SUPPORT,
1941 2),
1942 ATOM_DEVICE_CRT2_SUPPORT);
1943 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1944 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1945 CONNECTOR_OBJECT_ID_VGA,
1946 &hpd);
1947 /* TV - TV DAC */
1948 ddc_i2c.valid = false;
1949 hpd.hpd = RADEON_HPD_NONE;
1950 radeon_add_legacy_encoder(dev,
1951 radeon_get_encoder_enum(dev,
1952 ATOM_DEVICE_TV1_SUPPORT,
1953 2),
1954 ATOM_DEVICE_TV1_SUPPORT);
1955 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1956 DRM_MODE_CONNECTOR_SVIDEO,
1957 &ddc_i2c,
1958 CONNECTOR_OBJECT_ID_SVIDEO,
1959 &hpd);
1960 break;
1961 case CT_RN50_POWER:
1962 DRM_INFO("Connector Table: %d (rn50-power)\n",
1963 rdev->mode_info.connector_table);
1964 /* VGA - primary dac */
1965 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1966 hpd.hpd = RADEON_HPD_NONE;
1967 radeon_add_legacy_encoder(dev,
1968 radeon_get_encoder_enum(dev,
1969 ATOM_DEVICE_CRT1_SUPPORT,
1970 1),
1971 ATOM_DEVICE_CRT1_SUPPORT);
1972 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1973 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1974 CONNECTOR_OBJECT_ID_VGA,
1975 &hpd);
1976 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1977 hpd.hpd = RADEON_HPD_NONE;
1978 radeon_add_legacy_encoder(dev,
1979 radeon_get_encoder_enum(dev,
1980 ATOM_DEVICE_CRT2_SUPPORT,
1981 2),
1982 ATOM_DEVICE_CRT2_SUPPORT);
1983 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1984 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1985 CONNECTOR_OBJECT_ID_VGA,
1986 &hpd);
1987 break;
1988 case CT_MAC_X800:
1989 DRM_INFO("Connector Table: %d (mac x800)\n",
1990 rdev->mode_info.connector_table);
1991 /* DVI - primary dac, internal tmds */
1992 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1993 hpd.hpd = RADEON_HPD_1; /* ??? */
1994 radeon_add_legacy_encoder(dev,
1995 radeon_get_encoder_enum(dev,
1996 ATOM_DEVICE_DFP1_SUPPORT,
1997 0),
1998 ATOM_DEVICE_DFP1_SUPPORT);
1999 radeon_add_legacy_encoder(dev,
2000 radeon_get_encoder_enum(dev,
2001 ATOM_DEVICE_CRT1_SUPPORT,
2002 1),
2003 ATOM_DEVICE_CRT1_SUPPORT);
2004 radeon_add_legacy_connector(dev, 0,
2005 ATOM_DEVICE_DFP1_SUPPORT |
2006 ATOM_DEVICE_CRT1_SUPPORT,
2007 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2008 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2009 &hpd);
2010 /* DVI - tv dac, dvo */
2011 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2012 hpd.hpd = RADEON_HPD_2; /* ??? */
2013 radeon_add_legacy_encoder(dev,
2014 radeon_get_encoder_enum(dev,
2015 ATOM_DEVICE_DFP2_SUPPORT,
2016 0),
2017 ATOM_DEVICE_DFP2_SUPPORT);
2018 radeon_add_legacy_encoder(dev,
2019 radeon_get_encoder_enum(dev,
2020 ATOM_DEVICE_CRT2_SUPPORT,
2021 2),
2022 ATOM_DEVICE_CRT2_SUPPORT);
2023 radeon_add_legacy_connector(dev, 1,
2024 ATOM_DEVICE_DFP2_SUPPORT |
2025 ATOM_DEVICE_CRT2_SUPPORT,
2026 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2027 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2028 &hpd);
2029 break;
2030 case CT_MAC_G5_9600:
2031 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2032 rdev->mode_info.connector_table);
2033 /* DVI - tv dac, dvo */
2034 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2035 hpd.hpd = RADEON_HPD_1; /* ??? */
2036 radeon_add_legacy_encoder(dev,
2037 radeon_get_encoder_enum(dev,
2038 ATOM_DEVICE_DFP2_SUPPORT,
2039 0),
2040 ATOM_DEVICE_DFP2_SUPPORT);
2041 radeon_add_legacy_encoder(dev,
2042 radeon_get_encoder_enum(dev,
2043 ATOM_DEVICE_CRT2_SUPPORT,
2044 2),
2045 ATOM_DEVICE_CRT2_SUPPORT);
2046 radeon_add_legacy_connector(dev, 0,
2047 ATOM_DEVICE_DFP2_SUPPORT |
2048 ATOM_DEVICE_CRT2_SUPPORT,
2049 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2050 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2051 &hpd);
2052 /* ADC - primary dac, internal tmds */
2053 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2054 hpd.hpd = RADEON_HPD_2; /* ??? */
2055 radeon_add_legacy_encoder(dev,
2056 radeon_get_encoder_enum(dev,
2057 ATOM_DEVICE_DFP1_SUPPORT,
2058 0),
2059 ATOM_DEVICE_DFP1_SUPPORT);
2060 radeon_add_legacy_encoder(dev,
2061 radeon_get_encoder_enum(dev,
2062 ATOM_DEVICE_CRT1_SUPPORT,
2063 1),
2064 ATOM_DEVICE_CRT1_SUPPORT);
2065 radeon_add_legacy_connector(dev, 1,
2066 ATOM_DEVICE_DFP1_SUPPORT |
2067 ATOM_DEVICE_CRT1_SUPPORT,
2068 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2069 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2070 &hpd);
2071 /* TV - TV DAC */
2072 ddc_i2c.valid = false;
2073 hpd.hpd = RADEON_HPD_NONE;
2074 radeon_add_legacy_encoder(dev,
2075 radeon_get_encoder_enum(dev,
2076 ATOM_DEVICE_TV1_SUPPORT,
2077 2),
2078 ATOM_DEVICE_TV1_SUPPORT);
2079 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2080 DRM_MODE_CONNECTOR_SVIDEO,
2081 &ddc_i2c,
2082 CONNECTOR_OBJECT_ID_SVIDEO,
2083 &hpd);
2084 break;
2085 default:
2086 DRM_INFO("Connector table: %d (invalid)\n",
2087 rdev->mode_info.connector_table);
2088 return false;
2089 }
2090
2091 radeon_link_encoder_connector(dev);
2092
2093 return true;
2094 }
2095
radeon_apply_legacy_quirks(struct drm_device * dev,int bios_index,enum radeon_combios_connector * legacy_connector,struct radeon_i2c_bus_rec * ddc_i2c,struct radeon_hpd * hpd)2096 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2097 int bios_index,
2098 enum radeon_combios_connector
2099 *legacy_connector,
2100 struct radeon_i2c_bus_rec *ddc_i2c,
2101 struct radeon_hpd *hpd)
2102 {
2103
2104 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2105 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2106 if (dev->pdev->device == 0x515e &&
2107 dev->pdev->subsystem_vendor == 0x1014) {
2108 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2109 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2110 return false;
2111 }
2112
2113 /* X300 card with extra non-existent DVI port */
2114 if (dev->pdev->device == 0x5B60 &&
2115 dev->pdev->subsystem_vendor == 0x17af &&
2116 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2117 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2118 return false;
2119 }
2120
2121 return true;
2122 }
2123
radeon_apply_legacy_tv_quirks(struct drm_device * dev)2124 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2125 {
2126 /* Acer 5102 has non-existent TV port */
2127 if (dev->pdev->device == 0x5975 &&
2128 dev->pdev->subsystem_vendor == 0x1025 &&
2129 dev->pdev->subsystem_device == 0x009f)
2130 return false;
2131
2132 /* HP dc5750 has non-existent TV port */
2133 if (dev->pdev->device == 0x5974 &&
2134 dev->pdev->subsystem_vendor == 0x103c &&
2135 dev->pdev->subsystem_device == 0x280a)
2136 return false;
2137
2138 /* MSI S270 has non-existent TV port */
2139 if (dev->pdev->device == 0x5955 &&
2140 dev->pdev->subsystem_vendor == 0x1462 &&
2141 dev->pdev->subsystem_device == 0x0131)
2142 return false;
2143
2144 return true;
2145 }
2146
combios_check_dl_dvi(struct drm_device * dev,int is_dvi_d)2147 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2148 {
2149 struct radeon_device *rdev = dev->dev_private;
2150 uint32_t ext_tmds_info;
2151
2152 if (rdev->flags & RADEON_IS_IGP) {
2153 if (is_dvi_d)
2154 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2155 else
2156 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2157 }
2158 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2159 if (ext_tmds_info) {
2160 uint8_t rev = RBIOS8(ext_tmds_info);
2161 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2162 if (rev >= 3) {
2163 if (is_dvi_d)
2164 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2165 else
2166 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2167 } else {
2168 if (flags & 1) {
2169 if (is_dvi_d)
2170 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2171 else
2172 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2173 }
2174 }
2175 }
2176 if (is_dvi_d)
2177 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2178 else
2179 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2180 }
2181
radeon_get_legacy_connector_info_from_bios(struct drm_device * dev)2182 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2183 {
2184 struct radeon_device *rdev = dev->dev_private;
2185 uint32_t conn_info, entry, devices;
2186 uint16_t tmp, connector_object_id;
2187 enum radeon_combios_ddc ddc_type;
2188 enum radeon_combios_connector connector;
2189 int i = 0;
2190 struct radeon_i2c_bus_rec ddc_i2c;
2191 struct radeon_hpd hpd;
2192
2193 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2194 if (conn_info) {
2195 for (i = 0; i < 4; i++) {
2196 entry = conn_info + 2 + i * 2;
2197
2198 if (!RBIOS16(entry))
2199 break;
2200
2201 tmp = RBIOS16(entry);
2202
2203 connector = (tmp >> 12) & 0xf;
2204
2205 ddc_type = (tmp >> 8) & 0xf;
2206 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2207
2208 switch (connector) {
2209 case CONNECTOR_PROPRIETARY_LEGACY:
2210 case CONNECTOR_DVI_I_LEGACY:
2211 case CONNECTOR_DVI_D_LEGACY:
2212 if ((tmp >> 4) & 0x1)
2213 hpd.hpd = RADEON_HPD_2;
2214 else
2215 hpd.hpd = RADEON_HPD_1;
2216 break;
2217 default:
2218 hpd.hpd = RADEON_HPD_NONE;
2219 break;
2220 }
2221
2222 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2223 &ddc_i2c, &hpd))
2224 continue;
2225
2226 switch (connector) {
2227 case CONNECTOR_PROPRIETARY_LEGACY:
2228 if ((tmp >> 4) & 0x1)
2229 devices = ATOM_DEVICE_DFP2_SUPPORT;
2230 else
2231 devices = ATOM_DEVICE_DFP1_SUPPORT;
2232 radeon_add_legacy_encoder(dev,
2233 radeon_get_encoder_enum
2234 (dev, devices, 0),
2235 devices);
2236 radeon_add_legacy_connector(dev, i, devices,
2237 legacy_connector_convert
2238 [connector],
2239 &ddc_i2c,
2240 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2241 &hpd);
2242 break;
2243 case CONNECTOR_CRT_LEGACY:
2244 if (tmp & 0x1) {
2245 devices = ATOM_DEVICE_CRT2_SUPPORT;
2246 radeon_add_legacy_encoder(dev,
2247 radeon_get_encoder_enum
2248 (dev,
2249 ATOM_DEVICE_CRT2_SUPPORT,
2250 2),
2251 ATOM_DEVICE_CRT2_SUPPORT);
2252 } else {
2253 devices = ATOM_DEVICE_CRT1_SUPPORT;
2254 radeon_add_legacy_encoder(dev,
2255 radeon_get_encoder_enum
2256 (dev,
2257 ATOM_DEVICE_CRT1_SUPPORT,
2258 1),
2259 ATOM_DEVICE_CRT1_SUPPORT);
2260 }
2261 radeon_add_legacy_connector(dev,
2262 i,
2263 devices,
2264 legacy_connector_convert
2265 [connector],
2266 &ddc_i2c,
2267 CONNECTOR_OBJECT_ID_VGA,
2268 &hpd);
2269 break;
2270 case CONNECTOR_DVI_I_LEGACY:
2271 devices = 0;
2272 if (tmp & 0x1) {
2273 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2274 radeon_add_legacy_encoder(dev,
2275 radeon_get_encoder_enum
2276 (dev,
2277 ATOM_DEVICE_CRT2_SUPPORT,
2278 2),
2279 ATOM_DEVICE_CRT2_SUPPORT);
2280 } else {
2281 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2282 radeon_add_legacy_encoder(dev,
2283 radeon_get_encoder_enum
2284 (dev,
2285 ATOM_DEVICE_CRT1_SUPPORT,
2286 1),
2287 ATOM_DEVICE_CRT1_SUPPORT);
2288 }
2289 /* RV100 board with external TDMS bit mis-set.
2290 * Actually uses internal TMDS, clear the bit.
2291 */
2292 if (dev->pdev->device == 0x5159 &&
2293 dev->pdev->subsystem_vendor == 0x1014 &&
2294 dev->pdev->subsystem_device == 0x029A) {
2295 tmp &= ~(1 << 4);
2296 }
2297 if ((tmp >> 4) & 0x1) {
2298 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2299 radeon_add_legacy_encoder(dev,
2300 radeon_get_encoder_enum
2301 (dev,
2302 ATOM_DEVICE_DFP2_SUPPORT,
2303 0),
2304 ATOM_DEVICE_DFP2_SUPPORT);
2305 connector_object_id = combios_check_dl_dvi(dev, 0);
2306 } else {
2307 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2308 radeon_add_legacy_encoder(dev,
2309 radeon_get_encoder_enum
2310 (dev,
2311 ATOM_DEVICE_DFP1_SUPPORT,
2312 0),
2313 ATOM_DEVICE_DFP1_SUPPORT);
2314 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2315 }
2316 radeon_add_legacy_connector(dev,
2317 i,
2318 devices,
2319 legacy_connector_convert
2320 [connector],
2321 &ddc_i2c,
2322 connector_object_id,
2323 &hpd);
2324 break;
2325 case CONNECTOR_DVI_D_LEGACY:
2326 if ((tmp >> 4) & 0x1) {
2327 devices = ATOM_DEVICE_DFP2_SUPPORT;
2328 connector_object_id = combios_check_dl_dvi(dev, 1);
2329 } else {
2330 devices = ATOM_DEVICE_DFP1_SUPPORT;
2331 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2332 }
2333 radeon_add_legacy_encoder(dev,
2334 radeon_get_encoder_enum
2335 (dev, devices, 0),
2336 devices);
2337 radeon_add_legacy_connector(dev, i, devices,
2338 legacy_connector_convert
2339 [connector],
2340 &ddc_i2c,
2341 connector_object_id,
2342 &hpd);
2343 break;
2344 case CONNECTOR_CTV_LEGACY:
2345 case CONNECTOR_STV_LEGACY:
2346 radeon_add_legacy_encoder(dev,
2347 radeon_get_encoder_enum
2348 (dev,
2349 ATOM_DEVICE_TV1_SUPPORT,
2350 2),
2351 ATOM_DEVICE_TV1_SUPPORT);
2352 radeon_add_legacy_connector(dev, i,
2353 ATOM_DEVICE_TV1_SUPPORT,
2354 legacy_connector_convert
2355 [connector],
2356 &ddc_i2c,
2357 CONNECTOR_OBJECT_ID_SVIDEO,
2358 &hpd);
2359 break;
2360 default:
2361 DRM_ERROR("Unknown connector type: %d\n",
2362 connector);
2363 continue;
2364 }
2365
2366 }
2367 } else {
2368 uint16_t tmds_info =
2369 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2370 if (tmds_info) {
2371 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2372
2373 radeon_add_legacy_encoder(dev,
2374 radeon_get_encoder_enum(dev,
2375 ATOM_DEVICE_CRT1_SUPPORT,
2376 1),
2377 ATOM_DEVICE_CRT1_SUPPORT);
2378 radeon_add_legacy_encoder(dev,
2379 radeon_get_encoder_enum(dev,
2380 ATOM_DEVICE_DFP1_SUPPORT,
2381 0),
2382 ATOM_DEVICE_DFP1_SUPPORT);
2383
2384 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2385 hpd.hpd = RADEON_HPD_1;
2386 radeon_add_legacy_connector(dev,
2387 0,
2388 ATOM_DEVICE_CRT1_SUPPORT |
2389 ATOM_DEVICE_DFP1_SUPPORT,
2390 DRM_MODE_CONNECTOR_DVII,
2391 &ddc_i2c,
2392 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2393 &hpd);
2394 } else {
2395 uint16_t crt_info =
2396 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2397 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2398 if (crt_info) {
2399 radeon_add_legacy_encoder(dev,
2400 radeon_get_encoder_enum(dev,
2401 ATOM_DEVICE_CRT1_SUPPORT,
2402 1),
2403 ATOM_DEVICE_CRT1_SUPPORT);
2404 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2405 hpd.hpd = RADEON_HPD_NONE;
2406 radeon_add_legacy_connector(dev,
2407 0,
2408 ATOM_DEVICE_CRT1_SUPPORT,
2409 DRM_MODE_CONNECTOR_VGA,
2410 &ddc_i2c,
2411 CONNECTOR_OBJECT_ID_VGA,
2412 &hpd);
2413 } else {
2414 DRM_DEBUG_KMS("No connector info found\n");
2415 return false;
2416 }
2417 }
2418 }
2419
2420 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2421 uint16_t lcd_info =
2422 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2423 if (lcd_info) {
2424 uint16_t lcd_ddc_info =
2425 combios_get_table_offset(dev,
2426 COMBIOS_LCD_DDC_INFO_TABLE);
2427
2428 radeon_add_legacy_encoder(dev,
2429 radeon_get_encoder_enum(dev,
2430 ATOM_DEVICE_LCD1_SUPPORT,
2431 0),
2432 ATOM_DEVICE_LCD1_SUPPORT);
2433
2434 if (lcd_ddc_info) {
2435 ddc_type = RBIOS8(lcd_ddc_info + 2);
2436 switch (ddc_type) {
2437 case DDC_LCD:
2438 ddc_i2c =
2439 combios_setup_i2c_bus(rdev,
2440 DDC_LCD,
2441 RBIOS32(lcd_ddc_info + 3),
2442 RBIOS32(lcd_ddc_info + 7));
2443 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2444 break;
2445 case DDC_GPIO:
2446 ddc_i2c =
2447 combios_setup_i2c_bus(rdev,
2448 DDC_GPIO,
2449 RBIOS32(lcd_ddc_info + 3),
2450 RBIOS32(lcd_ddc_info + 7));
2451 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2452 break;
2453 default:
2454 ddc_i2c =
2455 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2456 break;
2457 }
2458 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2459 } else
2460 ddc_i2c.valid = false;
2461
2462 hpd.hpd = RADEON_HPD_NONE;
2463 radeon_add_legacy_connector(dev,
2464 5,
2465 ATOM_DEVICE_LCD1_SUPPORT,
2466 DRM_MODE_CONNECTOR_LVDS,
2467 &ddc_i2c,
2468 CONNECTOR_OBJECT_ID_LVDS,
2469 &hpd);
2470 }
2471 }
2472
2473 /* check TV table */
2474 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2475 uint32_t tv_info =
2476 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2477 if (tv_info) {
2478 if (RBIOS8(tv_info + 6) == 'T') {
2479 if (radeon_apply_legacy_tv_quirks(dev)) {
2480 hpd.hpd = RADEON_HPD_NONE;
2481 ddc_i2c.valid = false;
2482 radeon_add_legacy_encoder(dev,
2483 radeon_get_encoder_enum
2484 (dev,
2485 ATOM_DEVICE_TV1_SUPPORT,
2486 2),
2487 ATOM_DEVICE_TV1_SUPPORT);
2488 radeon_add_legacy_connector(dev, 6,
2489 ATOM_DEVICE_TV1_SUPPORT,
2490 DRM_MODE_CONNECTOR_SVIDEO,
2491 &ddc_i2c,
2492 CONNECTOR_OBJECT_ID_SVIDEO,
2493 &hpd);
2494 }
2495 }
2496 }
2497 }
2498
2499 radeon_link_encoder_connector(dev);
2500
2501 return true;
2502 }
2503
2504 static const char *thermal_controller_names[] = {
2505 "NONE",
2506 "lm63",
2507 "adm1032",
2508 };
2509
radeon_combios_get_power_modes(struct radeon_device * rdev)2510 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2511 {
2512 struct drm_device *dev = rdev->ddev;
2513 u16 offset, misc, misc2 = 0;
2514 u8 rev, blocks, tmp;
2515 int state_index = 0;
2516 struct radeon_i2c_bus_rec i2c_bus;
2517
2518 rdev->pm.default_power_state_index = -1;
2519
2520 /* allocate 2 power states */
2521 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2522 if (rdev->pm.power_state) {
2523 /* allocate 1 clock mode per state */
2524 rdev->pm.power_state[0].clock_info =
2525 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2526 rdev->pm.power_state[1].clock_info =
2527 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2528 if (!rdev->pm.power_state[0].clock_info ||
2529 !rdev->pm.power_state[1].clock_info)
2530 goto pm_failed;
2531 } else
2532 goto pm_failed;
2533
2534 /* check for a thermal chip */
2535 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2536 if (offset) {
2537 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2538
2539 rev = RBIOS8(offset);
2540
2541 if (rev == 0) {
2542 thermal_controller = RBIOS8(offset + 3);
2543 gpio = RBIOS8(offset + 4) & 0x3f;
2544 i2c_addr = RBIOS8(offset + 5);
2545 } else if (rev == 1) {
2546 thermal_controller = RBIOS8(offset + 4);
2547 gpio = RBIOS8(offset + 5) & 0x3f;
2548 i2c_addr = RBIOS8(offset + 6);
2549 } else if (rev == 2) {
2550 thermal_controller = RBIOS8(offset + 4);
2551 gpio = RBIOS8(offset + 5) & 0x3f;
2552 i2c_addr = RBIOS8(offset + 6);
2553 clk_bit = RBIOS8(offset + 0xa);
2554 data_bit = RBIOS8(offset + 0xb);
2555 }
2556 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2557 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2558 thermal_controller_names[thermal_controller],
2559 i2c_addr >> 1);
2560 if (gpio == DDC_LCD) {
2561 /* MM i2c */
2562 i2c_bus.valid = true;
2563 i2c_bus.hw_capable = true;
2564 i2c_bus.mm_i2c = true;
2565 i2c_bus.i2c_id = 0xa0;
2566 } else if (gpio == DDC_GPIO)
2567 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2568 else
2569 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2570 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2571 if (rdev->pm.i2c_bus) {
2572 struct i2c_board_info info = { };
2573 const char *name = thermal_controller_names[thermal_controller];
2574 info.addr = i2c_addr >> 1;
2575 strlcpy(info.type, name, sizeof(info.type));
2576 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2577 }
2578 }
2579 } else {
2580 /* boards with a thermal chip, but no overdrive table */
2581
2582 /* Asus 9600xt has an f75375 on the monid bus */
2583 if ((dev->pdev->device == 0x4152) &&
2584 (dev->pdev->subsystem_vendor == 0x1043) &&
2585 (dev->pdev->subsystem_device == 0xc002)) {
2586 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2587 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2588 if (rdev->pm.i2c_bus) {
2589 struct i2c_board_info info = { };
2590 const char *name = "f75375";
2591 info.addr = 0x28;
2592 strlcpy(info.type, name, sizeof(info.type));
2593 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2594 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2595 name, info.addr);
2596 }
2597 }
2598 }
2599
2600 if (rdev->flags & RADEON_IS_MOBILITY) {
2601 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2602 if (offset) {
2603 rev = RBIOS8(offset);
2604 blocks = RBIOS8(offset + 0x2);
2605 /* power mode 0 tends to be the only valid one */
2606 rdev->pm.power_state[state_index].num_clock_modes = 1;
2607 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2608 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2609 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2610 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2611 goto default_mode;
2612 rdev->pm.power_state[state_index].type =
2613 POWER_STATE_TYPE_BATTERY;
2614 misc = RBIOS16(offset + 0x5 + 0x0);
2615 if (rev > 4)
2616 misc2 = RBIOS16(offset + 0x5 + 0xe);
2617 rdev->pm.power_state[state_index].misc = misc;
2618 rdev->pm.power_state[state_index].misc2 = misc2;
2619 if (misc & 0x4) {
2620 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2621 if (misc & 0x8)
2622 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2623 true;
2624 else
2625 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2626 false;
2627 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2628 if (rev < 6) {
2629 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2630 RBIOS16(offset + 0x5 + 0xb) * 4;
2631 tmp = RBIOS8(offset + 0x5 + 0xd);
2632 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2633 } else {
2634 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2635 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2636 if (entries && voltage_table_offset) {
2637 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2638 RBIOS16(voltage_table_offset) * 4;
2639 tmp = RBIOS8(voltage_table_offset + 0x2);
2640 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2641 } else
2642 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2643 }
2644 switch ((misc2 & 0x700) >> 8) {
2645 case 0:
2646 default:
2647 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2648 break;
2649 case 1:
2650 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2651 break;
2652 case 2:
2653 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2654 break;
2655 case 3:
2656 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2657 break;
2658 case 4:
2659 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2660 break;
2661 }
2662 } else
2663 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2664 if (rev > 6)
2665 rdev->pm.power_state[state_index].pcie_lanes =
2666 RBIOS8(offset + 0x5 + 0x10);
2667 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2668 state_index++;
2669 } else {
2670 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2671 }
2672 } else {
2673 /* XXX figure out some good default low power mode for desktop cards */
2674 }
2675
2676 default_mode:
2677 /* add the default mode */
2678 rdev->pm.power_state[state_index].type =
2679 POWER_STATE_TYPE_DEFAULT;
2680 rdev->pm.power_state[state_index].num_clock_modes = 1;
2681 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2682 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2683 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2684 if ((state_index > 0) &&
2685 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2686 rdev->pm.power_state[state_index].clock_info[0].voltage =
2687 rdev->pm.power_state[0].clock_info[0].voltage;
2688 else
2689 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2690 rdev->pm.power_state[state_index].pcie_lanes = 16;
2691 rdev->pm.power_state[state_index].flags = 0;
2692 rdev->pm.default_power_state_index = state_index;
2693 rdev->pm.num_power_states = state_index + 1;
2694
2695 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2696 rdev->pm.current_clock_mode_index = 0;
2697 return;
2698
2699 pm_failed:
2700 rdev->pm.default_power_state_index = state_index;
2701 rdev->pm.num_power_states = 0;
2702
2703 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2704 rdev->pm.current_clock_mode_index = 0;
2705 }
2706
radeon_external_tmds_setup(struct drm_encoder * encoder)2707 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2708 {
2709 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2710 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2711
2712 if (!tmds)
2713 return;
2714
2715 switch (tmds->dvo_chip) {
2716 case DVO_SIL164:
2717 /* sil 164 */
2718 radeon_i2c_put_byte(tmds->i2c_bus,
2719 tmds->slave_addr,
2720 0x08, 0x30);
2721 radeon_i2c_put_byte(tmds->i2c_bus,
2722 tmds->slave_addr,
2723 0x09, 0x00);
2724 radeon_i2c_put_byte(tmds->i2c_bus,
2725 tmds->slave_addr,
2726 0x0a, 0x90);
2727 radeon_i2c_put_byte(tmds->i2c_bus,
2728 tmds->slave_addr,
2729 0x0c, 0x89);
2730 radeon_i2c_put_byte(tmds->i2c_bus,
2731 tmds->slave_addr,
2732 0x08, 0x3b);
2733 break;
2734 case DVO_SIL1178:
2735 /* sil 1178 - untested */
2736 /*
2737 * 0x0f, 0x44
2738 * 0x0f, 0x4c
2739 * 0x0e, 0x01
2740 * 0x0a, 0x80
2741 * 0x09, 0x30
2742 * 0x0c, 0xc9
2743 * 0x0d, 0x70
2744 * 0x08, 0x32
2745 * 0x08, 0x33
2746 */
2747 break;
2748 default:
2749 break;
2750 }
2751
2752 }
2753
radeon_combios_external_tmds_setup(struct drm_encoder * encoder)2754 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2755 {
2756 struct drm_device *dev = encoder->dev;
2757 struct radeon_device *rdev = dev->dev_private;
2758 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2759 uint16_t offset;
2760 uint8_t blocks, slave_addr, rev;
2761 uint32_t index, id;
2762 uint32_t reg, val, and_mask, or_mask;
2763 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2764
2765 if (!tmds)
2766 return false;
2767
2768 if (rdev->flags & RADEON_IS_IGP) {
2769 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2770 rev = RBIOS8(offset);
2771 if (offset) {
2772 rev = RBIOS8(offset);
2773 if (rev > 1) {
2774 blocks = RBIOS8(offset + 3);
2775 index = offset + 4;
2776 while (blocks > 0) {
2777 id = RBIOS16(index);
2778 index += 2;
2779 switch (id >> 13) {
2780 case 0:
2781 reg = (id & 0x1fff) * 4;
2782 val = RBIOS32(index);
2783 index += 4;
2784 WREG32(reg, val);
2785 break;
2786 case 2:
2787 reg = (id & 0x1fff) * 4;
2788 and_mask = RBIOS32(index);
2789 index += 4;
2790 or_mask = RBIOS32(index);
2791 index += 4;
2792 val = RREG32(reg);
2793 val = (val & and_mask) | or_mask;
2794 WREG32(reg, val);
2795 break;
2796 case 3:
2797 val = RBIOS16(index);
2798 index += 2;
2799 udelay(val);
2800 break;
2801 case 4:
2802 val = RBIOS16(index);
2803 index += 2;
2804 mdelay(val);
2805 break;
2806 case 6:
2807 slave_addr = id & 0xff;
2808 slave_addr >>= 1; /* 7 bit addressing */
2809 index++;
2810 reg = RBIOS8(index);
2811 index++;
2812 val = RBIOS8(index);
2813 index++;
2814 radeon_i2c_put_byte(tmds->i2c_bus,
2815 slave_addr,
2816 reg, val);
2817 break;
2818 default:
2819 DRM_ERROR("Unknown id %d\n", id >> 13);
2820 break;
2821 }
2822 blocks--;
2823 }
2824 return true;
2825 }
2826 }
2827 } else {
2828 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2829 if (offset) {
2830 index = offset + 10;
2831 id = RBIOS16(index);
2832 while (id != 0xffff) {
2833 index += 2;
2834 switch (id >> 13) {
2835 case 0:
2836 reg = (id & 0x1fff) * 4;
2837 val = RBIOS32(index);
2838 WREG32(reg, val);
2839 break;
2840 case 2:
2841 reg = (id & 0x1fff) * 4;
2842 and_mask = RBIOS32(index);
2843 index += 4;
2844 or_mask = RBIOS32(index);
2845 index += 4;
2846 val = RREG32(reg);
2847 val = (val & and_mask) | or_mask;
2848 WREG32(reg, val);
2849 break;
2850 case 4:
2851 val = RBIOS16(index);
2852 index += 2;
2853 udelay(val);
2854 break;
2855 case 5:
2856 reg = id & 0x1fff;
2857 and_mask = RBIOS32(index);
2858 index += 4;
2859 or_mask = RBIOS32(index);
2860 index += 4;
2861 val = RREG32_PLL(reg);
2862 val = (val & and_mask) | or_mask;
2863 WREG32_PLL(reg, val);
2864 break;
2865 case 6:
2866 reg = id & 0x1fff;
2867 val = RBIOS8(index);
2868 index += 1;
2869 radeon_i2c_put_byte(tmds->i2c_bus,
2870 tmds->slave_addr,
2871 reg, val);
2872 break;
2873 default:
2874 DRM_ERROR("Unknown id %d\n", id >> 13);
2875 break;
2876 }
2877 id = RBIOS16(index);
2878 }
2879 return true;
2880 }
2881 }
2882 return false;
2883 }
2884
combios_parse_mmio_table(struct drm_device * dev,uint16_t offset)2885 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2886 {
2887 struct radeon_device *rdev = dev->dev_private;
2888
2889 if (offset) {
2890 while (RBIOS16(offset)) {
2891 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2892 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2893 uint32_t val, and_mask, or_mask;
2894 uint32_t tmp;
2895
2896 offset += 2;
2897 switch (cmd) {
2898 case 0:
2899 val = RBIOS32(offset);
2900 offset += 4;
2901 WREG32(addr, val);
2902 break;
2903 case 1:
2904 val = RBIOS32(offset);
2905 offset += 4;
2906 WREG32(addr, val);
2907 break;
2908 case 2:
2909 and_mask = RBIOS32(offset);
2910 offset += 4;
2911 or_mask = RBIOS32(offset);
2912 offset += 4;
2913 tmp = RREG32(addr);
2914 tmp &= and_mask;
2915 tmp |= or_mask;
2916 WREG32(addr, tmp);
2917 break;
2918 case 3:
2919 and_mask = RBIOS32(offset);
2920 offset += 4;
2921 or_mask = RBIOS32(offset);
2922 offset += 4;
2923 tmp = RREG32(addr);
2924 tmp &= and_mask;
2925 tmp |= or_mask;
2926 WREG32(addr, tmp);
2927 break;
2928 case 4:
2929 val = RBIOS16(offset);
2930 offset += 2;
2931 udelay(val);
2932 break;
2933 case 5:
2934 val = RBIOS16(offset);
2935 offset += 2;
2936 switch (addr) {
2937 case 8:
2938 while (val--) {
2939 if (!
2940 (RREG32_PLL
2941 (RADEON_CLK_PWRMGT_CNTL) &
2942 RADEON_MC_BUSY))
2943 break;
2944 }
2945 break;
2946 case 9:
2947 while (val--) {
2948 if ((RREG32(RADEON_MC_STATUS) &
2949 RADEON_MC_IDLE))
2950 break;
2951 }
2952 break;
2953 default:
2954 break;
2955 }
2956 break;
2957 default:
2958 break;
2959 }
2960 }
2961 }
2962 }
2963
combios_parse_pll_table(struct drm_device * dev,uint16_t offset)2964 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2965 {
2966 struct radeon_device *rdev = dev->dev_private;
2967
2968 if (offset) {
2969 while (RBIOS8(offset)) {
2970 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2971 uint8_t addr = (RBIOS8(offset) & 0x3f);
2972 uint32_t val, shift, tmp;
2973 uint32_t and_mask, or_mask;
2974
2975 offset++;
2976 switch (cmd) {
2977 case 0:
2978 val = RBIOS32(offset);
2979 offset += 4;
2980 WREG32_PLL(addr, val);
2981 break;
2982 case 1:
2983 shift = RBIOS8(offset) * 8;
2984 offset++;
2985 and_mask = RBIOS8(offset) << shift;
2986 and_mask |= ~(0xff << shift);
2987 offset++;
2988 or_mask = RBIOS8(offset) << shift;
2989 offset++;
2990 tmp = RREG32_PLL(addr);
2991 tmp &= and_mask;
2992 tmp |= or_mask;
2993 WREG32_PLL(addr, tmp);
2994 break;
2995 case 2:
2996 case 3:
2997 tmp = 1000;
2998 switch (addr) {
2999 case 1:
3000 udelay(150);
3001 break;
3002 case 2:
3003 mdelay(1);
3004 break;
3005 case 3:
3006 while (tmp--) {
3007 if (!
3008 (RREG32_PLL
3009 (RADEON_CLK_PWRMGT_CNTL) &
3010 RADEON_MC_BUSY))
3011 break;
3012 }
3013 break;
3014 case 4:
3015 while (tmp--) {
3016 if (RREG32_PLL
3017 (RADEON_CLK_PWRMGT_CNTL) &
3018 RADEON_DLL_READY)
3019 break;
3020 }
3021 break;
3022 case 5:
3023 tmp =
3024 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3025 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3026 #if 0
3027 uint32_t mclk_cntl =
3028 RREG32_PLL
3029 (RADEON_MCLK_CNTL);
3030 mclk_cntl &= 0xffff0000;
3031 /*mclk_cntl |= 0x00001111;*//* ??? */
3032 WREG32_PLL(RADEON_MCLK_CNTL,
3033 mclk_cntl);
3034 mdelay(10);
3035 #endif
3036 WREG32_PLL
3037 (RADEON_CLK_PWRMGT_CNTL,
3038 tmp &
3039 ~RADEON_CG_NO1_DEBUG_0);
3040 mdelay(10);
3041 }
3042 break;
3043 default:
3044 break;
3045 }
3046 break;
3047 default:
3048 break;
3049 }
3050 }
3051 }
3052 }
3053
combios_parse_ram_reset_table(struct drm_device * dev,uint16_t offset)3054 static void combios_parse_ram_reset_table(struct drm_device *dev,
3055 uint16_t offset)
3056 {
3057 struct radeon_device *rdev = dev->dev_private;
3058 uint32_t tmp;
3059
3060 if (offset) {
3061 uint8_t val = RBIOS8(offset);
3062 while (val != 0xff) {
3063 offset++;
3064
3065 if (val == 0x0f) {
3066 uint32_t channel_complete_mask;
3067
3068 if (ASIC_IS_R300(rdev))
3069 channel_complete_mask =
3070 R300_MEM_PWRUP_COMPLETE;
3071 else
3072 channel_complete_mask =
3073 RADEON_MEM_PWRUP_COMPLETE;
3074 tmp = 20000;
3075 while (tmp--) {
3076 if ((RREG32(RADEON_MEM_STR_CNTL) &
3077 channel_complete_mask) ==
3078 channel_complete_mask)
3079 break;
3080 }
3081 } else {
3082 uint32_t or_mask = RBIOS16(offset);
3083 offset += 2;
3084
3085 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3086 tmp &= RADEON_SDRAM_MODE_MASK;
3087 tmp |= or_mask;
3088 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3089
3090 or_mask = val << 24;
3091 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3092 tmp &= RADEON_B3MEM_RESET_MASK;
3093 tmp |= or_mask;
3094 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3095 }
3096 val = RBIOS8(offset);
3097 }
3098 }
3099 }
3100
combios_detect_ram(struct drm_device * dev,int ram,int mem_addr_mapping)3101 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3102 int mem_addr_mapping)
3103 {
3104 struct radeon_device *rdev = dev->dev_private;
3105 uint32_t mem_cntl;
3106 uint32_t mem_size;
3107 uint32_t addr = 0;
3108
3109 mem_cntl = RREG32(RADEON_MEM_CNTL);
3110 if (mem_cntl & RV100_HALF_MODE)
3111 ram /= 2;
3112 mem_size = ram;
3113 mem_cntl &= ~(0xff << 8);
3114 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3115 WREG32(RADEON_MEM_CNTL, mem_cntl);
3116 RREG32(RADEON_MEM_CNTL);
3117
3118 /* sdram reset ? */
3119
3120 /* something like this???? */
3121 while (ram--) {
3122 addr = ram * 1024 * 1024;
3123 /* write to each page */
3124 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3125 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3126 /* read back and verify */
3127 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3128 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3129 return 0;
3130 }
3131
3132 return mem_size;
3133 }
3134
combios_write_ram_size(struct drm_device * dev)3135 static void combios_write_ram_size(struct drm_device *dev)
3136 {
3137 struct radeon_device *rdev = dev->dev_private;
3138 uint8_t rev;
3139 uint16_t offset;
3140 uint32_t mem_size = 0;
3141 uint32_t mem_cntl = 0;
3142
3143 /* should do something smarter here I guess... */
3144 if (rdev->flags & RADEON_IS_IGP)
3145 return;
3146
3147 /* first check detected mem table */
3148 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3149 if (offset) {
3150 rev = RBIOS8(offset);
3151 if (rev < 3) {
3152 mem_cntl = RBIOS32(offset + 1);
3153 mem_size = RBIOS16(offset + 5);
3154 if ((rdev->family < CHIP_R200) &&
3155 !ASIC_IS_RN50(rdev))
3156 WREG32(RADEON_MEM_CNTL, mem_cntl);
3157 }
3158 }
3159
3160 if (!mem_size) {
3161 offset =
3162 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3163 if (offset) {
3164 rev = RBIOS8(offset - 1);
3165 if (rev < 1) {
3166 if ((rdev->family < CHIP_R200)
3167 && !ASIC_IS_RN50(rdev)) {
3168 int ram = 0;
3169 int mem_addr_mapping = 0;
3170
3171 while (RBIOS8(offset)) {
3172 ram = RBIOS8(offset);
3173 mem_addr_mapping =
3174 RBIOS8(offset + 1);
3175 if (mem_addr_mapping != 0x25)
3176 ram *= 2;
3177 mem_size =
3178 combios_detect_ram(dev, ram,
3179 mem_addr_mapping);
3180 if (mem_size)
3181 break;
3182 offset += 2;
3183 }
3184 } else
3185 mem_size = RBIOS8(offset);
3186 } else {
3187 mem_size = RBIOS8(offset);
3188 mem_size *= 2; /* convert to MB */
3189 }
3190 }
3191 }
3192
3193 mem_size *= (1024 * 1024); /* convert to bytes */
3194 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3195 }
3196
radeon_combios_dyn_clk_setup(struct drm_device * dev,int enable)3197 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3198 {
3199 uint16_t dyn_clk_info =
3200 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3201
3202 if (dyn_clk_info)
3203 combios_parse_pll_table(dev, dyn_clk_info);
3204 }
3205
radeon_combios_asic_init(struct drm_device * dev)3206 void radeon_combios_asic_init(struct drm_device *dev)
3207 {
3208 struct radeon_device *rdev = dev->dev_private;
3209 uint16_t table;
3210
3211 /* port hardcoded mac stuff from radeonfb */
3212 if (rdev->bios == NULL)
3213 return;
3214
3215 /* ASIC INIT 1 */
3216 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3217 if (table)
3218 combios_parse_mmio_table(dev, table);
3219
3220 /* PLL INIT */
3221 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3222 if (table)
3223 combios_parse_pll_table(dev, table);
3224
3225 /* ASIC INIT 2 */
3226 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3227 if (table)
3228 combios_parse_mmio_table(dev, table);
3229
3230 if (!(rdev->flags & RADEON_IS_IGP)) {
3231 /* ASIC INIT 4 */
3232 table =
3233 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3234 if (table)
3235 combios_parse_mmio_table(dev, table);
3236
3237 /* RAM RESET */
3238 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3239 if (table)
3240 combios_parse_ram_reset_table(dev, table);
3241
3242 /* ASIC INIT 3 */
3243 table =
3244 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3245 if (table)
3246 combios_parse_mmio_table(dev, table);
3247
3248 /* write CONFIG_MEMSIZE */
3249 combios_write_ram_size(dev);
3250 }
3251
3252 /* quirk for rs4xx HP nx6125 laptop to make it resume
3253 * - it hangs on resume inside the dynclk 1 table.
3254 */
3255 if (rdev->family == CHIP_RS480 &&
3256 rdev->pdev->subsystem_vendor == 0x103c &&
3257 rdev->pdev->subsystem_device == 0x308b)
3258 return;
3259
3260 /* quirk for rs4xx HP dv5000 laptop to make it resume
3261 * - it hangs on resume inside the dynclk 1 table.
3262 */
3263 if (rdev->family == CHIP_RS480 &&
3264 rdev->pdev->subsystem_vendor == 0x103c &&
3265 rdev->pdev->subsystem_device == 0x30a4)
3266 return;
3267
3268 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3269 * - it hangs on resume inside the dynclk 1 table.
3270 */
3271 if (rdev->family == CHIP_RS480 &&
3272 rdev->pdev->subsystem_vendor == 0x103c &&
3273 rdev->pdev->subsystem_device == 0x30ae)
3274 return;
3275
3276 /* DYN CLK 1 */
3277 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3278 if (table)
3279 combios_parse_pll_table(dev, table);
3280
3281 }
3282
radeon_combios_initialize_bios_scratch_regs(struct drm_device * dev)3283 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3284 {
3285 struct radeon_device *rdev = dev->dev_private;
3286 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3287
3288 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3289 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3290 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3291
3292 /* let the bios control the backlight */
3293 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3294
3295 /* tell the bios not to handle mode switching */
3296 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3297 RADEON_ACC_MODE_CHANGE);
3298
3299 /* tell the bios a driver is loaded */
3300 bios_7_scratch |= RADEON_DRV_LOADED;
3301
3302 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3303 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3304 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3305 }
3306
radeon_combios_output_lock(struct drm_encoder * encoder,bool lock)3307 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3308 {
3309 struct drm_device *dev = encoder->dev;
3310 struct radeon_device *rdev = dev->dev_private;
3311 uint32_t bios_6_scratch;
3312
3313 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3314
3315 if (lock)
3316 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3317 else
3318 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3319
3320 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3321 }
3322
3323 void
radeon_combios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)3324 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3325 struct drm_encoder *encoder,
3326 bool connected)
3327 {
3328 struct drm_device *dev = connector->dev;
3329 struct radeon_device *rdev = dev->dev_private;
3330 struct radeon_connector *radeon_connector =
3331 to_radeon_connector(connector);
3332 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3333 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3334 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3335
3336 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3337 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3338 if (connected) {
3339 DRM_DEBUG_KMS("TV1 connected\n");
3340 /* fix me */
3341 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3342 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3343 bios_5_scratch |= RADEON_TV1_ON;
3344 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3345 } else {
3346 DRM_DEBUG_KMS("TV1 disconnected\n");
3347 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3348 bios_5_scratch &= ~RADEON_TV1_ON;
3349 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3350 }
3351 }
3352 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3353 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3354 if (connected) {
3355 DRM_DEBUG_KMS("LCD1 connected\n");
3356 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3357 bios_5_scratch |= RADEON_LCD1_ON;
3358 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3359 } else {
3360 DRM_DEBUG_KMS("LCD1 disconnected\n");
3361 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3362 bios_5_scratch &= ~RADEON_LCD1_ON;
3363 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3364 }
3365 }
3366 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3367 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3368 if (connected) {
3369 DRM_DEBUG_KMS("CRT1 connected\n");
3370 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3371 bios_5_scratch |= RADEON_CRT1_ON;
3372 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3373 } else {
3374 DRM_DEBUG_KMS("CRT1 disconnected\n");
3375 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3376 bios_5_scratch &= ~RADEON_CRT1_ON;
3377 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3378 }
3379 }
3380 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3381 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3382 if (connected) {
3383 DRM_DEBUG_KMS("CRT2 connected\n");
3384 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3385 bios_5_scratch |= RADEON_CRT2_ON;
3386 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3387 } else {
3388 DRM_DEBUG_KMS("CRT2 disconnected\n");
3389 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3390 bios_5_scratch &= ~RADEON_CRT2_ON;
3391 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3392 }
3393 }
3394 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3395 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3396 if (connected) {
3397 DRM_DEBUG_KMS("DFP1 connected\n");
3398 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3399 bios_5_scratch |= RADEON_DFP1_ON;
3400 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3401 } else {
3402 DRM_DEBUG_KMS("DFP1 disconnected\n");
3403 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3404 bios_5_scratch &= ~RADEON_DFP1_ON;
3405 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3406 }
3407 }
3408 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3409 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3410 if (connected) {
3411 DRM_DEBUG_KMS("DFP2 connected\n");
3412 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3413 bios_5_scratch |= RADEON_DFP2_ON;
3414 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3415 } else {
3416 DRM_DEBUG_KMS("DFP2 disconnected\n");
3417 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3418 bios_5_scratch &= ~RADEON_DFP2_ON;
3419 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3420 }
3421 }
3422 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3423 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3424 }
3425
3426 void
radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)3427 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3428 {
3429 struct drm_device *dev = encoder->dev;
3430 struct radeon_device *rdev = dev->dev_private;
3431 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3432 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3433
3434 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3435 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3436 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3437 }
3438 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3439 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3440 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3441 }
3442 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3443 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3444 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3445 }
3446 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3447 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3448 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3449 }
3450 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3451 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3452 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3453 }
3454 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3455 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3456 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3457 }
3458 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3459 }
3460
3461 void
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)3462 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3463 {
3464 struct drm_device *dev = encoder->dev;
3465 struct radeon_device *rdev = dev->dev_private;
3466 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3467 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3468
3469 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3470 if (on)
3471 bios_6_scratch |= RADEON_TV_DPMS_ON;
3472 else
3473 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3474 }
3475 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3476 if (on)
3477 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3478 else
3479 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3480 }
3481 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3482 if (on)
3483 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3484 else
3485 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3486 }
3487 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3488 if (on)
3489 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3490 else
3491 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3492 }
3493 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3494 }
3495