1 /*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * Common Codes for S3C64XX machines
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/ioport.h>
22 #include <linux/serial_core.h>
23 #include <linux/platform_device.h>
24 #include <linux/io.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/gpio.h>
28
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
31 #include <asm/hardware/vic.h>
32 #include <asm/system_misc.h>
33
34 #include <mach/map.h>
35 #include <mach/hardware.h>
36 #include <mach/regs-gpio.h>
37
38 #include <plat/cpu.h>
39 #include <plat/clock.h>
40 #include <plat/devs.h>
41 #include <plat/pm.h>
42 #include <plat/gpio-cfg.h>
43 #include <plat/irq-uart.h>
44 #include <plat/irq-vic-timer.h>
45 #include <plat/regs-irqtype.h>
46 #include <plat/regs-serial.h>
47 #include <plat/watchdog-reset.h>
48
49 #include "common.h"
50
51 /* uart registration process */
52
s3c64xx_init_uarts(struct s3c2410_uartcfg * cfg,int no)53 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
54 {
55 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
56 }
57
58 /* table of supported CPUs */
59
60 static const char name_s3c6400[] = "S3C6400";
61 static const char name_s3c6410[] = "S3C6410";
62
63 static struct cpu_table cpu_ids[] __initdata = {
64 {
65 .idcode = S3C6400_CPU_ID,
66 .idmask = S3C64XX_CPU_MASK,
67 .map_io = s3c6400_map_io,
68 .init_clocks = s3c6400_init_clocks,
69 .init_uarts = s3c64xx_init_uarts,
70 .init = s3c6400_init,
71 .name = name_s3c6400,
72 }, {
73 .idcode = S3C6410_CPU_ID,
74 .idmask = S3C64XX_CPU_MASK,
75 .map_io = s3c6410_map_io,
76 .init_clocks = s3c6410_init_clocks,
77 .init_uarts = s3c64xx_init_uarts,
78 .init = s3c6410_init,
79 .name = name_s3c6410,
80 },
81 };
82
83 /* minimal IO mapping */
84
85 /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
86 #define UART_OFFS (S3C_PA_UART & 0xfffff)
87
88 static struct map_desc s3c_iodesc[] __initdata = {
89 {
90 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
92 .length = SZ_4K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S3C_VA_MEM,
96 .pfn = __phys_to_pfn(S3C64XX_PA_SROM),
97 .length = SZ_4K,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
101 .pfn = __phys_to_pfn(S3C_PA_UART),
102 .length = SZ_4K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)VA_VIC0,
106 .pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
107 .length = SZ_16K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)VA_VIC1,
111 .pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
112 .length = SZ_16K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)S3C_VA_TIMER,
116 .pfn = __phys_to_pfn(S3C_PA_TIMER),
117 .length = SZ_16K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)S3C64XX_VA_GPIO,
121 .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
122 .length = SZ_4K,
123 .type = MT_DEVICE,
124 }, {
125 .virtual = (unsigned long)S3C64XX_VA_MODEM,
126 .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
127 .length = SZ_4K,
128 .type = MT_DEVICE,
129 }, {
130 .virtual = (unsigned long)S3C_VA_WATCHDOG,
131 .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
132 .length = SZ_4K,
133 .type = MT_DEVICE,
134 }, {
135 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
136 .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
137 .length = SZ_1K,
138 .type = MT_DEVICE,
139 },
140 };
141
142 static struct bus_type s3c64xx_subsys = {
143 .name = "s3c64xx-core",
144 .dev_name = "s3c64xx-core",
145 };
146
147 static struct device s3c64xx_dev = {
148 .bus = &s3c64xx_subsys,
149 };
150
151 /* read cpu identification code */
152
s3c64xx_init_io(struct map_desc * mach_desc,int size)153 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
154 {
155 /* initialise the io descriptors we need for initialisation */
156 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
157 iotable_init(mach_desc, size);
158 init_consistent_dma_size(SZ_8M);
159
160 /* detect cpu id */
161 s3c64xx_init_cpu();
162
163 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
164 }
165
s3c64xx_dev_init(void)166 static __init int s3c64xx_dev_init(void)
167 {
168 subsys_system_register(&s3c64xx_subsys, NULL);
169 return device_register(&s3c64xx_dev);
170 }
171 core_initcall(s3c64xx_dev_init);
172
173 /*
174 * setup the sources the vic should advertise resume
175 * for, even though it is not doing the wake
176 * (set_irq_wake needs to be valid)
177 */
178 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
179 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
180 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
181 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
182 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
183 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
184
s3c64xx_init_irq(u32 vic0_valid,u32 vic1_valid)185 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
186 {
187 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
188
189 /* initialise the pair of VICs */
190 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
191 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
192
193 /* add the timer sub-irqs */
194 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
195 }
196
197 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
198 #define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
199
s3c_irq_eint_mask(struct irq_data * data)200 static inline void s3c_irq_eint_mask(struct irq_data *data)
201 {
202 u32 mask;
203
204 mask = __raw_readl(S3C64XX_EINT0MASK);
205 mask |= (u32)data->chip_data;
206 __raw_writel(mask, S3C64XX_EINT0MASK);
207 }
208
s3c_irq_eint_unmask(struct irq_data * data)209 static void s3c_irq_eint_unmask(struct irq_data *data)
210 {
211 u32 mask;
212
213 mask = __raw_readl(S3C64XX_EINT0MASK);
214 mask &= ~((u32)data->chip_data);
215 __raw_writel(mask, S3C64XX_EINT0MASK);
216 }
217
s3c_irq_eint_ack(struct irq_data * data)218 static inline void s3c_irq_eint_ack(struct irq_data *data)
219 {
220 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
221 }
222
s3c_irq_eint_maskack(struct irq_data * data)223 static void s3c_irq_eint_maskack(struct irq_data *data)
224 {
225 /* compiler should in-line these */
226 s3c_irq_eint_mask(data);
227 s3c_irq_eint_ack(data);
228 }
229
s3c_irq_eint_set_type(struct irq_data * data,unsigned int type)230 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
231 {
232 int offs = eint_offset(data->irq);
233 int pin, pin_val;
234 int shift;
235 u32 ctrl, mask;
236 u32 newvalue = 0;
237 void __iomem *reg;
238
239 if (offs > 27)
240 return -EINVAL;
241
242 if (offs <= 15)
243 reg = S3C64XX_EINT0CON0;
244 else
245 reg = S3C64XX_EINT0CON1;
246
247 switch (type) {
248 case IRQ_TYPE_NONE:
249 printk(KERN_WARNING "No edge setting!\n");
250 break;
251
252 case IRQ_TYPE_EDGE_RISING:
253 newvalue = S3C2410_EXTINT_RISEEDGE;
254 break;
255
256 case IRQ_TYPE_EDGE_FALLING:
257 newvalue = S3C2410_EXTINT_FALLEDGE;
258 break;
259
260 case IRQ_TYPE_EDGE_BOTH:
261 newvalue = S3C2410_EXTINT_BOTHEDGE;
262 break;
263
264 case IRQ_TYPE_LEVEL_LOW:
265 newvalue = S3C2410_EXTINT_LOWLEV;
266 break;
267
268 case IRQ_TYPE_LEVEL_HIGH:
269 newvalue = S3C2410_EXTINT_HILEV;
270 break;
271
272 default:
273 printk(KERN_ERR "No such irq type %d", type);
274 return -1;
275 }
276
277 if (offs <= 15)
278 shift = (offs / 2) * 4;
279 else
280 shift = ((offs - 16) / 2) * 4;
281 mask = 0x7 << shift;
282
283 ctrl = __raw_readl(reg);
284 ctrl &= ~mask;
285 ctrl |= newvalue << shift;
286 __raw_writel(ctrl, reg);
287
288 /* set the GPIO pin appropriately */
289
290 if (offs < 16) {
291 pin = S3C64XX_GPN(offs);
292 pin_val = S3C_GPIO_SFN(2);
293 } else if (offs < 23) {
294 pin = S3C64XX_GPL(offs + 8 - 16);
295 pin_val = S3C_GPIO_SFN(3);
296 } else {
297 pin = S3C64XX_GPM(offs - 23);
298 pin_val = S3C_GPIO_SFN(3);
299 }
300
301 s3c_gpio_cfgpin(pin, pin_val);
302
303 return 0;
304 }
305
306 static struct irq_chip s3c_irq_eint = {
307 .name = "s3c-eint",
308 .irq_mask = s3c_irq_eint_mask,
309 .irq_unmask = s3c_irq_eint_unmask,
310 .irq_mask_ack = s3c_irq_eint_maskack,
311 .irq_ack = s3c_irq_eint_ack,
312 .irq_set_type = s3c_irq_eint_set_type,
313 .irq_set_wake = s3c_irqext_wake,
314 };
315
316 /* s3c_irq_demux_eint
317 *
318 * This function demuxes the IRQ from the group0 external interrupts,
319 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
320 * the specific handlers s3c_irq_demux_eintX_Y.
321 */
s3c_irq_demux_eint(unsigned int start,unsigned int end)322 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
323 {
324 u32 status = __raw_readl(S3C64XX_EINT0PEND);
325 u32 mask = __raw_readl(S3C64XX_EINT0MASK);
326 unsigned int irq;
327
328 status &= ~mask;
329 status >>= start;
330 status &= (1 << (end - start + 1)) - 1;
331
332 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
333 if (status & 1)
334 generic_handle_irq(irq);
335
336 status >>= 1;
337 }
338 }
339
s3c_irq_demux_eint0_3(unsigned int irq,struct irq_desc * desc)340 static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
341 {
342 s3c_irq_demux_eint(0, 3);
343 }
344
s3c_irq_demux_eint4_11(unsigned int irq,struct irq_desc * desc)345 static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
346 {
347 s3c_irq_demux_eint(4, 11);
348 }
349
s3c_irq_demux_eint12_19(unsigned int irq,struct irq_desc * desc)350 static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
351 {
352 s3c_irq_demux_eint(12, 19);
353 }
354
s3c_irq_demux_eint20_27(unsigned int irq,struct irq_desc * desc)355 static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
356 {
357 s3c_irq_demux_eint(20, 27);
358 }
359
s3c64xx_init_irq_eint(void)360 static int __init s3c64xx_init_irq_eint(void)
361 {
362 int irq;
363
364 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
365 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
366 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
367 set_irq_flags(irq, IRQF_VALID);
368 }
369
370 irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
371 irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
372 irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
373 irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
374
375 return 0;
376 }
377 arch_initcall(s3c64xx_init_irq_eint);
378
s3c64xx_restart(char mode,const char * cmd)379 void s3c64xx_restart(char mode, const char *cmd)
380 {
381 if (mode != 's')
382 arch_wdt_reset();
383
384 /* if all else fails, or mode was for soft, jump to 0 */
385 soft_restart(0);
386 }
387