1 /* linux/arch/arm/plat-samsung/devs.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Base SAMSUNG platform device definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/serial_core.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/string.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/fb.h>
26 #include <linux/gfp.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/onenand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/mmc/host.h>
31 #include <linux/ioport.h>
32 #include <linux/platform_data/s3c-hsudc.h>
33
34 #include <asm/irq.h>
35 #include <asm/pmu.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/irq.h>
39
40 #include <mach/hardware.h>
41 #include <mach/dma.h>
42 #include <mach/irqs.h>
43 #include <mach/map.h>
44
45 #include <plat/cpu.h>
46 #include <plat/devs.h>
47 #include <plat/adc.h>
48 #include <plat/ata.h>
49 #include <plat/ehci.h>
50 #include <plat/fb.h>
51 #include <plat/fb-s3c2410.h>
52 #include <plat/hwmon.h>
53 #include <plat/iic.h>
54 #include <plat/keypad.h>
55 #include <plat/mci.h>
56 #include <plat/nand.h>
57 #include <plat/sdhci.h>
58 #include <plat/ts.h>
59 #include <plat/udc.h>
60 #include <plat/udc-hs.h>
61 #include <plat/usb-control.h>
62 #include <plat/usb-phy.h>
63 #include <plat/regs-iic.h>
64 #include <plat/regs-serial.h>
65 #include <plat/regs-spi.h>
66 #include <plat/s3c64xx-spi.h>
67
68 static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
69
70 /* AC97 */
71 #ifdef CONFIG_CPU_S3C2440
72 static struct resource s3c_ac97_resource[] = {
73 [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
74 [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
75 [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
76 [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
77 [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
78 };
79
80 struct platform_device s3c_device_ac97 = {
81 .name = "samsung-ac97",
82 .id = -1,
83 .num_resources = ARRAY_SIZE(s3c_ac97_resource),
84 .resource = s3c_ac97_resource,
85 .dev = {
86 .dma_mask = &samsung_device_dma_mask,
87 .coherent_dma_mask = DMA_BIT_MASK(32),
88 }
89 };
90 #endif /* CONFIG_CPU_S3C2440 */
91
92 /* ADC */
93
94 #ifdef CONFIG_PLAT_S3C24XX
95 static struct resource s3c_adc_resource[] = {
96 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
97 [1] = DEFINE_RES_IRQ(IRQ_TC),
98 [2] = DEFINE_RES_IRQ(IRQ_ADC),
99 };
100
101 struct platform_device s3c_device_adc = {
102 .name = "s3c24xx-adc",
103 .id = -1,
104 .num_resources = ARRAY_SIZE(s3c_adc_resource),
105 .resource = s3c_adc_resource,
106 };
107 #endif /* CONFIG_PLAT_S3C24XX */
108
109 #if defined(CONFIG_SAMSUNG_DEV_ADC)
110 static struct resource s3c_adc_resource[] = {
111 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
112 [1] = DEFINE_RES_IRQ(IRQ_TC),
113 [2] = DEFINE_RES_IRQ(IRQ_ADC),
114 };
115
116 struct platform_device s3c_device_adc = {
117 .name = "samsung-adc",
118 .id = -1,
119 .num_resources = ARRAY_SIZE(s3c_adc_resource),
120 .resource = s3c_adc_resource,
121 };
122 #endif /* CONFIG_SAMSUNG_DEV_ADC */
123
124 /* Camif Controller */
125
126 #ifdef CONFIG_CPU_S3C2440
127 static struct resource s3c_camif_resource[] = {
128 [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
129 [1] = DEFINE_RES_IRQ(IRQ_CAM),
130 };
131
132 struct platform_device s3c_device_camif = {
133 .name = "s3c2440-camif",
134 .id = -1,
135 .num_resources = ARRAY_SIZE(s3c_camif_resource),
136 .resource = s3c_camif_resource,
137 .dev = {
138 .dma_mask = &samsung_device_dma_mask,
139 .coherent_dma_mask = DMA_BIT_MASK(32),
140 }
141 };
142 #endif /* CONFIG_CPU_S3C2440 */
143
144 /* ASOC DMA */
145
146 struct platform_device samsung_asoc_dma = {
147 .name = "samsung-audio",
148 .id = -1,
149 .dev = {
150 .dma_mask = &samsung_device_dma_mask,
151 .coherent_dma_mask = DMA_BIT_MASK(32),
152 }
153 };
154
155 struct platform_device samsung_asoc_idma = {
156 .name = "samsung-idma",
157 .id = -1,
158 .dev = {
159 .dma_mask = &samsung_device_dma_mask,
160 .coherent_dma_mask = DMA_BIT_MASK(32),
161 }
162 };
163
164 /* FB */
165
166 #ifdef CONFIG_S3C_DEV_FB
167 static struct resource s3c_fb_resource[] = {
168 [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
169 [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
170 [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
171 [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
172 };
173
174 struct platform_device s3c_device_fb = {
175 .name = "s3c-fb",
176 .id = -1,
177 .num_resources = ARRAY_SIZE(s3c_fb_resource),
178 .resource = s3c_fb_resource,
179 .dev = {
180 .dma_mask = &samsung_device_dma_mask,
181 .coherent_dma_mask = DMA_BIT_MASK(32),
182 },
183 };
184
s3c_fb_set_platdata(struct s3c_fb_platdata * pd)185 void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
186 {
187 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
188 &s3c_device_fb);
189 }
190 #endif /* CONFIG_S3C_DEV_FB */
191
192 /* FIMC */
193
194 #ifdef CONFIG_S5P_DEV_FIMC0
195 static struct resource s5p_fimc0_resource[] = {
196 [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
197 [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
198 };
199
200 struct platform_device s5p_device_fimc0 = {
201 .name = "s5p-fimc",
202 .id = 0,
203 .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
204 .resource = s5p_fimc0_resource,
205 .dev = {
206 .dma_mask = &samsung_device_dma_mask,
207 .coherent_dma_mask = DMA_BIT_MASK(32),
208 },
209 };
210
211 struct platform_device s5p_device_fimc_md = {
212 .name = "s5p-fimc-md",
213 .id = -1,
214 };
215 #endif /* CONFIG_S5P_DEV_FIMC0 */
216
217 #ifdef CONFIG_S5P_DEV_FIMC1
218 static struct resource s5p_fimc1_resource[] = {
219 [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
220 [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
221 };
222
223 struct platform_device s5p_device_fimc1 = {
224 .name = "s5p-fimc",
225 .id = 1,
226 .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
227 .resource = s5p_fimc1_resource,
228 .dev = {
229 .dma_mask = &samsung_device_dma_mask,
230 .coherent_dma_mask = DMA_BIT_MASK(32),
231 },
232 };
233 #endif /* CONFIG_S5P_DEV_FIMC1 */
234
235 #ifdef CONFIG_S5P_DEV_FIMC2
236 static struct resource s5p_fimc2_resource[] = {
237 [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
238 [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
239 };
240
241 struct platform_device s5p_device_fimc2 = {
242 .name = "s5p-fimc",
243 .id = 2,
244 .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
245 .resource = s5p_fimc2_resource,
246 .dev = {
247 .dma_mask = &samsung_device_dma_mask,
248 .coherent_dma_mask = DMA_BIT_MASK(32),
249 },
250 };
251 #endif /* CONFIG_S5P_DEV_FIMC2 */
252
253 #ifdef CONFIG_S5P_DEV_FIMC3
254 static struct resource s5p_fimc3_resource[] = {
255 [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
256 [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
257 };
258
259 struct platform_device s5p_device_fimc3 = {
260 .name = "s5p-fimc",
261 .id = 3,
262 .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
263 .resource = s5p_fimc3_resource,
264 .dev = {
265 .dma_mask = &samsung_device_dma_mask,
266 .coherent_dma_mask = DMA_BIT_MASK(32),
267 },
268 };
269 #endif /* CONFIG_S5P_DEV_FIMC3 */
270
271 /* G2D */
272
273 #ifdef CONFIG_S5P_DEV_G2D
274 static struct resource s5p_g2d_resource[] = {
275 [0] = {
276 .start = S5P_PA_G2D,
277 .end = S5P_PA_G2D + SZ_4K - 1,
278 .flags = IORESOURCE_MEM,
279 },
280 [1] = {
281 .start = IRQ_2D,
282 .end = IRQ_2D,
283 .flags = IORESOURCE_IRQ,
284 },
285 };
286
287 struct platform_device s5p_device_g2d = {
288 .name = "s5p-g2d",
289 .id = 0,
290 .num_resources = ARRAY_SIZE(s5p_g2d_resource),
291 .resource = s5p_g2d_resource,
292 .dev = {
293 .dma_mask = &samsung_device_dma_mask,
294 .coherent_dma_mask = DMA_BIT_MASK(32),
295 },
296 };
297 #endif /* CONFIG_S5P_DEV_G2D */
298
299 #ifdef CONFIG_S5P_DEV_JPEG
300 static struct resource s5p_jpeg_resource[] = {
301 [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
302 [1] = DEFINE_RES_IRQ(IRQ_JPEG),
303 };
304
305 struct platform_device s5p_device_jpeg = {
306 .name = "s5p-jpeg",
307 .id = 0,
308 .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
309 .resource = s5p_jpeg_resource,
310 .dev = {
311 .dma_mask = &samsung_device_dma_mask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
313 },
314 };
315 #endif /* CONFIG_S5P_DEV_JPEG */
316
317 /* FIMD0 */
318
319 #ifdef CONFIG_S5P_DEV_FIMD0
320 static struct resource s5p_fimd0_resource[] = {
321 [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
322 [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
323 [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
324 [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
325 };
326
327 struct platform_device s5p_device_fimd0 = {
328 .name = "s5p-fb",
329 .id = 0,
330 .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
331 .resource = s5p_fimd0_resource,
332 .dev = {
333 .dma_mask = &samsung_device_dma_mask,
334 .coherent_dma_mask = DMA_BIT_MASK(32),
335 },
336 };
337
s5p_fimd0_set_platdata(struct s3c_fb_platdata * pd)338 void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
339 {
340 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
341 &s5p_device_fimd0);
342 }
343 #endif /* CONFIG_S5P_DEV_FIMD0 */
344
345 /* HWMON */
346
347 #ifdef CONFIG_S3C_DEV_HWMON
348 struct platform_device s3c_device_hwmon = {
349 .name = "s3c-hwmon",
350 .id = -1,
351 .dev.parent = &s3c_device_adc.dev,
352 };
353
s3c_hwmon_set_platdata(struct s3c_hwmon_pdata * pd)354 void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
355 {
356 s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
357 &s3c_device_hwmon);
358 }
359 #endif /* CONFIG_S3C_DEV_HWMON */
360
361 /* HSMMC */
362
363 #ifdef CONFIG_S3C_DEV_HSMMC
364 static struct resource s3c_hsmmc_resource[] = {
365 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
366 [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
367 };
368
369 struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
370 .max_width = 4,
371 .host_caps = (MMC_CAP_4_BIT_DATA |
372 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
373 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
374 };
375
376 struct platform_device s3c_device_hsmmc0 = {
377 .name = "s3c-sdhci",
378 .id = 0,
379 .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
380 .resource = s3c_hsmmc_resource,
381 .dev = {
382 .dma_mask = &samsung_device_dma_mask,
383 .coherent_dma_mask = DMA_BIT_MASK(32),
384 .platform_data = &s3c_hsmmc0_def_platdata,
385 },
386 };
387
s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata * pd)388 void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
389 {
390 s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
391 }
392 #endif /* CONFIG_S3C_DEV_HSMMC */
393
394 #ifdef CONFIG_S3C_DEV_HSMMC1
395 static struct resource s3c_hsmmc1_resource[] = {
396 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
397 [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
398 };
399
400 struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
401 .max_width = 4,
402 .host_caps = (MMC_CAP_4_BIT_DATA |
403 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
404 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
405 };
406
407 struct platform_device s3c_device_hsmmc1 = {
408 .name = "s3c-sdhci",
409 .id = 1,
410 .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
411 .resource = s3c_hsmmc1_resource,
412 .dev = {
413 .dma_mask = &samsung_device_dma_mask,
414 .coherent_dma_mask = DMA_BIT_MASK(32),
415 .platform_data = &s3c_hsmmc1_def_platdata,
416 },
417 };
418
s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata * pd)419 void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
420 {
421 s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
422 }
423 #endif /* CONFIG_S3C_DEV_HSMMC1 */
424
425 /* HSMMC2 */
426
427 #ifdef CONFIG_S3C_DEV_HSMMC2
428 static struct resource s3c_hsmmc2_resource[] = {
429 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
430 [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
431 };
432
433 struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
434 .max_width = 4,
435 .host_caps = (MMC_CAP_4_BIT_DATA |
436 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
437 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
438 };
439
440 struct platform_device s3c_device_hsmmc2 = {
441 .name = "s3c-sdhci",
442 .id = 2,
443 .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
444 .resource = s3c_hsmmc2_resource,
445 .dev = {
446 .dma_mask = &samsung_device_dma_mask,
447 .coherent_dma_mask = DMA_BIT_MASK(32),
448 .platform_data = &s3c_hsmmc2_def_platdata,
449 },
450 };
451
s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata * pd)452 void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
453 {
454 s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
455 }
456 #endif /* CONFIG_S3C_DEV_HSMMC2 */
457
458 #ifdef CONFIG_S3C_DEV_HSMMC3
459 static struct resource s3c_hsmmc3_resource[] = {
460 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
461 [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
462 };
463
464 struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
465 .max_width = 4,
466 .host_caps = (MMC_CAP_4_BIT_DATA |
467 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
468 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
469 };
470
471 struct platform_device s3c_device_hsmmc3 = {
472 .name = "s3c-sdhci",
473 .id = 3,
474 .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
475 .resource = s3c_hsmmc3_resource,
476 .dev = {
477 .dma_mask = &samsung_device_dma_mask,
478 .coherent_dma_mask = DMA_BIT_MASK(32),
479 .platform_data = &s3c_hsmmc3_def_platdata,
480 },
481 };
482
s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata * pd)483 void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
484 {
485 s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
486 }
487 #endif /* CONFIG_S3C_DEV_HSMMC3 */
488
489 /* I2C */
490
491 static struct resource s3c_i2c0_resource[] = {
492 [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
493 [1] = DEFINE_RES_IRQ(IRQ_IIC),
494 };
495
496 struct platform_device s3c_device_i2c0 = {
497 .name = "s3c2410-i2c",
498 #ifdef CONFIG_S3C_DEV_I2C1
499 .id = 0,
500 #else
501 .id = -1,
502 #endif
503 .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
504 .resource = s3c_i2c0_resource,
505 };
506
507 struct s3c2410_platform_i2c default_i2c_data __initdata = {
508 .flags = 0,
509 .slave_addr = 0x10,
510 .frequency = 100*1000,
511 .sda_delay = 100,
512 };
513
s3c_i2c0_set_platdata(struct s3c2410_platform_i2c * pd)514 void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
515 {
516 struct s3c2410_platform_i2c *npd;
517
518 if (!pd) {
519 pd = &default_i2c_data;
520 pd->bus_num = 0;
521 }
522
523 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
524 &s3c_device_i2c0);
525
526 if (!npd->cfg_gpio)
527 npd->cfg_gpio = s3c_i2c0_cfg_gpio;
528 }
529
530 #ifdef CONFIG_S3C_DEV_I2C1
531 static struct resource s3c_i2c1_resource[] = {
532 [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
533 [1] = DEFINE_RES_IRQ(IRQ_IIC1),
534 };
535
536 struct platform_device s3c_device_i2c1 = {
537 .name = "s3c2410-i2c",
538 .id = 1,
539 .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
540 .resource = s3c_i2c1_resource,
541 };
542
s3c_i2c1_set_platdata(struct s3c2410_platform_i2c * pd)543 void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
544 {
545 struct s3c2410_platform_i2c *npd;
546
547 if (!pd) {
548 pd = &default_i2c_data;
549 pd->bus_num = 1;
550 }
551
552 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
553 &s3c_device_i2c1);
554
555 if (!npd->cfg_gpio)
556 npd->cfg_gpio = s3c_i2c1_cfg_gpio;
557 }
558 #endif /* CONFIG_S3C_DEV_I2C1 */
559
560 #ifdef CONFIG_S3C_DEV_I2C2
561 static struct resource s3c_i2c2_resource[] = {
562 [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
563 [1] = DEFINE_RES_IRQ(IRQ_IIC2),
564 };
565
566 struct platform_device s3c_device_i2c2 = {
567 .name = "s3c2410-i2c",
568 .id = 2,
569 .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
570 .resource = s3c_i2c2_resource,
571 };
572
s3c_i2c2_set_platdata(struct s3c2410_platform_i2c * pd)573 void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
574 {
575 struct s3c2410_platform_i2c *npd;
576
577 if (!pd) {
578 pd = &default_i2c_data;
579 pd->bus_num = 2;
580 }
581
582 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
583 &s3c_device_i2c2);
584
585 if (!npd->cfg_gpio)
586 npd->cfg_gpio = s3c_i2c2_cfg_gpio;
587 }
588 #endif /* CONFIG_S3C_DEV_I2C2 */
589
590 #ifdef CONFIG_S3C_DEV_I2C3
591 static struct resource s3c_i2c3_resource[] = {
592 [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
593 [1] = DEFINE_RES_IRQ(IRQ_IIC3),
594 };
595
596 struct platform_device s3c_device_i2c3 = {
597 .name = "s3c2440-i2c",
598 .id = 3,
599 .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
600 .resource = s3c_i2c3_resource,
601 };
602
s3c_i2c3_set_platdata(struct s3c2410_platform_i2c * pd)603 void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
604 {
605 struct s3c2410_platform_i2c *npd;
606
607 if (!pd) {
608 pd = &default_i2c_data;
609 pd->bus_num = 3;
610 }
611
612 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
613 &s3c_device_i2c3);
614
615 if (!npd->cfg_gpio)
616 npd->cfg_gpio = s3c_i2c3_cfg_gpio;
617 }
618 #endif /*CONFIG_S3C_DEV_I2C3 */
619
620 #ifdef CONFIG_S3C_DEV_I2C4
621 static struct resource s3c_i2c4_resource[] = {
622 [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
623 [1] = DEFINE_RES_IRQ(IRQ_IIC4),
624 };
625
626 struct platform_device s3c_device_i2c4 = {
627 .name = "s3c2440-i2c",
628 .id = 4,
629 .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
630 .resource = s3c_i2c4_resource,
631 };
632
s3c_i2c4_set_platdata(struct s3c2410_platform_i2c * pd)633 void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
634 {
635 struct s3c2410_platform_i2c *npd;
636
637 if (!pd) {
638 pd = &default_i2c_data;
639 pd->bus_num = 4;
640 }
641
642 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
643 &s3c_device_i2c4);
644
645 if (!npd->cfg_gpio)
646 npd->cfg_gpio = s3c_i2c4_cfg_gpio;
647 }
648 #endif /*CONFIG_S3C_DEV_I2C4 */
649
650 #ifdef CONFIG_S3C_DEV_I2C5
651 static struct resource s3c_i2c5_resource[] = {
652 [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
653 [1] = DEFINE_RES_IRQ(IRQ_IIC5),
654 };
655
656 struct platform_device s3c_device_i2c5 = {
657 .name = "s3c2440-i2c",
658 .id = 5,
659 .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
660 .resource = s3c_i2c5_resource,
661 };
662
s3c_i2c5_set_platdata(struct s3c2410_platform_i2c * pd)663 void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
664 {
665 struct s3c2410_platform_i2c *npd;
666
667 if (!pd) {
668 pd = &default_i2c_data;
669 pd->bus_num = 5;
670 }
671
672 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
673 &s3c_device_i2c5);
674
675 if (!npd->cfg_gpio)
676 npd->cfg_gpio = s3c_i2c5_cfg_gpio;
677 }
678 #endif /*CONFIG_S3C_DEV_I2C5 */
679
680 #ifdef CONFIG_S3C_DEV_I2C6
681 static struct resource s3c_i2c6_resource[] = {
682 [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
683 [1] = DEFINE_RES_IRQ(IRQ_IIC6),
684 };
685
686 struct platform_device s3c_device_i2c6 = {
687 .name = "s3c2440-i2c",
688 .id = 6,
689 .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
690 .resource = s3c_i2c6_resource,
691 };
692
s3c_i2c6_set_platdata(struct s3c2410_platform_i2c * pd)693 void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
694 {
695 struct s3c2410_platform_i2c *npd;
696
697 if (!pd) {
698 pd = &default_i2c_data;
699 pd->bus_num = 6;
700 }
701
702 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
703 &s3c_device_i2c6);
704
705 if (!npd->cfg_gpio)
706 npd->cfg_gpio = s3c_i2c6_cfg_gpio;
707 }
708 #endif /* CONFIG_S3C_DEV_I2C6 */
709
710 #ifdef CONFIG_S3C_DEV_I2C7
711 static struct resource s3c_i2c7_resource[] = {
712 [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
713 [1] = DEFINE_RES_IRQ(IRQ_IIC7),
714 };
715
716 struct platform_device s3c_device_i2c7 = {
717 .name = "s3c2440-i2c",
718 .id = 7,
719 .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
720 .resource = s3c_i2c7_resource,
721 };
722
s3c_i2c7_set_platdata(struct s3c2410_platform_i2c * pd)723 void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
724 {
725 struct s3c2410_platform_i2c *npd;
726
727 if (!pd) {
728 pd = &default_i2c_data;
729 pd->bus_num = 7;
730 }
731
732 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
733 &s3c_device_i2c7);
734
735 if (!npd->cfg_gpio)
736 npd->cfg_gpio = s3c_i2c7_cfg_gpio;
737 }
738 #endif /* CONFIG_S3C_DEV_I2C7 */
739
740 /* I2C HDMIPHY */
741
742 #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
743 static struct resource s5p_i2c_resource[] = {
744 [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
745 [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
746 };
747
748 struct platform_device s5p_device_i2c_hdmiphy = {
749 .name = "s3c2440-hdmiphy-i2c",
750 .id = -1,
751 .num_resources = ARRAY_SIZE(s5p_i2c_resource),
752 .resource = s5p_i2c_resource,
753 };
754
s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c * pd)755 void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
756 {
757 struct s3c2410_platform_i2c *npd;
758
759 if (!pd) {
760 pd = &default_i2c_data;
761
762 if (soc_is_exynos4210())
763 pd->bus_num = 8;
764 else if (soc_is_s5pv210())
765 pd->bus_num = 3;
766 else
767 pd->bus_num = 0;
768 }
769
770 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
771 &s5p_device_i2c_hdmiphy);
772 }
773 #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
774
775 /* I2S */
776
777 #ifdef CONFIG_PLAT_S3C24XX
778 static struct resource s3c_iis_resource[] = {
779 [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
780 };
781
782 struct platform_device s3c_device_iis = {
783 .name = "s3c24xx-iis",
784 .id = -1,
785 .num_resources = ARRAY_SIZE(s3c_iis_resource),
786 .resource = s3c_iis_resource,
787 .dev = {
788 .dma_mask = &samsung_device_dma_mask,
789 .coherent_dma_mask = DMA_BIT_MASK(32),
790 }
791 };
792 #endif /* CONFIG_PLAT_S3C24XX */
793
794 /* IDE CFCON */
795
796 #ifdef CONFIG_SAMSUNG_DEV_IDE
797 static struct resource s3c_cfcon_resource[] = {
798 [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
799 [1] = DEFINE_RES_IRQ(IRQ_CFCON),
800 };
801
802 struct platform_device s3c_device_cfcon = {
803 .id = 0,
804 .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
805 .resource = s3c_cfcon_resource,
806 };
807
s3c_ide_set_platdata(struct s3c_ide_platdata * pdata)808 void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
809 {
810 s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
811 &s3c_device_cfcon);
812 }
813 #endif /* CONFIG_SAMSUNG_DEV_IDE */
814
815 /* KEYPAD */
816
817 #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
818 static struct resource samsung_keypad_resources[] = {
819 [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
820 [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
821 };
822
823 struct platform_device samsung_device_keypad = {
824 .name = "samsung-keypad",
825 .id = -1,
826 .num_resources = ARRAY_SIZE(samsung_keypad_resources),
827 .resource = samsung_keypad_resources,
828 };
829
samsung_keypad_set_platdata(struct samsung_keypad_platdata * pd)830 void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
831 {
832 struct samsung_keypad_platdata *npd;
833
834 npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
835 &samsung_device_keypad);
836
837 if (!npd->cfg_gpio)
838 npd->cfg_gpio = samsung_keypad_cfg_gpio;
839 }
840 #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
841
842 /* LCD Controller */
843
844 #ifdef CONFIG_PLAT_S3C24XX
845 static struct resource s3c_lcd_resource[] = {
846 [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
847 [1] = DEFINE_RES_IRQ(IRQ_LCD),
848 };
849
850 struct platform_device s3c_device_lcd = {
851 .name = "s3c2410-lcd",
852 .id = -1,
853 .num_resources = ARRAY_SIZE(s3c_lcd_resource),
854 .resource = s3c_lcd_resource,
855 .dev = {
856 .dma_mask = &samsung_device_dma_mask,
857 .coherent_dma_mask = DMA_BIT_MASK(32),
858 }
859 };
860
s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info * pd)861 void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
862 {
863 struct s3c2410fb_mach_info *npd;
864
865 npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
866 if (npd) {
867 npd->displays = kmemdup(pd->displays,
868 sizeof(struct s3c2410fb_display) * npd->num_displays,
869 GFP_KERNEL);
870 if (!npd->displays)
871 printk(KERN_ERR "no memory for LCD display data\n");
872 } else {
873 printk(KERN_ERR "no memory for LCD platform data\n");
874 }
875 }
876 #endif /* CONFIG_PLAT_S3C24XX */
877
878 /* MFC */
879
880 #ifdef CONFIG_S5P_DEV_MFC
881 static struct resource s5p_mfc_resource[] = {
882 [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
883 [1] = DEFINE_RES_IRQ(IRQ_MFC),
884 };
885
886 struct platform_device s5p_device_mfc = {
887 .name = "s5p-mfc",
888 .id = -1,
889 .num_resources = ARRAY_SIZE(s5p_mfc_resource),
890 .resource = s5p_mfc_resource,
891 };
892
893 /*
894 * MFC hardware has 2 memory interfaces which are modelled as two separate
895 * platform devices to let dma-mapping distinguish between them.
896 *
897 * MFC parent device (s5p_device_mfc) must be registered before memory
898 * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
899 */
900
901 struct platform_device s5p_device_mfc_l = {
902 .name = "s5p-mfc-l",
903 .id = -1,
904 .dev = {
905 .parent = &s5p_device_mfc.dev,
906 .dma_mask = &samsung_device_dma_mask,
907 .coherent_dma_mask = DMA_BIT_MASK(32),
908 },
909 };
910
911 struct platform_device s5p_device_mfc_r = {
912 .name = "s5p-mfc-r",
913 .id = -1,
914 .dev = {
915 .parent = &s5p_device_mfc.dev,
916 .dma_mask = &samsung_device_dma_mask,
917 .coherent_dma_mask = DMA_BIT_MASK(32),
918 },
919 };
920 #endif /* CONFIG_S5P_DEV_MFC */
921
922 /* MIPI CSIS */
923
924 #ifdef CONFIG_S5P_DEV_CSIS0
925 static struct resource s5p_mipi_csis0_resource[] = {
926 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
927 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
928 };
929
930 struct platform_device s5p_device_mipi_csis0 = {
931 .name = "s5p-mipi-csis",
932 .id = 0,
933 .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
934 .resource = s5p_mipi_csis0_resource,
935 };
936 #endif /* CONFIG_S5P_DEV_CSIS0 */
937
938 #ifdef CONFIG_S5P_DEV_CSIS1
939 static struct resource s5p_mipi_csis1_resource[] = {
940 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
941 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
942 };
943
944 struct platform_device s5p_device_mipi_csis1 = {
945 .name = "s5p-mipi-csis",
946 .id = 1,
947 .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
948 .resource = s5p_mipi_csis1_resource,
949 };
950 #endif
951
952 /* NAND */
953
954 #ifdef CONFIG_S3C_DEV_NAND
955 static struct resource s3c_nand_resource[] = {
956 [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
957 };
958
959 struct platform_device s3c_device_nand = {
960 .name = "s3c2410-nand",
961 .id = -1,
962 .num_resources = ARRAY_SIZE(s3c_nand_resource),
963 .resource = s3c_nand_resource,
964 };
965
966 /*
967 * s3c_nand_copy_set() - copy nand set data
968 * @set: The new structure, directly copied from the old.
969 *
970 * Copy all the fields from the NAND set field from what is probably __initdata
971 * to new kernel memory. The code returns 0 if the copy happened correctly or
972 * an error code for the calling function to display.
973 *
974 * Note, we currently do not try and look to see if we've already copied the
975 * data in a previous set.
976 */
s3c_nand_copy_set(struct s3c2410_nand_set * set)977 static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
978 {
979 void *ptr;
980 int size;
981
982 size = sizeof(struct mtd_partition) * set->nr_partitions;
983 if (size) {
984 ptr = kmemdup(set->partitions, size, GFP_KERNEL);
985 set->partitions = ptr;
986
987 if (!ptr)
988 return -ENOMEM;
989 }
990
991 if (set->nr_map && set->nr_chips) {
992 size = sizeof(int) * set->nr_chips;
993 ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
994 set->nr_map = ptr;
995
996 if (!ptr)
997 return -ENOMEM;
998 }
999
1000 if (set->ecc_layout) {
1001 ptr = kmemdup(set->ecc_layout,
1002 sizeof(struct nand_ecclayout), GFP_KERNEL);
1003 set->ecc_layout = ptr;
1004
1005 if (!ptr)
1006 return -ENOMEM;
1007 }
1008
1009 return 0;
1010 }
1011
s3c_nand_set_platdata(struct s3c2410_platform_nand * nand)1012 void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
1013 {
1014 struct s3c2410_platform_nand *npd;
1015 int size;
1016 int ret;
1017
1018 /* note, if we get a failure in allocation, we simply drop out of the
1019 * function. If there is so little memory available at initialisation
1020 * time then there is little chance the system is going to run.
1021 */
1022
1023 npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
1024 &s3c_device_nand);
1025 if (!npd)
1026 return;
1027
1028 /* now see if we need to copy any of the nand set data */
1029
1030 size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
1031 if (size) {
1032 struct s3c2410_nand_set *from = npd->sets;
1033 struct s3c2410_nand_set *to;
1034 int i;
1035
1036 to = kmemdup(from, size, GFP_KERNEL);
1037 npd->sets = to; /* set, even if we failed */
1038
1039 if (!to) {
1040 printk(KERN_ERR "%s: no memory for sets\n", __func__);
1041 return;
1042 }
1043
1044 for (i = 0; i < npd->nr_sets; i++) {
1045 ret = s3c_nand_copy_set(to);
1046 if (ret) {
1047 printk(KERN_ERR "%s: failed to copy set %d\n",
1048 __func__, i);
1049 return;
1050 }
1051 to++;
1052 }
1053 }
1054 }
1055 #endif /* CONFIG_S3C_DEV_NAND */
1056
1057 /* ONENAND */
1058
1059 #ifdef CONFIG_S3C_DEV_ONENAND
1060 static struct resource s3c_onenand_resources[] = {
1061 [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
1062 [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
1063 [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
1064 };
1065
1066 struct platform_device s3c_device_onenand = {
1067 .name = "samsung-onenand",
1068 .id = 0,
1069 .num_resources = ARRAY_SIZE(s3c_onenand_resources),
1070 .resource = s3c_onenand_resources,
1071 };
1072 #endif /* CONFIG_S3C_DEV_ONENAND */
1073
1074 #ifdef CONFIG_S3C64XX_DEV_ONENAND1
1075 static struct resource s3c64xx_onenand1_resources[] = {
1076 [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
1077 [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
1078 [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
1079 };
1080
1081 struct platform_device s3c64xx_device_onenand1 = {
1082 .name = "samsung-onenand",
1083 .id = 1,
1084 .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
1085 .resource = s3c64xx_onenand1_resources,
1086 };
1087
s3c64xx_onenand1_set_platdata(struct onenand_platform_data * pdata)1088 void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
1089 {
1090 s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
1091 &s3c64xx_device_onenand1);
1092 }
1093 #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
1094
1095 #ifdef CONFIG_S5P_DEV_ONENAND
1096 static struct resource s5p_onenand_resources[] = {
1097 [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
1098 [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
1099 [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
1100 };
1101
1102 struct platform_device s5p_device_onenand = {
1103 .name = "s5pc110-onenand",
1104 .id = -1,
1105 .num_resources = ARRAY_SIZE(s5p_onenand_resources),
1106 .resource = s5p_onenand_resources,
1107 };
1108 #endif /* CONFIG_S5P_DEV_ONENAND */
1109
1110 /* PMU */
1111
1112 #ifdef CONFIG_PLAT_S5P
1113 static struct resource s5p_pmu_resource[] = {
1114 DEFINE_RES_IRQ(IRQ_PMU)
1115 };
1116
1117 static struct platform_device s5p_device_pmu = {
1118 .name = "arm-pmu",
1119 .id = ARM_PMU_DEVICE_CPU,
1120 .num_resources = ARRAY_SIZE(s5p_pmu_resource),
1121 .resource = s5p_pmu_resource,
1122 };
1123
s5p_pmu_init(void)1124 static int __init s5p_pmu_init(void)
1125 {
1126 platform_device_register(&s5p_device_pmu);
1127 return 0;
1128 }
1129 arch_initcall(s5p_pmu_init);
1130 #endif /* CONFIG_PLAT_S5P */
1131
1132 /* PWM Timer */
1133
1134 #ifdef CONFIG_SAMSUNG_DEV_PWM
1135
1136 #define TIMER_RESOURCE_SIZE (1)
1137
1138 #define TIMER_RESOURCE(_tmr, _irq) \
1139 (struct resource [TIMER_RESOURCE_SIZE]) { \
1140 [0] = { \
1141 .start = _irq, \
1142 .end = _irq, \
1143 .flags = IORESOURCE_IRQ \
1144 } \
1145 }
1146
1147 #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
1148 .name = "s3c24xx-pwm", \
1149 .id = _tmr_no, \
1150 .num_resources = TIMER_RESOURCE_SIZE, \
1151 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
1152
1153 /*
1154 * since we already have an static mapping for the timer,
1155 * we do not bother setting any IO resource for the base.
1156 */
1157
1158 struct platform_device s3c_device_timer[] = {
1159 [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
1160 [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
1161 [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
1162 [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
1163 [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
1164 };
1165 #endif /* CONFIG_SAMSUNG_DEV_PWM */
1166
1167 /* RTC */
1168
1169 #ifdef CONFIG_PLAT_S3C24XX
1170 static struct resource s3c_rtc_resource[] = {
1171 [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
1172 [1] = DEFINE_RES_IRQ(IRQ_RTC),
1173 [2] = DEFINE_RES_IRQ(IRQ_TICK),
1174 };
1175
1176 struct platform_device s3c_device_rtc = {
1177 .name = "s3c2410-rtc",
1178 .id = -1,
1179 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1180 .resource = s3c_rtc_resource,
1181 };
1182 #endif /* CONFIG_PLAT_S3C24XX */
1183
1184 #ifdef CONFIG_S3C_DEV_RTC
1185 static struct resource s3c_rtc_resource[] = {
1186 [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
1187 [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
1188 [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
1189 };
1190
1191 struct platform_device s3c_device_rtc = {
1192 .name = "s3c64xx-rtc",
1193 .id = -1,
1194 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1195 .resource = s3c_rtc_resource,
1196 };
1197 #endif /* CONFIG_S3C_DEV_RTC */
1198
1199 /* SDI */
1200
1201 #ifdef CONFIG_PLAT_S3C24XX
1202 static struct resource s3c_sdi_resource[] = {
1203 [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
1204 [1] = DEFINE_RES_IRQ(IRQ_SDI),
1205 };
1206
1207 struct platform_device s3c_device_sdi = {
1208 .name = "s3c2410-sdi",
1209 .id = -1,
1210 .num_resources = ARRAY_SIZE(s3c_sdi_resource),
1211 .resource = s3c_sdi_resource,
1212 };
1213
s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata * pdata)1214 void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
1215 {
1216 s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
1217 &s3c_device_sdi);
1218 }
1219 #endif /* CONFIG_PLAT_S3C24XX */
1220
1221 /* SPI */
1222
1223 #ifdef CONFIG_PLAT_S3C24XX
1224 static struct resource s3c_spi0_resource[] = {
1225 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
1226 [1] = DEFINE_RES_IRQ(IRQ_SPI0),
1227 };
1228
1229 struct platform_device s3c_device_spi0 = {
1230 .name = "s3c2410-spi",
1231 .id = 0,
1232 .num_resources = ARRAY_SIZE(s3c_spi0_resource),
1233 .resource = s3c_spi0_resource,
1234 .dev = {
1235 .dma_mask = &samsung_device_dma_mask,
1236 .coherent_dma_mask = DMA_BIT_MASK(32),
1237 }
1238 };
1239
1240 static struct resource s3c_spi1_resource[] = {
1241 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
1242 [1] = DEFINE_RES_IRQ(IRQ_SPI1),
1243 };
1244
1245 struct platform_device s3c_device_spi1 = {
1246 .name = "s3c2410-spi",
1247 .id = 1,
1248 .num_resources = ARRAY_SIZE(s3c_spi1_resource),
1249 .resource = s3c_spi1_resource,
1250 .dev = {
1251 .dma_mask = &samsung_device_dma_mask,
1252 .coherent_dma_mask = DMA_BIT_MASK(32),
1253 }
1254 };
1255 #endif /* CONFIG_PLAT_S3C24XX */
1256
1257 /* Touchscreen */
1258
1259 #ifdef CONFIG_PLAT_S3C24XX
1260 static struct resource s3c_ts_resource[] = {
1261 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
1262 [1] = DEFINE_RES_IRQ(IRQ_TC),
1263 };
1264
1265 struct platform_device s3c_device_ts = {
1266 .name = "s3c2410-ts",
1267 .id = -1,
1268 .dev.parent = &s3c_device_adc.dev,
1269 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1270 .resource = s3c_ts_resource,
1271 };
1272
s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info * hard_s3c2410ts_info)1273 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
1274 {
1275 s3c_set_platdata(hard_s3c2410ts_info,
1276 sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
1277 }
1278 #endif /* CONFIG_PLAT_S3C24XX */
1279
1280 #ifdef CONFIG_SAMSUNG_DEV_TS
1281 static struct resource s3c_ts_resource[] = {
1282 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
1283 [1] = DEFINE_RES_IRQ(IRQ_TC),
1284 };
1285
1286 static struct s3c2410_ts_mach_info default_ts_data __initdata = {
1287 .delay = 10000,
1288 .presc = 49,
1289 .oversampling_shift = 2,
1290 };
1291
1292 struct platform_device s3c_device_ts = {
1293 .name = "s3c64xx-ts",
1294 .id = -1,
1295 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1296 .resource = s3c_ts_resource,
1297 };
1298
s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info * pd)1299 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
1300 {
1301 if (!pd)
1302 pd = &default_ts_data;
1303
1304 s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
1305 &s3c_device_ts);
1306 }
1307 #endif /* CONFIG_SAMSUNG_DEV_TS */
1308
1309 /* TV */
1310
1311 #ifdef CONFIG_S5P_DEV_TV
1312
1313 static struct resource s5p_hdmi_resources[] = {
1314 [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
1315 [1] = DEFINE_RES_IRQ(IRQ_HDMI),
1316 };
1317
1318 struct platform_device s5p_device_hdmi = {
1319 .name = "s5p-hdmi",
1320 .id = -1,
1321 .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
1322 .resource = s5p_hdmi_resources,
1323 };
1324
1325 static struct resource s5p_sdo_resources[] = {
1326 [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
1327 [1] = DEFINE_RES_IRQ(IRQ_SDO),
1328 };
1329
1330 struct platform_device s5p_device_sdo = {
1331 .name = "s5p-sdo",
1332 .id = -1,
1333 .num_resources = ARRAY_SIZE(s5p_sdo_resources),
1334 .resource = s5p_sdo_resources,
1335 };
1336
1337 static struct resource s5p_mixer_resources[] = {
1338 [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
1339 [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
1340 [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
1341 };
1342
1343 struct platform_device s5p_device_mixer = {
1344 .name = "s5p-mixer",
1345 .id = -1,
1346 .num_resources = ARRAY_SIZE(s5p_mixer_resources),
1347 .resource = s5p_mixer_resources,
1348 .dev = {
1349 .dma_mask = &samsung_device_dma_mask,
1350 .coherent_dma_mask = DMA_BIT_MASK(32),
1351 }
1352 };
1353 #endif /* CONFIG_S5P_DEV_TV */
1354
1355 /* USB */
1356
1357 #ifdef CONFIG_S3C_DEV_USB_HOST
1358 static struct resource s3c_usb_resource[] = {
1359 [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
1360 [1] = DEFINE_RES_IRQ(IRQ_USBH),
1361 };
1362
1363 struct platform_device s3c_device_ohci = {
1364 .name = "s3c2410-ohci",
1365 .id = -1,
1366 .num_resources = ARRAY_SIZE(s3c_usb_resource),
1367 .resource = s3c_usb_resource,
1368 .dev = {
1369 .dma_mask = &samsung_device_dma_mask,
1370 .coherent_dma_mask = DMA_BIT_MASK(32),
1371 }
1372 };
1373
1374 /*
1375 * s3c_ohci_set_platdata - initialise OHCI device platform data
1376 * @info: The platform data.
1377 *
1378 * This call copies the @info passed in and sets the device .platform_data
1379 * field to that copy. The @info is copied so that the original can be marked
1380 * __initdata.
1381 */
1382
s3c_ohci_set_platdata(struct s3c2410_hcd_info * info)1383 void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
1384 {
1385 s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
1386 &s3c_device_ohci);
1387 }
1388 #endif /* CONFIG_S3C_DEV_USB_HOST */
1389
1390 /* USB Device (Gadget) */
1391
1392 #ifdef CONFIG_PLAT_S3C24XX
1393 static struct resource s3c_usbgadget_resource[] = {
1394 [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
1395 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1396 };
1397
1398 struct platform_device s3c_device_usbgadget = {
1399 .name = "s3c2410-usbgadget",
1400 .id = -1,
1401 .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
1402 .resource = s3c_usbgadget_resource,
1403 };
1404
s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info * pd)1405 void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
1406 {
1407 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
1408 }
1409 #endif /* CONFIG_PLAT_S3C24XX */
1410
1411 /* USB EHCI Host Controller */
1412
1413 #ifdef CONFIG_S5P_DEV_USB_EHCI
1414 static struct resource s5p_ehci_resource[] = {
1415 [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
1416 [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
1417 };
1418
1419 struct platform_device s5p_device_ehci = {
1420 .name = "s5p-ehci",
1421 .id = -1,
1422 .num_resources = ARRAY_SIZE(s5p_ehci_resource),
1423 .resource = s5p_ehci_resource,
1424 .dev = {
1425 .dma_mask = &samsung_device_dma_mask,
1426 .coherent_dma_mask = DMA_BIT_MASK(32),
1427 }
1428 };
1429
s5p_ehci_set_platdata(struct s5p_ehci_platdata * pd)1430 void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
1431 {
1432 struct s5p_ehci_platdata *npd;
1433
1434 npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
1435 &s5p_device_ehci);
1436
1437 if (!npd->phy_init)
1438 npd->phy_init = s5p_usb_phy_init;
1439 if (!npd->phy_exit)
1440 npd->phy_exit = s5p_usb_phy_exit;
1441 }
1442 #endif /* CONFIG_S5P_DEV_USB_EHCI */
1443
1444 /* USB HSOTG */
1445
1446 #ifdef CONFIG_S3C_DEV_USB_HSOTG
1447 static struct resource s3c_usb_hsotg_resources[] = {
1448 [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
1449 [1] = DEFINE_RES_IRQ(IRQ_OTG),
1450 };
1451
1452 struct platform_device s3c_device_usb_hsotg = {
1453 .name = "s3c-hsotg",
1454 .id = -1,
1455 .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
1456 .resource = s3c_usb_hsotg_resources,
1457 .dev = {
1458 .dma_mask = &samsung_device_dma_mask,
1459 .coherent_dma_mask = DMA_BIT_MASK(32),
1460 },
1461 };
1462
s3c_hsotg_set_platdata(struct s3c_hsotg_plat * pd)1463 void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
1464 {
1465 struct s3c_hsotg_plat *npd;
1466
1467 npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
1468 &s3c_device_usb_hsotg);
1469
1470 if (!npd->phy_init)
1471 npd->phy_init = s5p_usb_phy_init;
1472 if (!npd->phy_exit)
1473 npd->phy_exit = s5p_usb_phy_exit;
1474 }
1475 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
1476
1477 /* USB High Spped 2.0 Device (Gadget) */
1478
1479 #ifdef CONFIG_PLAT_S3C24XX
1480 static struct resource s3c_hsudc_resource[] = {
1481 [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
1482 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1483 };
1484
1485 struct platform_device s3c_device_usb_hsudc = {
1486 .name = "s3c-hsudc",
1487 .id = -1,
1488 .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
1489 .resource = s3c_hsudc_resource,
1490 .dev = {
1491 .dma_mask = &samsung_device_dma_mask,
1492 .coherent_dma_mask = DMA_BIT_MASK(32),
1493 },
1494 };
1495
s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata * pd)1496 void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
1497 {
1498 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
1499 }
1500 #endif /* CONFIG_PLAT_S3C24XX */
1501
1502 /* WDT */
1503
1504 #ifdef CONFIG_S3C_DEV_WDT
1505 static struct resource s3c_wdt_resource[] = {
1506 [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
1507 [1] = DEFINE_RES_IRQ(IRQ_WDT),
1508 };
1509
1510 struct platform_device s3c_device_wdt = {
1511 .name = "s3c2410-wdt",
1512 .id = -1,
1513 .num_resources = ARRAY_SIZE(s3c_wdt_resource),
1514 .resource = s3c_wdt_resource,
1515 };
1516 #endif /* CONFIG_S3C_DEV_WDT */
1517
1518 #ifdef CONFIG_S3C64XX_DEV_SPI0
1519 static struct resource s3c64xx_spi0_resource[] = {
1520 [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
1521 [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
1522 [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
1523 [3] = DEFINE_RES_IRQ(IRQ_SPI0),
1524 };
1525
1526 struct platform_device s3c64xx_device_spi0 = {
1527 .name = "s3c64xx-spi",
1528 .id = 0,
1529 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1530 .resource = s3c64xx_spi0_resource,
1531 .dev = {
1532 .dma_mask = &samsung_device_dma_mask,
1533 .coherent_dma_mask = DMA_BIT_MASK(32),
1534 },
1535 };
1536
s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info * pd,int src_clk_nr,int num_cs)1537 void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
1538 int src_clk_nr, int num_cs)
1539 {
1540 if (!pd) {
1541 pr_err("%s:Need to pass platform data\n", __func__);
1542 return;
1543 }
1544
1545 /* Reject invalid configuration */
1546 if (!num_cs || src_clk_nr < 0) {
1547 pr_err("%s: Invalid SPI configuration\n", __func__);
1548 return;
1549 }
1550
1551 pd->num_cs = num_cs;
1552 pd->src_clk_nr = src_clk_nr;
1553 if (!pd->cfg_gpio)
1554 pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
1555
1556 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
1557 }
1558 #endif /* CONFIG_S3C64XX_DEV_SPI0 */
1559
1560 #ifdef CONFIG_S3C64XX_DEV_SPI1
1561 static struct resource s3c64xx_spi1_resource[] = {
1562 [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
1563 [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
1564 [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
1565 [3] = DEFINE_RES_IRQ(IRQ_SPI1),
1566 };
1567
1568 struct platform_device s3c64xx_device_spi1 = {
1569 .name = "s3c64xx-spi",
1570 .id = 1,
1571 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1572 .resource = s3c64xx_spi1_resource,
1573 .dev = {
1574 .dma_mask = &samsung_device_dma_mask,
1575 .coherent_dma_mask = DMA_BIT_MASK(32),
1576 },
1577 };
1578
s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info * pd,int src_clk_nr,int num_cs)1579 void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
1580 int src_clk_nr, int num_cs)
1581 {
1582 if (!pd) {
1583 pr_err("%s:Need to pass platform data\n", __func__);
1584 return;
1585 }
1586
1587 /* Reject invalid configuration */
1588 if (!num_cs || src_clk_nr < 0) {
1589 pr_err("%s: Invalid SPI configuration\n", __func__);
1590 return;
1591 }
1592
1593 pd->num_cs = num_cs;
1594 pd->src_clk_nr = src_clk_nr;
1595 if (!pd->cfg_gpio)
1596 pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
1597
1598 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
1599 }
1600 #endif /* CONFIG_S3C64XX_DEV_SPI1 */
1601
1602 #ifdef CONFIG_S3C64XX_DEV_SPI2
1603 static struct resource s3c64xx_spi2_resource[] = {
1604 [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
1605 [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
1606 [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
1607 [3] = DEFINE_RES_IRQ(IRQ_SPI2),
1608 };
1609
1610 struct platform_device s3c64xx_device_spi2 = {
1611 .name = "s3c64xx-spi",
1612 .id = 2,
1613 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1614 .resource = s3c64xx_spi2_resource,
1615 .dev = {
1616 .dma_mask = &samsung_device_dma_mask,
1617 .coherent_dma_mask = DMA_BIT_MASK(32),
1618 },
1619 };
1620
s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info * pd,int src_clk_nr,int num_cs)1621 void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
1622 int src_clk_nr, int num_cs)
1623 {
1624 if (!pd) {
1625 pr_err("%s:Need to pass platform data\n", __func__);
1626 return;
1627 }
1628
1629 /* Reject invalid configuration */
1630 if (!num_cs || src_clk_nr < 0) {
1631 pr_err("%s: Invalid SPI configuration\n", __func__);
1632 return;
1633 }
1634
1635 pd->num_cs = num_cs;
1636 pd->src_clk_nr = src_clk_nr;
1637 if (!pd->cfg_gpio)
1638 pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
1639
1640 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
1641 }
1642 #endif /* CONFIG_S3C64XX_DEV_SPI2 */
1643