1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
41 #ifdef CONFIG_SPARC
42 #include <linux/sunserialcore.h>
43 #endif
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47
48 #include "8250.h"
49
50 /*
51 * Configuration:
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
59 static struct uart_driver serial8250_reg;
60
serial_index(struct uart_port * port)61 static int serial_index(struct uart_port *port)
62 {
63 return (serial8250_reg.minor - 64) + port->line;
64 }
65
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
68 /*
69 * Debugging.
70 */
71 #if 0
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
73 #else
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
75 #endif
76
77 #if 0
78 #define DEBUG_INTR(fmt...) printk(fmt)
79 #else
80 #define DEBUG_INTR(fmt...) do { } while (0)
81 #endif
82
83 #define PASS_LIMIT 512
84
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
90 #endif
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
93 #endif
94
95 /*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99 #define CONFIG_HUB6 1
100
101 #include <asm/serial.h>
102 /*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
109 #endif
110
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 };
114
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
116
117 #ifdef CONFIG_SERIAL_8250_RSA
118
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
123
124 struct irq_info {
125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
129 };
130
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
134
135 /*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138 static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
241 },
242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO,
255 },
256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
284 },
285 };
286
287 #if defined(CONFIG_MIPS_ALCHEMY)
288
289 /* Au1x00 UART hardware has a weird register layout */
290 static const u8 au_io_in_map[] = {
291 [UART_RX] = 0,
292 [UART_IER] = 2,
293 [UART_IIR] = 3,
294 [UART_LCR] = 5,
295 [UART_MCR] = 6,
296 [UART_LSR] = 7,
297 [UART_MSR] = 8,
298 };
299
300 static const u8 au_io_out_map[] = {
301 [UART_TX] = 1,
302 [UART_IER] = 2,
303 [UART_FCR] = 4,
304 [UART_LCR] = 5,
305 [UART_MCR] = 6,
306 };
307
308 /* sane hardware needs no mapping */
map_8250_in_reg(struct uart_port * p,int offset)309 static inline int map_8250_in_reg(struct uart_port *p, int offset)
310 {
311 if (p->iotype != UPIO_AU)
312 return offset;
313 return au_io_in_map[offset];
314 }
315
map_8250_out_reg(struct uart_port * p,int offset)316 static inline int map_8250_out_reg(struct uart_port *p, int offset)
317 {
318 if (p->iotype != UPIO_AU)
319 return offset;
320 return au_io_out_map[offset];
321 }
322
323 #elif defined(CONFIG_SERIAL_8250_RM9K)
324
325 static const u8
326 regmap_in[8] = {
327 [UART_RX] = 0x00,
328 [UART_IER] = 0x0c,
329 [UART_IIR] = 0x14,
330 [UART_LCR] = 0x1c,
331 [UART_MCR] = 0x20,
332 [UART_LSR] = 0x24,
333 [UART_MSR] = 0x28,
334 [UART_SCR] = 0x2c
335 },
336 regmap_out[8] = {
337 [UART_TX] = 0x04,
338 [UART_IER] = 0x0c,
339 [UART_FCR] = 0x18,
340 [UART_LCR] = 0x1c,
341 [UART_MCR] = 0x20,
342 [UART_LSR] = 0x24,
343 [UART_MSR] = 0x28,
344 [UART_SCR] = 0x2c
345 };
346
map_8250_in_reg(struct uart_port * p,int offset)347 static inline int map_8250_in_reg(struct uart_port *p, int offset)
348 {
349 if (p->iotype != UPIO_RM9000)
350 return offset;
351 return regmap_in[offset];
352 }
353
map_8250_out_reg(struct uart_port * p,int offset)354 static inline int map_8250_out_reg(struct uart_port *p, int offset)
355 {
356 if (p->iotype != UPIO_RM9000)
357 return offset;
358 return regmap_out[offset];
359 }
360
361 #else
362
363 /* sane hardware needs no mapping */
364 #define map_8250_in_reg(up, offset) (offset)
365 #define map_8250_out_reg(up, offset) (offset)
366
367 #endif
368
hub6_serial_in(struct uart_port * p,int offset)369 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
370 {
371 offset = map_8250_in_reg(p, offset) << p->regshift;
372 outb(p->hub6 - 1 + offset, p->iobase);
373 return inb(p->iobase + 1);
374 }
375
hub6_serial_out(struct uart_port * p,int offset,int value)376 static void hub6_serial_out(struct uart_port *p, int offset, int value)
377 {
378 offset = map_8250_out_reg(p, offset) << p->regshift;
379 outb(p->hub6 - 1 + offset, p->iobase);
380 outb(value, p->iobase + 1);
381 }
382
mem_serial_in(struct uart_port * p,int offset)383 static unsigned int mem_serial_in(struct uart_port *p, int offset)
384 {
385 offset = map_8250_in_reg(p, offset) << p->regshift;
386 return readb(p->membase + offset);
387 }
388
mem_serial_out(struct uart_port * p,int offset,int value)389 static void mem_serial_out(struct uart_port *p, int offset, int value)
390 {
391 offset = map_8250_out_reg(p, offset) << p->regshift;
392 writeb(value, p->membase + offset);
393 }
394
mem32_serial_out(struct uart_port * p,int offset,int value)395 static void mem32_serial_out(struct uart_port *p, int offset, int value)
396 {
397 offset = map_8250_out_reg(p, offset) << p->regshift;
398 writel(value, p->membase + offset);
399 }
400
mem32_serial_in(struct uart_port * p,int offset)401 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
402 {
403 offset = map_8250_in_reg(p, offset) << p->regshift;
404 return readl(p->membase + offset);
405 }
406
au_serial_in(struct uart_port * p,int offset)407 static unsigned int au_serial_in(struct uart_port *p, int offset)
408 {
409 offset = map_8250_in_reg(p, offset) << p->regshift;
410 return __raw_readl(p->membase + offset);
411 }
412
au_serial_out(struct uart_port * p,int offset,int value)413 static void au_serial_out(struct uart_port *p, int offset, int value)
414 {
415 offset = map_8250_out_reg(p, offset) << p->regshift;
416 __raw_writel(value, p->membase + offset);
417 }
418
io_serial_in(struct uart_port * p,int offset)419 static unsigned int io_serial_in(struct uart_port *p, int offset)
420 {
421 offset = map_8250_in_reg(p, offset) << p->regshift;
422 return inb(p->iobase + offset);
423 }
424
io_serial_out(struct uart_port * p,int offset,int value)425 static void io_serial_out(struct uart_port *p, int offset, int value)
426 {
427 offset = map_8250_out_reg(p, offset) << p->regshift;
428 outb(value, p->iobase + offset);
429 }
430
431 static int serial8250_default_handle_irq(struct uart_port *port);
432
set_io_from_upio(struct uart_port * p)433 static void set_io_from_upio(struct uart_port *p)
434 {
435 struct uart_8250_port *up =
436 container_of(p, struct uart_8250_port, port);
437 switch (p->iotype) {
438 case UPIO_HUB6:
439 p->serial_in = hub6_serial_in;
440 p->serial_out = hub6_serial_out;
441 break;
442
443 case UPIO_MEM:
444 p->serial_in = mem_serial_in;
445 p->serial_out = mem_serial_out;
446 break;
447
448 case UPIO_RM9000:
449 case UPIO_MEM32:
450 p->serial_in = mem32_serial_in;
451 p->serial_out = mem32_serial_out;
452 break;
453
454 case UPIO_AU:
455 p->serial_in = au_serial_in;
456 p->serial_out = au_serial_out;
457 break;
458
459 default:
460 p->serial_in = io_serial_in;
461 p->serial_out = io_serial_out;
462 break;
463 }
464 /* Remember loaded iotype */
465 up->cur_iotype = p->iotype;
466 p->handle_irq = serial8250_default_handle_irq;
467 }
468
469 static void
serial_port_out_sync(struct uart_port * p,int offset,int value)470 serial_port_out_sync(struct uart_port *p, int offset, int value)
471 {
472 switch (p->iotype) {
473 case UPIO_MEM:
474 case UPIO_MEM32:
475 case UPIO_AU:
476 p->serial_out(p, offset, value);
477 p->serial_in(p, UART_LCR); /* safe, no side-effects */
478 break;
479 default:
480 p->serial_out(p, offset, value);
481 }
482 }
483
484 /* Uart divisor latch read */
_serial_dl_read(struct uart_8250_port * up)485 static inline int _serial_dl_read(struct uart_8250_port *up)
486 {
487 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
488 }
489
490 /* Uart divisor latch write */
_serial_dl_write(struct uart_8250_port * up,int value)491 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
492 {
493 serial_out(up, UART_DLL, value & 0xff);
494 serial_out(up, UART_DLM, value >> 8 & 0xff);
495 }
496
497 #if defined(CONFIG_MIPS_ALCHEMY)
498 /* Au1x00 haven't got a standard divisor latch */
serial_dl_read(struct uart_8250_port * up)499 static int serial_dl_read(struct uart_8250_port *up)
500 {
501 if (up->port.iotype == UPIO_AU)
502 return __raw_readl(up->port.membase + 0x28);
503 else
504 return _serial_dl_read(up);
505 }
506
serial_dl_write(struct uart_8250_port * up,int value)507 static void serial_dl_write(struct uart_8250_port *up, int value)
508 {
509 if (up->port.iotype == UPIO_AU)
510 __raw_writel(value, up->port.membase + 0x28);
511 else
512 _serial_dl_write(up, value);
513 }
514 #elif defined(CONFIG_SERIAL_8250_RM9K)
serial_dl_read(struct uart_8250_port * up)515 static int serial_dl_read(struct uart_8250_port *up)
516 {
517 return (up->port.iotype == UPIO_RM9000) ?
518 (((__raw_readl(up->port.membase + 0x10) << 8) |
519 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
520 _serial_dl_read(up);
521 }
522
serial_dl_write(struct uart_8250_port * up,int value)523 static void serial_dl_write(struct uart_8250_port *up, int value)
524 {
525 if (up->port.iotype == UPIO_RM9000) {
526 __raw_writel(value, up->port.membase + 0x08);
527 __raw_writel(value >> 8, up->port.membase + 0x10);
528 } else {
529 _serial_dl_write(up, value);
530 }
531 }
532 #else
533 #define serial_dl_read(up) _serial_dl_read(up)
534 #define serial_dl_write(up, value) _serial_dl_write(up, value)
535 #endif
536
537 /*
538 * For the 16C950
539 */
serial_icr_write(struct uart_8250_port * up,int offset,int value)540 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
541 {
542 serial_out(up, UART_SCR, offset);
543 serial_out(up, UART_ICR, value);
544 }
545
serial_icr_read(struct uart_8250_port * up,int offset)546 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
547 {
548 unsigned int value;
549
550 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
551 serial_out(up, UART_SCR, offset);
552 value = serial_in(up, UART_ICR);
553 serial_icr_write(up, UART_ACR, up->acr);
554
555 return value;
556 }
557
558 /*
559 * FIFO support.
560 */
serial8250_clear_fifos(struct uart_8250_port * p)561 static void serial8250_clear_fifos(struct uart_8250_port *p)
562 {
563 if (p->capabilities & UART_CAP_FIFO) {
564 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
565 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
566 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
567 serial_out(p, UART_FCR, 0);
568 }
569 }
570
571 /*
572 * IER sleep support. UARTs which have EFRs need the "extended
573 * capability" bit enabled. Note that on XR16C850s, we need to
574 * reset LCR to write to IER.
575 */
serial8250_set_sleep(struct uart_8250_port * p,int sleep)576 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
577 {
578 if (p->capabilities & UART_CAP_SLEEP) {
579 if (p->capabilities & UART_CAP_EFR) {
580 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
581 serial_out(p, UART_EFR, UART_EFR_ECB);
582 serial_out(p, UART_LCR, 0);
583 }
584 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
585 if (p->capabilities & UART_CAP_EFR) {
586 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
587 serial_out(p, UART_EFR, 0);
588 serial_out(p, UART_LCR, 0);
589 }
590 }
591 }
592
593 #ifdef CONFIG_SERIAL_8250_RSA
594 /*
595 * Attempts to turn on the RSA FIFO. Returns zero on failure.
596 * We set the port uart clock rate if we succeed.
597 */
__enable_rsa(struct uart_8250_port * up)598 static int __enable_rsa(struct uart_8250_port *up)
599 {
600 unsigned char mode;
601 int result;
602
603 mode = serial_in(up, UART_RSA_MSR);
604 result = mode & UART_RSA_MSR_FIFO;
605
606 if (!result) {
607 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
608 mode = serial_in(up, UART_RSA_MSR);
609 result = mode & UART_RSA_MSR_FIFO;
610 }
611
612 if (result)
613 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
614
615 return result;
616 }
617
enable_rsa(struct uart_8250_port * up)618 static void enable_rsa(struct uart_8250_port *up)
619 {
620 if (up->port.type == PORT_RSA) {
621 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
622 spin_lock_irq(&up->port.lock);
623 __enable_rsa(up);
624 spin_unlock_irq(&up->port.lock);
625 }
626 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
627 serial_out(up, UART_RSA_FRR, 0);
628 }
629 }
630
631 /*
632 * Attempts to turn off the RSA FIFO. Returns zero on failure.
633 * It is unknown why interrupts were disabled in here. However,
634 * the caller is expected to preserve this behaviour by grabbing
635 * the spinlock before calling this function.
636 */
disable_rsa(struct uart_8250_port * up)637 static void disable_rsa(struct uart_8250_port *up)
638 {
639 unsigned char mode;
640 int result;
641
642 if (up->port.type == PORT_RSA &&
643 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
644 spin_lock_irq(&up->port.lock);
645
646 mode = serial_in(up, UART_RSA_MSR);
647 result = !(mode & UART_RSA_MSR_FIFO);
648
649 if (!result) {
650 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
651 mode = serial_in(up, UART_RSA_MSR);
652 result = !(mode & UART_RSA_MSR_FIFO);
653 }
654
655 if (result)
656 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
657 spin_unlock_irq(&up->port.lock);
658 }
659 }
660 #endif /* CONFIG_SERIAL_8250_RSA */
661
662 /*
663 * This is a quickie test to see how big the FIFO is.
664 * It doesn't work at all the time, more's the pity.
665 */
size_fifo(struct uart_8250_port * up)666 static int size_fifo(struct uart_8250_port *up)
667 {
668 unsigned char old_fcr, old_mcr, old_lcr;
669 unsigned short old_dl;
670 int count;
671
672 old_lcr = serial_in(up, UART_LCR);
673 serial_out(up, UART_LCR, 0);
674 old_fcr = serial_in(up, UART_FCR);
675 old_mcr = serial_in(up, UART_MCR);
676 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
677 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
678 serial_out(up, UART_MCR, UART_MCR_LOOP);
679 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
680 old_dl = serial_dl_read(up);
681 serial_dl_write(up, 0x0001);
682 serial_out(up, UART_LCR, 0x03);
683 for (count = 0; count < 256; count++)
684 serial_out(up, UART_TX, count);
685 mdelay(20);/* FIXME - schedule_timeout */
686 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
687 (count < 256); count++)
688 serial_in(up, UART_RX);
689 serial_out(up, UART_FCR, old_fcr);
690 serial_out(up, UART_MCR, old_mcr);
691 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
692 serial_dl_write(up, old_dl);
693 serial_out(up, UART_LCR, old_lcr);
694
695 return count;
696 }
697
698 /*
699 * Read UART ID using the divisor method - set DLL and DLM to zero
700 * and the revision will be in DLL and device type in DLM. We
701 * preserve the device state across this.
702 */
autoconfig_read_divisor_id(struct uart_8250_port * p)703 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
704 {
705 unsigned char old_dll, old_dlm, old_lcr;
706 unsigned int id;
707
708 old_lcr = serial_in(p, UART_LCR);
709 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
710
711 old_dll = serial_in(p, UART_DLL);
712 old_dlm = serial_in(p, UART_DLM);
713
714 serial_out(p, UART_DLL, 0);
715 serial_out(p, UART_DLM, 0);
716
717 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
718
719 serial_out(p, UART_DLL, old_dll);
720 serial_out(p, UART_DLM, old_dlm);
721 serial_out(p, UART_LCR, old_lcr);
722
723 return id;
724 }
725
726 /*
727 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
728 * When this function is called we know it is at least a StarTech
729 * 16650 V2, but it might be one of several StarTech UARTs, or one of
730 * its clones. (We treat the broken original StarTech 16650 V1 as a
731 * 16550, and why not? Startech doesn't seem to even acknowledge its
732 * existence.)
733 *
734 * What evil have men's minds wrought...
735 */
autoconfig_has_efr(struct uart_8250_port * up)736 static void autoconfig_has_efr(struct uart_8250_port *up)
737 {
738 unsigned int id1, id2, id3, rev;
739
740 /*
741 * Everything with an EFR has SLEEP
742 */
743 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
744
745 /*
746 * First we check to see if it's an Oxford Semiconductor UART.
747 *
748 * If we have to do this here because some non-National
749 * Semiconductor clone chips lock up if you try writing to the
750 * LSR register (which serial_icr_read does)
751 */
752
753 /*
754 * Check for Oxford Semiconductor 16C950.
755 *
756 * EFR [4] must be set else this test fails.
757 *
758 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
759 * claims that it's needed for 952 dual UART's (which are not
760 * recommended for new designs).
761 */
762 up->acr = 0;
763 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
764 serial_out(up, UART_EFR, UART_EFR_ECB);
765 serial_out(up, UART_LCR, 0x00);
766 id1 = serial_icr_read(up, UART_ID1);
767 id2 = serial_icr_read(up, UART_ID2);
768 id3 = serial_icr_read(up, UART_ID3);
769 rev = serial_icr_read(up, UART_REV);
770
771 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
772
773 if (id1 == 0x16 && id2 == 0xC9 &&
774 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
775 up->port.type = PORT_16C950;
776
777 /*
778 * Enable work around for the Oxford Semiconductor 952 rev B
779 * chip which causes it to seriously miscalculate baud rates
780 * when DLL is 0.
781 */
782 if (id3 == 0x52 && rev == 0x01)
783 up->bugs |= UART_BUG_QUOT;
784 return;
785 }
786
787 /*
788 * We check for a XR16C850 by setting DLL and DLM to 0, and then
789 * reading back DLL and DLM. The chip type depends on the DLM
790 * value read back:
791 * 0x10 - XR16C850 and the DLL contains the chip revision.
792 * 0x12 - XR16C2850.
793 * 0x14 - XR16C854.
794 */
795 id1 = autoconfig_read_divisor_id(up);
796 DEBUG_AUTOCONF("850id=%04x ", id1);
797
798 id2 = id1 >> 8;
799 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
800 up->port.type = PORT_16850;
801 return;
802 }
803
804 /*
805 * It wasn't an XR16C850.
806 *
807 * We distinguish between the '654 and the '650 by counting
808 * how many bytes are in the FIFO. I'm using this for now,
809 * since that's the technique that was sent to me in the
810 * serial driver update, but I'm not convinced this works.
811 * I've had problems doing this in the past. -TYT
812 */
813 if (size_fifo(up) == 64)
814 up->port.type = PORT_16654;
815 else
816 up->port.type = PORT_16650V2;
817 }
818
819 /*
820 * We detected a chip without a FIFO. Only two fall into
821 * this category - the original 8250 and the 16450. The
822 * 16450 has a scratch register (accessible with LCR=0)
823 */
autoconfig_8250(struct uart_8250_port * up)824 static void autoconfig_8250(struct uart_8250_port *up)
825 {
826 unsigned char scratch, status1, status2;
827
828 up->port.type = PORT_8250;
829
830 scratch = serial_in(up, UART_SCR);
831 serial_out(up, UART_SCR, 0xa5);
832 status1 = serial_in(up, UART_SCR);
833 serial_out(up, UART_SCR, 0x5a);
834 status2 = serial_in(up, UART_SCR);
835 serial_out(up, UART_SCR, scratch);
836
837 if (status1 == 0xa5 && status2 == 0x5a)
838 up->port.type = PORT_16450;
839 }
840
broken_efr(struct uart_8250_port * up)841 static int broken_efr(struct uart_8250_port *up)
842 {
843 /*
844 * Exar ST16C2550 "A2" devices incorrectly detect as
845 * having an EFR, and report an ID of 0x0201. See
846 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
847 */
848 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
849 return 1;
850
851 return 0;
852 }
853
ns16550a_goto_highspeed(struct uart_8250_port * up)854 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
855 {
856 unsigned char status;
857
858 status = serial_in(up, 0x04); /* EXCR2 */
859 #define PRESL(x) ((x) & 0x30)
860 if (PRESL(status) == 0x10) {
861 /* already in high speed mode */
862 return 0;
863 } else {
864 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
865 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
866 serial_out(up, 0x04, status);
867 }
868 return 1;
869 }
870
871 /*
872 * We know that the chip has FIFOs. Does it have an EFR? The
873 * EFR is located in the same register position as the IIR and
874 * we know the top two bits of the IIR are currently set. The
875 * EFR should contain zero. Try to read the EFR.
876 */
autoconfig_16550a(struct uart_8250_port * up)877 static void autoconfig_16550a(struct uart_8250_port *up)
878 {
879 unsigned char status1, status2;
880 unsigned int iersave;
881
882 up->port.type = PORT_16550A;
883 up->capabilities |= UART_CAP_FIFO;
884
885 /*
886 * Check for presence of the EFR when DLAB is set.
887 * Only ST16C650V1 UARTs pass this test.
888 */
889 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
890 if (serial_in(up, UART_EFR) == 0) {
891 serial_out(up, UART_EFR, 0xA8);
892 if (serial_in(up, UART_EFR) != 0) {
893 DEBUG_AUTOCONF("EFRv1 ");
894 up->port.type = PORT_16650;
895 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
896 } else {
897 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
898 }
899 serial_out(up, UART_EFR, 0);
900 return;
901 }
902
903 /*
904 * Maybe it requires 0xbf to be written to the LCR.
905 * (other ST16C650V2 UARTs, TI16C752A, etc)
906 */
907 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
908 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
909 DEBUG_AUTOCONF("EFRv2 ");
910 autoconfig_has_efr(up);
911 return;
912 }
913
914 /*
915 * Check for a National Semiconductor SuperIO chip.
916 * Attempt to switch to bank 2, read the value of the LOOP bit
917 * from EXCR1. Switch back to bank 0, change it in MCR. Then
918 * switch back to bank 2, read it from EXCR1 again and check
919 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
920 */
921 serial_out(up, UART_LCR, 0);
922 status1 = serial_in(up, UART_MCR);
923 serial_out(up, UART_LCR, 0xE0);
924 status2 = serial_in(up, 0x02); /* EXCR1 */
925
926 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
927 serial_out(up, UART_LCR, 0);
928 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
929 serial_out(up, UART_LCR, 0xE0);
930 status2 = serial_in(up, 0x02); /* EXCR1 */
931 serial_out(up, UART_LCR, 0);
932 serial_out(up, UART_MCR, status1);
933
934 if ((status2 ^ status1) & UART_MCR_LOOP) {
935 unsigned short quot;
936
937 serial_out(up, UART_LCR, 0xE0);
938
939 quot = serial_dl_read(up);
940 quot <<= 3;
941
942 if (ns16550a_goto_highspeed(up))
943 serial_dl_write(up, quot);
944
945 serial_out(up, UART_LCR, 0);
946
947 up->port.uartclk = 921600*16;
948 up->port.type = PORT_NS16550A;
949 up->capabilities |= UART_NATSEMI;
950 return;
951 }
952 }
953
954 /*
955 * No EFR. Try to detect a TI16750, which only sets bit 5 of
956 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
957 * Try setting it with and without DLAB set. Cheap clones
958 * set bit 5 without DLAB set.
959 */
960 serial_out(up, UART_LCR, 0);
961 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
962 status1 = serial_in(up, UART_IIR) >> 5;
963 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
964 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
965 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
966 status2 = serial_in(up, UART_IIR) >> 5;
967 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
968 serial_out(up, UART_LCR, 0);
969
970 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
971
972 if (status1 == 6 && status2 == 7) {
973 up->port.type = PORT_16750;
974 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
975 return;
976 }
977
978 /*
979 * Try writing and reading the UART_IER_UUE bit (b6).
980 * If it works, this is probably one of the Xscale platform's
981 * internal UARTs.
982 * We're going to explicitly set the UUE bit to 0 before
983 * trying to write and read a 1 just to make sure it's not
984 * already a 1 and maybe locked there before we even start start.
985 */
986 iersave = serial_in(up, UART_IER);
987 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
988 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
989 /*
990 * OK it's in a known zero state, try writing and reading
991 * without disturbing the current state of the other bits.
992 */
993 serial_out(up, UART_IER, iersave | UART_IER_UUE);
994 if (serial_in(up, UART_IER) & UART_IER_UUE) {
995 /*
996 * It's an Xscale.
997 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
998 */
999 DEBUG_AUTOCONF("Xscale ");
1000 up->port.type = PORT_XSCALE;
1001 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1002 return;
1003 }
1004 } else {
1005 /*
1006 * If we got here we couldn't force the IER_UUE bit to 0.
1007 * Log it and continue.
1008 */
1009 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1010 }
1011 serial_out(up, UART_IER, iersave);
1012
1013 /*
1014 * Exar uarts have EFR in a weird location
1015 */
1016 if (up->port.flags & UPF_EXAR_EFR) {
1017 up->port.type = PORT_XR17D15X;
1018 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1019 }
1020
1021 /*
1022 * We distinguish between 16550A and U6 16550A by counting
1023 * how many bytes are in the FIFO.
1024 */
1025 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1026 up->port.type = PORT_U6_16550A;
1027 up->capabilities |= UART_CAP_AFE;
1028 }
1029 }
1030
1031 /*
1032 * This routine is called by rs_init() to initialize a specific serial
1033 * port. It determines what type of UART chip this serial port is
1034 * using: 8250, 16450, 16550, 16550A. The important question is
1035 * whether or not this UART is a 16550A or not, since this will
1036 * determine whether or not we can use its FIFO features or not.
1037 */
autoconfig(struct uart_8250_port * up,unsigned int probeflags)1038 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1039 {
1040 unsigned char status1, scratch, scratch2, scratch3;
1041 unsigned char save_lcr, save_mcr;
1042 struct uart_port *port = &up->port;
1043 unsigned long flags;
1044
1045 if (!port->iobase && !port->mapbase && !port->membase)
1046 return;
1047
1048 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1049 serial_index(port), port->iobase, port->membase);
1050
1051 /*
1052 * We really do need global IRQs disabled here - we're going to
1053 * be frobbing the chips IRQ enable register to see if it exists.
1054 */
1055 spin_lock_irqsave(&port->lock, flags);
1056
1057 up->capabilities = 0;
1058 up->bugs = 0;
1059
1060 if (!(port->flags & UPF_BUGGY_UART)) {
1061 /*
1062 * Do a simple existence test first; if we fail this,
1063 * there's no point trying anything else.
1064 *
1065 * 0x80 is used as a nonsense port to prevent against
1066 * false positives due to ISA bus float. The
1067 * assumption is that 0x80 is a non-existent port;
1068 * which should be safe since include/asm/io.h also
1069 * makes this assumption.
1070 *
1071 * Note: this is safe as long as MCR bit 4 is clear
1072 * and the device is in "PC" mode.
1073 */
1074 scratch = serial_in(up, UART_IER);
1075 serial_out(up, UART_IER, 0);
1076 #ifdef __i386__
1077 outb(0xff, 0x080);
1078 #endif
1079 /*
1080 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1081 * 16C754B) allow only to modify them if an EFR bit is set.
1082 */
1083 scratch2 = serial_in(up, UART_IER) & 0x0f;
1084 serial_out(up, UART_IER, 0x0F);
1085 #ifdef __i386__
1086 outb(0, 0x080);
1087 #endif
1088 scratch3 = serial_in(up, UART_IER) & 0x0f;
1089 serial_out(up, UART_IER, scratch);
1090 if (scratch2 != 0 || scratch3 != 0x0F) {
1091 /*
1092 * We failed; there's nothing here
1093 */
1094 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1095 scratch2, scratch3);
1096 goto out;
1097 }
1098 }
1099
1100 save_mcr = serial_in(up, UART_MCR);
1101 save_lcr = serial_in(up, UART_LCR);
1102
1103 /*
1104 * Check to see if a UART is really there. Certain broken
1105 * internal modems based on the Rockwell chipset fail this
1106 * test, because they apparently don't implement the loopback
1107 * test mode. So this test is skipped on the COM 1 through
1108 * COM 4 ports. This *should* be safe, since no board
1109 * manufacturer would be stupid enough to design a board
1110 * that conflicts with COM 1-4 --- we hope!
1111 */
1112 if (!(port->flags & UPF_SKIP_TEST)) {
1113 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1114 status1 = serial_in(up, UART_MSR) & 0xF0;
1115 serial_out(up, UART_MCR, save_mcr);
1116 if (status1 != 0x90) {
1117 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1118 status1);
1119 goto out;
1120 }
1121 }
1122
1123 /*
1124 * We're pretty sure there's a port here. Lets find out what
1125 * type of port it is. The IIR top two bits allows us to find
1126 * out if it's 8250 or 16450, 16550, 16550A or later. This
1127 * determines what we test for next.
1128 *
1129 * We also initialise the EFR (if any) to zero for later. The
1130 * EFR occupies the same register location as the FCR and IIR.
1131 */
1132 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1133 serial_out(up, UART_EFR, 0);
1134 serial_out(up, UART_LCR, 0);
1135
1136 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1137 scratch = serial_in(up, UART_IIR) >> 6;
1138
1139 DEBUG_AUTOCONF("iir=%d ", scratch);
1140
1141 switch (scratch) {
1142 case 0:
1143 autoconfig_8250(up);
1144 break;
1145 case 1:
1146 port->type = PORT_UNKNOWN;
1147 break;
1148 case 2:
1149 port->type = PORT_16550;
1150 break;
1151 case 3:
1152 autoconfig_16550a(up);
1153 break;
1154 }
1155
1156 #ifdef CONFIG_SERIAL_8250_RSA
1157 /*
1158 * Only probe for RSA ports if we got the region.
1159 */
1160 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1161 int i;
1162
1163 for (i = 0 ; i < probe_rsa_count; ++i) {
1164 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1165 port->type = PORT_RSA;
1166 break;
1167 }
1168 }
1169 }
1170 #endif
1171
1172 serial_out(up, UART_LCR, save_lcr);
1173
1174 if (up->capabilities != uart_config[port->type].flags) {
1175 printk(KERN_WARNING
1176 "ttyS%d: detected caps %08x should be %08x\n",
1177 serial_index(port), up->capabilities,
1178 uart_config[port->type].flags);
1179 }
1180
1181 port->fifosize = uart_config[up->port.type].fifo_size;
1182 up->capabilities = uart_config[port->type].flags;
1183 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1184
1185 if (port->type == PORT_UNKNOWN)
1186 goto out;
1187
1188 /*
1189 * Reset the UART.
1190 */
1191 #ifdef CONFIG_SERIAL_8250_RSA
1192 if (port->type == PORT_RSA)
1193 serial_out(up, UART_RSA_FRR, 0);
1194 #endif
1195 serial_out(up, UART_MCR, save_mcr);
1196 serial8250_clear_fifos(up);
1197 serial_in(up, UART_RX);
1198 if (up->capabilities & UART_CAP_UUE)
1199 serial_out(up, UART_IER, UART_IER_UUE);
1200 else
1201 serial_out(up, UART_IER, 0);
1202
1203 out:
1204 spin_unlock_irqrestore(&port->lock, flags);
1205 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1206 }
1207
autoconfig_irq(struct uart_8250_port * up)1208 static void autoconfig_irq(struct uart_8250_port *up)
1209 {
1210 struct uart_port *port = &up->port;
1211 unsigned char save_mcr, save_ier;
1212 unsigned char save_ICP = 0;
1213 unsigned int ICP = 0;
1214 unsigned long irqs;
1215 int irq;
1216
1217 if (port->flags & UPF_FOURPORT) {
1218 ICP = (port->iobase & 0xfe0) | 0x1f;
1219 save_ICP = inb_p(ICP);
1220 outb_p(0x80, ICP);
1221 inb_p(ICP);
1222 }
1223
1224 /* forget possible initially masked and pending IRQ */
1225 probe_irq_off(probe_irq_on());
1226 save_mcr = serial_in(up, UART_MCR);
1227 save_ier = serial_in(up, UART_IER);
1228 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1229
1230 irqs = probe_irq_on();
1231 serial_out(up, UART_MCR, 0);
1232 udelay(10);
1233 if (port->flags & UPF_FOURPORT) {
1234 serial_out(up, UART_MCR,
1235 UART_MCR_DTR | UART_MCR_RTS);
1236 } else {
1237 serial_out(up, UART_MCR,
1238 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1239 }
1240 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1241 serial_in(up, UART_LSR);
1242 serial_in(up, UART_RX);
1243 serial_in(up, UART_IIR);
1244 serial_in(up, UART_MSR);
1245 serial_out(up, UART_TX, 0xFF);
1246 udelay(20);
1247 irq = probe_irq_off(irqs);
1248
1249 serial_out(up, UART_MCR, save_mcr);
1250 serial_out(up, UART_IER, save_ier);
1251
1252 if (port->flags & UPF_FOURPORT)
1253 outb_p(save_ICP, ICP);
1254
1255 port->irq = (irq > 0) ? irq : 0;
1256 }
1257
__stop_tx(struct uart_8250_port * p)1258 static inline void __stop_tx(struct uart_8250_port *p)
1259 {
1260 if (p->ier & UART_IER_THRI) {
1261 p->ier &= ~UART_IER_THRI;
1262 serial_out(p, UART_IER, p->ier);
1263 }
1264 }
1265
serial8250_stop_tx(struct uart_port * port)1266 static void serial8250_stop_tx(struct uart_port *port)
1267 {
1268 struct uart_8250_port *up =
1269 container_of(port, struct uart_8250_port, port);
1270
1271 __stop_tx(up);
1272
1273 /*
1274 * We really want to stop the transmitter from sending.
1275 */
1276 if (port->type == PORT_16C950) {
1277 up->acr |= UART_ACR_TXDIS;
1278 serial_icr_write(up, UART_ACR, up->acr);
1279 }
1280 }
1281
serial8250_start_tx(struct uart_port * port)1282 static void serial8250_start_tx(struct uart_port *port)
1283 {
1284 struct uart_8250_port *up =
1285 container_of(port, struct uart_8250_port, port);
1286
1287 if (!(up->ier & UART_IER_THRI)) {
1288 up->ier |= UART_IER_THRI;
1289 serial_port_out(port, UART_IER, up->ier);
1290
1291 if (up->bugs & UART_BUG_TXEN) {
1292 unsigned char lsr;
1293 lsr = serial_in(up, UART_LSR);
1294 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1295 if ((port->type == PORT_RM9000) ?
1296 (lsr & UART_LSR_THRE) :
1297 (lsr & UART_LSR_TEMT))
1298 serial8250_tx_chars(up);
1299 }
1300 }
1301
1302 /*
1303 * Re-enable the transmitter if we disabled it.
1304 */
1305 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1306 up->acr &= ~UART_ACR_TXDIS;
1307 serial_icr_write(up, UART_ACR, up->acr);
1308 }
1309 }
1310
serial8250_stop_rx(struct uart_port * port)1311 static void serial8250_stop_rx(struct uart_port *port)
1312 {
1313 struct uart_8250_port *up =
1314 container_of(port, struct uart_8250_port, port);
1315
1316 up->ier &= ~UART_IER_RLSI;
1317 up->port.read_status_mask &= ~UART_LSR_DR;
1318 serial_port_out(port, UART_IER, up->ier);
1319 }
1320
serial8250_enable_ms(struct uart_port * port)1321 static void serial8250_enable_ms(struct uart_port *port)
1322 {
1323 struct uart_8250_port *up =
1324 container_of(port, struct uart_8250_port, port);
1325
1326 /* no MSR capabilities */
1327 if (up->bugs & UART_BUG_NOMSR)
1328 return;
1329
1330 up->ier |= UART_IER_MSI;
1331 serial_port_out(port, UART_IER, up->ier);
1332 }
1333
1334 /*
1335 * Clear the Tegra rx fifo after a break
1336 *
1337 * FIXME: This needs to become a port specific callback once we have a
1338 * framework for this
1339 */
clear_rx_fifo(struct uart_8250_port * up)1340 static void clear_rx_fifo(struct uart_8250_port *up)
1341 {
1342 unsigned int status, tmout = 10000;
1343 do {
1344 status = serial_in(up, UART_LSR);
1345 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1346 status = serial_in(up, UART_RX);
1347 else
1348 break;
1349 if (--tmout == 0)
1350 break;
1351 udelay(1);
1352 } while (1);
1353 }
1354
1355 /*
1356 * serial8250_rx_chars: processes according to the passed in LSR
1357 * value, and returns the remaining LSR bits not handled
1358 * by this Rx routine.
1359 */
1360 unsigned char
serial8250_rx_chars(struct uart_8250_port * up,unsigned char lsr)1361 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1362 {
1363 struct uart_port *port = &up->port;
1364 struct tty_struct *tty = port->state->port.tty;
1365 unsigned char ch;
1366 int max_count = 256;
1367 char flag;
1368
1369 do {
1370 if (likely(lsr & UART_LSR_DR))
1371 ch = serial_in(up, UART_RX);
1372 else
1373 /*
1374 * Intel 82571 has a Serial Over Lan device that will
1375 * set UART_LSR_BI without setting UART_LSR_DR when
1376 * it receives a break. To avoid reading from the
1377 * receive buffer without UART_LSR_DR bit set, we
1378 * just force the read character to be 0
1379 */
1380 ch = 0;
1381
1382 flag = TTY_NORMAL;
1383 port->icount.rx++;
1384
1385 lsr |= up->lsr_saved_flags;
1386 up->lsr_saved_flags = 0;
1387
1388 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1389 /*
1390 * For statistics only
1391 */
1392 if (lsr & UART_LSR_BI) {
1393 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1394 port->icount.brk++;
1395 /*
1396 * If tegra port then clear the rx fifo to
1397 * accept another break/character.
1398 */
1399 if (port->type == PORT_TEGRA)
1400 clear_rx_fifo(up);
1401
1402 /*
1403 * We do the SysRQ and SAK checking
1404 * here because otherwise the break
1405 * may get masked by ignore_status_mask
1406 * or read_status_mask.
1407 */
1408 if (uart_handle_break(port))
1409 goto ignore_char;
1410 } else if (lsr & UART_LSR_PE)
1411 port->icount.parity++;
1412 else if (lsr & UART_LSR_FE)
1413 port->icount.frame++;
1414 if (lsr & UART_LSR_OE)
1415 port->icount.overrun++;
1416
1417 /*
1418 * Mask off conditions which should be ignored.
1419 */
1420 lsr &= port->read_status_mask;
1421
1422 if (lsr & UART_LSR_BI) {
1423 DEBUG_INTR("handling break....");
1424 flag = TTY_BREAK;
1425 } else if (lsr & UART_LSR_PE)
1426 flag = TTY_PARITY;
1427 else if (lsr & UART_LSR_FE)
1428 flag = TTY_FRAME;
1429 }
1430 if (uart_handle_sysrq_char(port, ch))
1431 goto ignore_char;
1432
1433 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1434
1435 ignore_char:
1436 lsr = serial_in(up, UART_LSR);
1437 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1438 spin_unlock(&port->lock);
1439 tty_flip_buffer_push(tty);
1440 spin_lock(&port->lock);
1441 return lsr;
1442 }
1443 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1444
serial8250_tx_chars(struct uart_8250_port * up)1445 void serial8250_tx_chars(struct uart_8250_port *up)
1446 {
1447 struct uart_port *port = &up->port;
1448 struct circ_buf *xmit = &port->state->xmit;
1449 int count;
1450
1451 if (port->x_char) {
1452 serial_out(up, UART_TX, port->x_char);
1453 port->icount.tx++;
1454 port->x_char = 0;
1455 return;
1456 }
1457 if (uart_tx_stopped(port)) {
1458 serial8250_stop_tx(port);
1459 return;
1460 }
1461 if (uart_circ_empty(xmit)) {
1462 __stop_tx(up);
1463 return;
1464 }
1465
1466 count = up->tx_loadsz;
1467 do {
1468 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1469 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1470 port->icount.tx++;
1471 if (uart_circ_empty(xmit))
1472 break;
1473 } while (--count > 0);
1474
1475 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1476 uart_write_wakeup(port);
1477
1478 DEBUG_INTR("THRE...");
1479
1480 if (uart_circ_empty(xmit))
1481 __stop_tx(up);
1482 }
1483 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1484
serial8250_modem_status(struct uart_8250_port * up)1485 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1486 {
1487 struct uart_port *port = &up->port;
1488 unsigned int status = serial_in(up, UART_MSR);
1489
1490 status |= up->msr_saved_flags;
1491 up->msr_saved_flags = 0;
1492 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1493 port->state != NULL) {
1494 if (status & UART_MSR_TERI)
1495 port->icount.rng++;
1496 if (status & UART_MSR_DDSR)
1497 port->icount.dsr++;
1498 if (status & UART_MSR_DDCD)
1499 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1500 if (status & UART_MSR_DCTS)
1501 uart_handle_cts_change(port, status & UART_MSR_CTS);
1502
1503 wake_up_interruptible(&port->state->port.delta_msr_wait);
1504 }
1505
1506 return status;
1507 }
1508 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1509
1510 /*
1511 * This handles the interrupt from one port.
1512 */
serial8250_handle_irq(struct uart_port * port,unsigned int iir)1513 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1514 {
1515 unsigned char status;
1516 unsigned long flags;
1517 struct uart_8250_port *up =
1518 container_of(port, struct uart_8250_port, port);
1519
1520 if (iir & UART_IIR_NO_INT)
1521 return 0;
1522
1523 spin_lock_irqsave(&port->lock, flags);
1524
1525 status = serial_port_in(port, UART_LSR);
1526
1527 DEBUG_INTR("status = %x...", status);
1528
1529 if (status & (UART_LSR_DR | UART_LSR_BI))
1530 status = serial8250_rx_chars(up, status);
1531 serial8250_modem_status(up);
1532 if (status & UART_LSR_THRE)
1533 serial8250_tx_chars(up);
1534
1535 spin_unlock_irqrestore(&port->lock, flags);
1536 return 1;
1537 }
1538 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1539
serial8250_default_handle_irq(struct uart_port * port)1540 static int serial8250_default_handle_irq(struct uart_port *port)
1541 {
1542 unsigned int iir = serial_port_in(port, UART_IIR);
1543
1544 return serial8250_handle_irq(port, iir);
1545 }
1546
1547 /*
1548 * This is the serial driver's interrupt routine.
1549 *
1550 * Arjan thinks the old way was overly complex, so it got simplified.
1551 * Alan disagrees, saying that need the complexity to handle the weird
1552 * nature of ISA shared interrupts. (This is a special exception.)
1553 *
1554 * In order to handle ISA shared interrupts properly, we need to check
1555 * that all ports have been serviced, and therefore the ISA interrupt
1556 * line has been de-asserted.
1557 *
1558 * This means we need to loop through all ports. checking that they
1559 * don't have an interrupt pending.
1560 */
serial8250_interrupt(int irq,void * dev_id)1561 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1562 {
1563 struct irq_info *i = dev_id;
1564 struct list_head *l, *end = NULL;
1565 int pass_counter = 0, handled = 0;
1566
1567 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1568
1569 spin_lock(&i->lock);
1570
1571 l = i->head;
1572 do {
1573 struct uart_8250_port *up;
1574 struct uart_port *port;
1575
1576 up = list_entry(l, struct uart_8250_port, list);
1577 port = &up->port;
1578
1579 if (port->handle_irq(port)) {
1580 handled = 1;
1581 end = NULL;
1582 } else if (end == NULL)
1583 end = l;
1584
1585 l = l->next;
1586
1587 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1588 /* If we hit this, we're dead. */
1589 printk_ratelimited(KERN_ERR
1590 "serial8250: too much work for irq%d\n", irq);
1591 break;
1592 }
1593 } while (l != end);
1594
1595 spin_unlock(&i->lock);
1596
1597 DEBUG_INTR("end.\n");
1598
1599 return IRQ_RETVAL(handled);
1600 }
1601
1602 /*
1603 * To support ISA shared interrupts, we need to have one interrupt
1604 * handler that ensures that the IRQ line has been deasserted
1605 * before returning. Failing to do this will result in the IRQ
1606 * line being stuck active, and, since ISA irqs are edge triggered,
1607 * no more IRQs will be seen.
1608 */
serial_do_unlink(struct irq_info * i,struct uart_8250_port * up)1609 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1610 {
1611 spin_lock_irq(&i->lock);
1612
1613 if (!list_empty(i->head)) {
1614 if (i->head == &up->list)
1615 i->head = i->head->next;
1616 list_del(&up->list);
1617 } else {
1618 BUG_ON(i->head != &up->list);
1619 i->head = NULL;
1620 }
1621 spin_unlock_irq(&i->lock);
1622 /* List empty so throw away the hash node */
1623 if (i->head == NULL) {
1624 hlist_del(&i->node);
1625 kfree(i);
1626 }
1627 }
1628
serial_link_irq_chain(struct uart_8250_port * up)1629 static int serial_link_irq_chain(struct uart_8250_port *up)
1630 {
1631 struct hlist_head *h;
1632 struct hlist_node *n;
1633 struct irq_info *i;
1634 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1635
1636 mutex_lock(&hash_mutex);
1637
1638 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1639
1640 hlist_for_each(n, h) {
1641 i = hlist_entry(n, struct irq_info, node);
1642 if (i->irq == up->port.irq)
1643 break;
1644 }
1645
1646 if (n == NULL) {
1647 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1648 if (i == NULL) {
1649 mutex_unlock(&hash_mutex);
1650 return -ENOMEM;
1651 }
1652 spin_lock_init(&i->lock);
1653 i->irq = up->port.irq;
1654 hlist_add_head(&i->node, h);
1655 }
1656 mutex_unlock(&hash_mutex);
1657
1658 spin_lock_irq(&i->lock);
1659
1660 if (i->head) {
1661 list_add(&up->list, i->head);
1662 spin_unlock_irq(&i->lock);
1663
1664 ret = 0;
1665 } else {
1666 INIT_LIST_HEAD(&up->list);
1667 i->head = &up->list;
1668 spin_unlock_irq(&i->lock);
1669 irq_flags |= up->port.irqflags;
1670 ret = request_irq(up->port.irq, serial8250_interrupt,
1671 irq_flags, "serial", i);
1672 if (ret < 0)
1673 serial_do_unlink(i, up);
1674 }
1675
1676 return ret;
1677 }
1678
serial_unlink_irq_chain(struct uart_8250_port * up)1679 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1680 {
1681 struct irq_info *i;
1682 struct hlist_node *n;
1683 struct hlist_head *h;
1684
1685 mutex_lock(&hash_mutex);
1686
1687 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1688
1689 hlist_for_each(n, h) {
1690 i = hlist_entry(n, struct irq_info, node);
1691 if (i->irq == up->port.irq)
1692 break;
1693 }
1694
1695 BUG_ON(n == NULL);
1696 BUG_ON(i->head == NULL);
1697
1698 if (list_empty(i->head))
1699 free_irq(up->port.irq, i);
1700
1701 serial_do_unlink(i, up);
1702 mutex_unlock(&hash_mutex);
1703 }
1704
1705 /*
1706 * This function is used to handle ports that do not have an
1707 * interrupt. This doesn't work very well for 16450's, but gives
1708 * barely passable results for a 16550A. (Although at the expense
1709 * of much CPU overhead).
1710 */
serial8250_timeout(unsigned long data)1711 static void serial8250_timeout(unsigned long data)
1712 {
1713 struct uart_8250_port *up = (struct uart_8250_port *)data;
1714
1715 up->port.handle_irq(&up->port);
1716 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1717 }
1718
serial8250_backup_timeout(unsigned long data)1719 static void serial8250_backup_timeout(unsigned long data)
1720 {
1721 struct uart_8250_port *up = (struct uart_8250_port *)data;
1722 unsigned int iir, ier = 0, lsr;
1723 unsigned long flags;
1724
1725 spin_lock_irqsave(&up->port.lock, flags);
1726
1727 /*
1728 * Must disable interrupts or else we risk racing with the interrupt
1729 * based handler.
1730 */
1731 if (up->port.irq) {
1732 ier = serial_in(up, UART_IER);
1733 serial_out(up, UART_IER, 0);
1734 }
1735
1736 iir = serial_in(up, UART_IIR);
1737
1738 /*
1739 * This should be a safe test for anyone who doesn't trust the
1740 * IIR bits on their UART, but it's specifically designed for
1741 * the "Diva" UART used on the management processor on many HP
1742 * ia64 and parisc boxes.
1743 */
1744 lsr = serial_in(up, UART_LSR);
1745 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1746 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1747 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1748 (lsr & UART_LSR_THRE)) {
1749 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1750 iir |= UART_IIR_THRI;
1751 }
1752
1753 if (!(iir & UART_IIR_NO_INT))
1754 serial8250_tx_chars(up);
1755
1756 if (up->port.irq)
1757 serial_out(up, UART_IER, ier);
1758
1759 spin_unlock_irqrestore(&up->port.lock, flags);
1760
1761 /* Standard timer interval plus 0.2s to keep the port running */
1762 mod_timer(&up->timer,
1763 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1764 }
1765
serial8250_tx_empty(struct uart_port * port)1766 static unsigned int serial8250_tx_empty(struct uart_port *port)
1767 {
1768 struct uart_8250_port *up =
1769 container_of(port, struct uart_8250_port, port);
1770 unsigned long flags;
1771 unsigned int lsr;
1772
1773 spin_lock_irqsave(&port->lock, flags);
1774 lsr = serial_port_in(port, UART_LSR);
1775 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1776 spin_unlock_irqrestore(&port->lock, flags);
1777
1778 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1779 }
1780
serial8250_get_mctrl(struct uart_port * port)1781 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1782 {
1783 struct uart_8250_port *up =
1784 container_of(port, struct uart_8250_port, port);
1785 unsigned int status;
1786 unsigned int ret;
1787
1788 status = serial8250_modem_status(up);
1789
1790 ret = 0;
1791 if (status & UART_MSR_DCD)
1792 ret |= TIOCM_CAR;
1793 if (status & UART_MSR_RI)
1794 ret |= TIOCM_RNG;
1795 if (status & UART_MSR_DSR)
1796 ret |= TIOCM_DSR;
1797 if (status & UART_MSR_CTS)
1798 ret |= TIOCM_CTS;
1799 return ret;
1800 }
1801
serial8250_set_mctrl(struct uart_port * port,unsigned int mctrl)1802 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1803 {
1804 struct uart_8250_port *up =
1805 container_of(port, struct uart_8250_port, port);
1806 unsigned char mcr = 0;
1807
1808 if (mctrl & TIOCM_RTS)
1809 mcr |= UART_MCR_RTS;
1810 if (mctrl & TIOCM_DTR)
1811 mcr |= UART_MCR_DTR;
1812 if (mctrl & TIOCM_OUT1)
1813 mcr |= UART_MCR_OUT1;
1814 if (mctrl & TIOCM_OUT2)
1815 mcr |= UART_MCR_OUT2;
1816 if (mctrl & TIOCM_LOOP)
1817 mcr |= UART_MCR_LOOP;
1818
1819 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1820
1821 serial_port_out(port, UART_MCR, mcr);
1822 }
1823
serial8250_break_ctl(struct uart_port * port,int break_state)1824 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1825 {
1826 struct uart_8250_port *up =
1827 container_of(port, struct uart_8250_port, port);
1828 unsigned long flags;
1829
1830 spin_lock_irqsave(&port->lock, flags);
1831 if (break_state == -1)
1832 up->lcr |= UART_LCR_SBC;
1833 else
1834 up->lcr &= ~UART_LCR_SBC;
1835 serial_port_out(port, UART_LCR, up->lcr);
1836 spin_unlock_irqrestore(&port->lock, flags);
1837 }
1838
1839 /*
1840 * Wait for transmitter & holding register to empty
1841 */
wait_for_xmitr(struct uart_8250_port * up,int bits)1842 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1843 {
1844 unsigned int status, tmout = 10000;
1845
1846 /* Wait up to 10ms for the character(s) to be sent. */
1847 for (;;) {
1848 status = serial_in(up, UART_LSR);
1849
1850 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1851
1852 if ((status & bits) == bits)
1853 break;
1854 if (--tmout == 0)
1855 break;
1856 udelay(1);
1857 }
1858
1859 /* Wait up to 1s for flow control if necessary */
1860 if (up->port.flags & UPF_CONS_FLOW) {
1861 unsigned int tmout;
1862 for (tmout = 1000000; tmout; tmout--) {
1863 unsigned int msr = serial_in(up, UART_MSR);
1864 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1865 if (msr & UART_MSR_CTS)
1866 break;
1867 udelay(1);
1868 touch_nmi_watchdog();
1869 }
1870 }
1871 }
1872
1873 #ifdef CONFIG_CONSOLE_POLL
1874 /*
1875 * Console polling routines for writing and reading from the uart while
1876 * in an interrupt or debug context.
1877 */
1878
serial8250_get_poll_char(struct uart_port * port)1879 static int serial8250_get_poll_char(struct uart_port *port)
1880 {
1881 unsigned char lsr = serial_port_in(port, UART_LSR);
1882
1883 if (!(lsr & UART_LSR_DR))
1884 return NO_POLL_CHAR;
1885
1886 return serial_port_in(port, UART_RX);
1887 }
1888
1889
serial8250_put_poll_char(struct uart_port * port,unsigned char c)1890 static void serial8250_put_poll_char(struct uart_port *port,
1891 unsigned char c)
1892 {
1893 unsigned int ier;
1894 struct uart_8250_port *up =
1895 container_of(port, struct uart_8250_port, port);
1896
1897 /*
1898 * First save the IER then disable the interrupts
1899 */
1900 ier = serial_port_in(port, UART_IER);
1901 if (up->capabilities & UART_CAP_UUE)
1902 serial_port_out(port, UART_IER, UART_IER_UUE);
1903 else
1904 serial_port_out(port, UART_IER, 0);
1905
1906 wait_for_xmitr(up, BOTH_EMPTY);
1907 /*
1908 * Send the character out.
1909 * If a LF, also do CR...
1910 */
1911 serial_port_out(port, UART_TX, c);
1912 if (c == 10) {
1913 wait_for_xmitr(up, BOTH_EMPTY);
1914 serial_port_out(port, UART_TX, 13);
1915 }
1916
1917 /*
1918 * Finally, wait for transmitter to become empty
1919 * and restore the IER
1920 */
1921 wait_for_xmitr(up, BOTH_EMPTY);
1922 serial_port_out(port, UART_IER, ier);
1923 }
1924
1925 #endif /* CONFIG_CONSOLE_POLL */
1926
serial8250_startup(struct uart_port * port)1927 static int serial8250_startup(struct uart_port *port)
1928 {
1929 struct uart_8250_port *up =
1930 container_of(port, struct uart_8250_port, port);
1931 unsigned long flags;
1932 unsigned char lsr, iir;
1933 int retval;
1934
1935 port->fifosize = uart_config[up->port.type].fifo_size;
1936 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1937 up->capabilities = uart_config[up->port.type].flags;
1938 up->mcr = 0;
1939
1940 if (port->iotype != up->cur_iotype)
1941 set_io_from_upio(port);
1942
1943 if (port->type == PORT_16C950) {
1944 /* Wake up and initialize UART */
1945 up->acr = 0;
1946 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1947 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1948 serial_port_out(port, UART_IER, 0);
1949 serial_port_out(port, UART_LCR, 0);
1950 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1951 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1952 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1953 serial_port_out(port, UART_LCR, 0);
1954 }
1955
1956 #ifdef CONFIG_SERIAL_8250_RSA
1957 /*
1958 * If this is an RSA port, see if we can kick it up to the
1959 * higher speed clock.
1960 */
1961 enable_rsa(up);
1962 #endif
1963
1964 /*
1965 * Clear the FIFO buffers and disable them.
1966 * (they will be reenabled in set_termios())
1967 */
1968 serial8250_clear_fifos(up);
1969
1970 /*
1971 * Clear the interrupt registers.
1972 */
1973 serial_port_in(port, UART_LSR);
1974 serial_port_in(port, UART_RX);
1975 serial_port_in(port, UART_IIR);
1976 serial_port_in(port, UART_MSR);
1977
1978 /*
1979 * At this point, there's no way the LSR could still be 0xff;
1980 * if it is, then bail out, because there's likely no UART
1981 * here.
1982 */
1983 if (!(port->flags & UPF_BUGGY_UART) &&
1984 (serial_port_in(port, UART_LSR) == 0xff)) {
1985 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1986 serial_index(port));
1987 return -ENODEV;
1988 }
1989
1990 /*
1991 * For a XR16C850, we need to set the trigger levels
1992 */
1993 if (port->type == PORT_16850) {
1994 unsigned char fctr;
1995
1996 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1997
1998 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1999 serial_port_out(port, UART_FCTR,
2000 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2001 serial_port_out(port, UART_TRG, UART_TRG_96);
2002 serial_port_out(port, UART_FCTR,
2003 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2004 serial_port_out(port, UART_TRG, UART_TRG_96);
2005
2006 serial_port_out(port, UART_LCR, 0);
2007 }
2008
2009 if (port->irq) {
2010 unsigned char iir1;
2011 /*
2012 * Test for UARTs that do not reassert THRE when the
2013 * transmitter is idle and the interrupt has already
2014 * been cleared. Real 16550s should always reassert
2015 * this interrupt whenever the transmitter is idle and
2016 * the interrupt is enabled. Delays are necessary to
2017 * allow register changes to become visible.
2018 */
2019 spin_lock_irqsave(&port->lock, flags);
2020 if (up->port.irqflags & IRQF_SHARED)
2021 disable_irq_nosync(port->irq);
2022
2023 wait_for_xmitr(up, UART_LSR_THRE);
2024 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2025 udelay(1); /* allow THRE to set */
2026 iir1 = serial_port_in(port, UART_IIR);
2027 serial_port_out(port, UART_IER, 0);
2028 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2029 udelay(1); /* allow a working UART time to re-assert THRE */
2030 iir = serial_port_in(port, UART_IIR);
2031 serial_port_out(port, UART_IER, 0);
2032
2033 if (port->irqflags & IRQF_SHARED)
2034 enable_irq(port->irq);
2035 spin_unlock_irqrestore(&port->lock, flags);
2036
2037 /*
2038 * If the interrupt is not reasserted, or we otherwise
2039 * don't trust the iir, setup a timer to kick the UART
2040 * on a regular basis.
2041 */
2042 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2043 up->port.flags & UPF_BUG_THRE) {
2044 up->bugs |= UART_BUG_THRE;
2045 pr_debug("ttyS%d - using backup timer\n",
2046 serial_index(port));
2047 }
2048 }
2049
2050 /*
2051 * The above check will only give an accurate result the first time
2052 * the port is opened so this value needs to be preserved.
2053 */
2054 if (up->bugs & UART_BUG_THRE) {
2055 up->timer.function = serial8250_backup_timeout;
2056 up->timer.data = (unsigned long)up;
2057 mod_timer(&up->timer, jiffies +
2058 uart_poll_timeout(port) + HZ / 5);
2059 }
2060
2061 /*
2062 * If the "interrupt" for this port doesn't correspond with any
2063 * hardware interrupt, we use a timer-based system. The original
2064 * driver used to do this with IRQ0.
2065 */
2066 if (!port->irq) {
2067 up->timer.data = (unsigned long)up;
2068 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2069 } else {
2070 retval = serial_link_irq_chain(up);
2071 if (retval)
2072 return retval;
2073 }
2074
2075 /*
2076 * Now, initialize the UART
2077 */
2078 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2079
2080 spin_lock_irqsave(&port->lock, flags);
2081 if (up->port.flags & UPF_FOURPORT) {
2082 if (!up->port.irq)
2083 up->port.mctrl |= TIOCM_OUT1;
2084 } else
2085 /*
2086 * Most PC uarts need OUT2 raised to enable interrupts.
2087 */
2088 if (port->irq)
2089 up->port.mctrl |= TIOCM_OUT2;
2090
2091 serial8250_set_mctrl(port, port->mctrl);
2092
2093 /* Serial over Lan (SoL) hack:
2094 Intel 8257x Gigabit ethernet chips have a
2095 16550 emulation, to be used for Serial Over Lan.
2096 Those chips take a longer time than a normal
2097 serial device to signalize that a transmission
2098 data was queued. Due to that, the above test generally
2099 fails. One solution would be to delay the reading of
2100 iir. However, this is not reliable, since the timeout
2101 is variable. So, let's just don't test if we receive
2102 TX irq. This way, we'll never enable UART_BUG_TXEN.
2103 */
2104 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2105 goto dont_test_tx_en;
2106
2107 /*
2108 * Do a quick test to see if we receive an
2109 * interrupt when we enable the TX irq.
2110 */
2111 serial_port_out(port, UART_IER, UART_IER_THRI);
2112 lsr = serial_port_in(port, UART_LSR);
2113 iir = serial_port_in(port, UART_IIR);
2114 serial_port_out(port, UART_IER, 0);
2115
2116 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2117 if (!(up->bugs & UART_BUG_TXEN)) {
2118 up->bugs |= UART_BUG_TXEN;
2119 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2120 serial_index(port));
2121 }
2122 } else {
2123 up->bugs &= ~UART_BUG_TXEN;
2124 }
2125
2126 dont_test_tx_en:
2127 spin_unlock_irqrestore(&port->lock, flags);
2128
2129 /*
2130 * Clear the interrupt registers again for luck, and clear the
2131 * saved flags to avoid getting false values from polling
2132 * routines or the previous session.
2133 */
2134 serial_port_in(port, UART_LSR);
2135 serial_port_in(port, UART_RX);
2136 serial_port_in(port, UART_IIR);
2137 serial_port_in(port, UART_MSR);
2138 up->lsr_saved_flags = 0;
2139 up->msr_saved_flags = 0;
2140
2141 /*
2142 * Finally, enable interrupts. Note: Modem status interrupts
2143 * are set via set_termios(), which will be occurring imminently
2144 * anyway, so we don't enable them here.
2145 */
2146 up->ier = UART_IER_RLSI | UART_IER_RDI;
2147 serial_port_out(port, UART_IER, up->ier);
2148
2149 if (port->flags & UPF_FOURPORT) {
2150 unsigned int icp;
2151 /*
2152 * Enable interrupts on the AST Fourport board
2153 */
2154 icp = (port->iobase & 0xfe0) | 0x01f;
2155 outb_p(0x80, icp);
2156 inb_p(icp);
2157 }
2158
2159 return 0;
2160 }
2161
serial8250_shutdown(struct uart_port * port)2162 static void serial8250_shutdown(struct uart_port *port)
2163 {
2164 struct uart_8250_port *up =
2165 container_of(port, struct uart_8250_port, port);
2166 unsigned long flags;
2167
2168 /*
2169 * Disable interrupts from this port
2170 */
2171 up->ier = 0;
2172 serial_port_out(port, UART_IER, 0);
2173
2174 spin_lock_irqsave(&port->lock, flags);
2175 if (port->flags & UPF_FOURPORT) {
2176 /* reset interrupts on the AST Fourport board */
2177 inb((port->iobase & 0xfe0) | 0x1f);
2178 port->mctrl |= TIOCM_OUT1;
2179 } else
2180 port->mctrl &= ~TIOCM_OUT2;
2181
2182 serial8250_set_mctrl(port, port->mctrl);
2183 spin_unlock_irqrestore(&port->lock, flags);
2184
2185 /*
2186 * Disable break condition and FIFOs
2187 */
2188 serial_port_out(port, UART_LCR,
2189 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2190 serial8250_clear_fifos(up);
2191
2192 #ifdef CONFIG_SERIAL_8250_RSA
2193 /*
2194 * Reset the RSA board back to 115kbps compat mode.
2195 */
2196 disable_rsa(up);
2197 #endif
2198
2199 /*
2200 * Read data port to reset things, and then unlink from
2201 * the IRQ chain.
2202 */
2203 serial_port_in(port, UART_RX);
2204
2205 del_timer_sync(&up->timer);
2206 up->timer.function = serial8250_timeout;
2207 if (port->irq)
2208 serial_unlink_irq_chain(up);
2209 }
2210
serial8250_get_divisor(struct uart_port * port,unsigned int baud)2211 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2212 {
2213 unsigned int quot;
2214
2215 /*
2216 * Handle magic divisors for baud rates above baud_base on
2217 * SMSC SuperIO chips.
2218 */
2219 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2220 baud == (port->uartclk/4))
2221 quot = 0x8001;
2222 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2223 baud == (port->uartclk/8))
2224 quot = 0x8002;
2225 else
2226 quot = uart_get_divisor(port, baud);
2227
2228 return quot;
2229 }
2230
2231 void
serial8250_do_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)2232 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2233 struct ktermios *old)
2234 {
2235 struct uart_8250_port *up =
2236 container_of(port, struct uart_8250_port, port);
2237 unsigned char cval, fcr = 0;
2238 unsigned long flags;
2239 unsigned int baud, quot;
2240
2241 switch (termios->c_cflag & CSIZE) {
2242 case CS5:
2243 cval = UART_LCR_WLEN5;
2244 break;
2245 case CS6:
2246 cval = UART_LCR_WLEN6;
2247 break;
2248 case CS7:
2249 cval = UART_LCR_WLEN7;
2250 break;
2251 default:
2252 case CS8:
2253 cval = UART_LCR_WLEN8;
2254 break;
2255 }
2256
2257 if (termios->c_cflag & CSTOPB)
2258 cval |= UART_LCR_STOP;
2259 if (termios->c_cflag & PARENB)
2260 cval |= UART_LCR_PARITY;
2261 if (!(termios->c_cflag & PARODD))
2262 cval |= UART_LCR_EPAR;
2263 #ifdef CMSPAR
2264 if (termios->c_cflag & CMSPAR)
2265 cval |= UART_LCR_SPAR;
2266 #endif
2267
2268 /*
2269 * Ask the core to calculate the divisor for us.
2270 */
2271 baud = uart_get_baud_rate(port, termios, old,
2272 port->uartclk / 16 / 0xffff,
2273 port->uartclk / 16);
2274 quot = serial8250_get_divisor(port, baud);
2275
2276 /*
2277 * Oxford Semi 952 rev B workaround
2278 */
2279 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2280 quot++;
2281
2282 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2283 fcr = uart_config[port->type].fcr;
2284 if (baud < 2400) {
2285 fcr &= ~UART_FCR_TRIGGER_MASK;
2286 fcr |= UART_FCR_TRIGGER_1;
2287 }
2288 }
2289
2290 /*
2291 * MCR-based auto flow control. When AFE is enabled, RTS will be
2292 * deasserted when the receive FIFO contains more characters than
2293 * the trigger, or the MCR RTS bit is cleared. In the case where
2294 * the remote UART is not using CTS auto flow control, we must
2295 * have sufficient FIFO entries for the latency of the remote
2296 * UART to respond. IOW, at least 32 bytes of FIFO.
2297 */
2298 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2299 up->mcr &= ~UART_MCR_AFE;
2300 if (termios->c_cflag & CRTSCTS)
2301 up->mcr |= UART_MCR_AFE;
2302 }
2303
2304 /*
2305 * Ok, we're now changing the port state. Do it with
2306 * interrupts disabled.
2307 */
2308 spin_lock_irqsave(&port->lock, flags);
2309
2310 /*
2311 * Update the per-port timeout.
2312 */
2313 uart_update_timeout(port, termios->c_cflag, baud);
2314
2315 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2316 if (termios->c_iflag & INPCK)
2317 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2318 if (termios->c_iflag & (BRKINT | PARMRK))
2319 port->read_status_mask |= UART_LSR_BI;
2320
2321 /*
2322 * Characteres to ignore
2323 */
2324 port->ignore_status_mask = 0;
2325 if (termios->c_iflag & IGNPAR)
2326 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2327 if (termios->c_iflag & IGNBRK) {
2328 port->ignore_status_mask |= UART_LSR_BI;
2329 /*
2330 * If we're ignoring parity and break indicators,
2331 * ignore overruns too (for real raw support).
2332 */
2333 if (termios->c_iflag & IGNPAR)
2334 port->ignore_status_mask |= UART_LSR_OE;
2335 }
2336
2337 /*
2338 * ignore all characters if CREAD is not set
2339 */
2340 if ((termios->c_cflag & CREAD) == 0)
2341 port->ignore_status_mask |= UART_LSR_DR;
2342
2343 /*
2344 * CTS flow control flag and modem status interrupts
2345 */
2346 up->ier &= ~UART_IER_MSI;
2347 if (!(up->bugs & UART_BUG_NOMSR) &&
2348 UART_ENABLE_MS(&up->port, termios->c_cflag))
2349 up->ier |= UART_IER_MSI;
2350 if (up->capabilities & UART_CAP_UUE)
2351 up->ier |= UART_IER_UUE;
2352 if (up->capabilities & UART_CAP_RTOIE)
2353 up->ier |= UART_IER_RTOIE;
2354
2355 serial_port_out(port, UART_IER, up->ier);
2356
2357 if (up->capabilities & UART_CAP_EFR) {
2358 unsigned char efr = 0;
2359 /*
2360 * TI16C752/Startech hardware flow control. FIXME:
2361 * - TI16C752 requires control thresholds to be set.
2362 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2363 */
2364 if (termios->c_cflag & CRTSCTS)
2365 efr |= UART_EFR_CTS;
2366
2367 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2368 if (port->flags & UPF_EXAR_EFR)
2369 serial_port_out(port, UART_XR_EFR, efr);
2370 else
2371 serial_port_out(port, UART_EFR, efr);
2372 }
2373
2374 #ifdef CONFIG_ARCH_OMAP
2375 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2376 if (cpu_is_omap1510() && is_omap_port(up)) {
2377 if (baud == 115200) {
2378 quot = 1;
2379 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2380 } else
2381 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2382 }
2383 #endif
2384
2385 /*
2386 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2387 * otherwise just set DLAB
2388 */
2389 if (up->capabilities & UART_NATSEMI)
2390 serial_port_out(port, UART_LCR, 0xe0);
2391 else
2392 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2393
2394 serial_dl_write(up, quot);
2395
2396 /*
2397 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2398 * is written without DLAB set, this mode will be disabled.
2399 */
2400 if (port->type == PORT_16750)
2401 serial_port_out(port, UART_FCR, fcr);
2402
2403 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2404 up->lcr = cval; /* Save LCR */
2405 if (port->type != PORT_16750) {
2406 /* emulated UARTs (Lucent Venus 167x) need two steps */
2407 if (fcr & UART_FCR_ENABLE_FIFO)
2408 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2409 serial_port_out(port, UART_FCR, fcr); /* set fcr */
2410 }
2411 serial8250_set_mctrl(port, port->mctrl);
2412 spin_unlock_irqrestore(&port->lock, flags);
2413 /* Don't rewrite B0 */
2414 if (tty_termios_baud_rate(termios))
2415 tty_termios_encode_baud_rate(termios, baud, baud);
2416 }
2417 EXPORT_SYMBOL(serial8250_do_set_termios);
2418
2419 static void
serial8250_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)2420 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2421 struct ktermios *old)
2422 {
2423 if (port->set_termios)
2424 port->set_termios(port, termios, old);
2425 else
2426 serial8250_do_set_termios(port, termios, old);
2427 }
2428
2429 static void
serial8250_set_ldisc(struct uart_port * port,int new)2430 serial8250_set_ldisc(struct uart_port *port, int new)
2431 {
2432 if (new == N_PPS) {
2433 port->flags |= UPF_HARDPPS_CD;
2434 serial8250_enable_ms(port);
2435 } else
2436 port->flags &= ~UPF_HARDPPS_CD;
2437 }
2438
2439
serial8250_do_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2440 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2441 unsigned int oldstate)
2442 {
2443 struct uart_8250_port *p =
2444 container_of(port, struct uart_8250_port, port);
2445
2446 serial8250_set_sleep(p, state != 0);
2447 }
2448 EXPORT_SYMBOL(serial8250_do_pm);
2449
2450 static void
serial8250_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2451 serial8250_pm(struct uart_port *port, unsigned int state,
2452 unsigned int oldstate)
2453 {
2454 if (port->pm)
2455 port->pm(port, state, oldstate);
2456 else
2457 serial8250_do_pm(port, state, oldstate);
2458 }
2459
serial8250_port_size(struct uart_8250_port * pt)2460 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2461 {
2462 if (pt->port.iotype == UPIO_AU)
2463 return 0x1000;
2464 #ifdef CONFIG_ARCH_OMAP
2465 if (is_omap_port(pt))
2466 return 0x16 << pt->port.regshift;
2467 #endif
2468 return 8 << pt->port.regshift;
2469 }
2470
2471 /*
2472 * Resource handling.
2473 */
serial8250_request_std_resource(struct uart_8250_port * up)2474 static int serial8250_request_std_resource(struct uart_8250_port *up)
2475 {
2476 unsigned int size = serial8250_port_size(up);
2477 struct uart_port *port = &up->port;
2478 int ret = 0;
2479
2480 switch (port->iotype) {
2481 case UPIO_AU:
2482 case UPIO_TSI:
2483 case UPIO_MEM32:
2484 case UPIO_MEM:
2485 if (!port->mapbase)
2486 break;
2487
2488 if (!request_mem_region(port->mapbase, size, "serial")) {
2489 ret = -EBUSY;
2490 break;
2491 }
2492
2493 if (port->flags & UPF_IOREMAP) {
2494 port->membase = ioremap_nocache(port->mapbase, size);
2495 if (!port->membase) {
2496 release_mem_region(port->mapbase, size);
2497 ret = -ENOMEM;
2498 }
2499 }
2500 break;
2501
2502 case UPIO_HUB6:
2503 case UPIO_PORT:
2504 if (!request_region(port->iobase, size, "serial"))
2505 ret = -EBUSY;
2506 break;
2507 }
2508 return ret;
2509 }
2510
serial8250_release_std_resource(struct uart_8250_port * up)2511 static void serial8250_release_std_resource(struct uart_8250_port *up)
2512 {
2513 unsigned int size = serial8250_port_size(up);
2514 struct uart_port *port = &up->port;
2515
2516 switch (port->iotype) {
2517 case UPIO_AU:
2518 case UPIO_TSI:
2519 case UPIO_MEM32:
2520 case UPIO_MEM:
2521 if (!port->mapbase)
2522 break;
2523
2524 if (port->flags & UPF_IOREMAP) {
2525 iounmap(port->membase);
2526 port->membase = NULL;
2527 }
2528
2529 release_mem_region(port->mapbase, size);
2530 break;
2531
2532 case UPIO_HUB6:
2533 case UPIO_PORT:
2534 release_region(port->iobase, size);
2535 break;
2536 }
2537 }
2538
serial8250_request_rsa_resource(struct uart_8250_port * up)2539 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2540 {
2541 unsigned long start = UART_RSA_BASE << up->port.regshift;
2542 unsigned int size = 8 << up->port.regshift;
2543 struct uart_port *port = &up->port;
2544 int ret = -EINVAL;
2545
2546 switch (port->iotype) {
2547 case UPIO_HUB6:
2548 case UPIO_PORT:
2549 start += port->iobase;
2550 if (request_region(start, size, "serial-rsa"))
2551 ret = 0;
2552 else
2553 ret = -EBUSY;
2554 break;
2555 }
2556
2557 return ret;
2558 }
2559
serial8250_release_rsa_resource(struct uart_8250_port * up)2560 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2561 {
2562 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2563 unsigned int size = 8 << up->port.regshift;
2564 struct uart_port *port = &up->port;
2565
2566 switch (port->iotype) {
2567 case UPIO_HUB6:
2568 case UPIO_PORT:
2569 release_region(port->iobase + offset, size);
2570 break;
2571 }
2572 }
2573
serial8250_release_port(struct uart_port * port)2574 static void serial8250_release_port(struct uart_port *port)
2575 {
2576 struct uart_8250_port *up =
2577 container_of(port, struct uart_8250_port, port);
2578
2579 serial8250_release_std_resource(up);
2580 if (port->type == PORT_RSA)
2581 serial8250_release_rsa_resource(up);
2582 }
2583
serial8250_request_port(struct uart_port * port)2584 static int serial8250_request_port(struct uart_port *port)
2585 {
2586 struct uart_8250_port *up =
2587 container_of(port, struct uart_8250_port, port);
2588 int ret = 0;
2589
2590 ret = serial8250_request_std_resource(up);
2591 if (ret == 0 && port->type == PORT_RSA) {
2592 ret = serial8250_request_rsa_resource(up);
2593 if (ret < 0)
2594 serial8250_release_std_resource(up);
2595 }
2596
2597 return ret;
2598 }
2599
serial8250_config_port(struct uart_port * port,int flags)2600 static void serial8250_config_port(struct uart_port *port, int flags)
2601 {
2602 struct uart_8250_port *up =
2603 container_of(port, struct uart_8250_port, port);
2604 int probeflags = PROBE_ANY;
2605 int ret;
2606
2607 /*
2608 * Find the region that we can probe for. This in turn
2609 * tells us whether we can probe for the type of port.
2610 */
2611 ret = serial8250_request_std_resource(up);
2612 if (ret < 0)
2613 return;
2614
2615 ret = serial8250_request_rsa_resource(up);
2616 if (ret < 0)
2617 probeflags &= ~PROBE_RSA;
2618
2619 if (port->iotype != up->cur_iotype)
2620 set_io_from_upio(port);
2621
2622 if (flags & UART_CONFIG_TYPE)
2623 autoconfig(up, probeflags);
2624
2625 /* if access method is AU, it is a 16550 with a quirk */
2626 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2627 up->bugs |= UART_BUG_NOMSR;
2628
2629 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2630 autoconfig_irq(up);
2631
2632 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2633 serial8250_release_rsa_resource(up);
2634 if (port->type == PORT_UNKNOWN)
2635 serial8250_release_std_resource(up);
2636 }
2637
2638 static int
serial8250_verify_port(struct uart_port * port,struct serial_struct * ser)2639 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2640 {
2641 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2642 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2643 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2644 ser->type == PORT_STARTECH)
2645 return -EINVAL;
2646 return 0;
2647 }
2648
2649 static const char *
serial8250_type(struct uart_port * port)2650 serial8250_type(struct uart_port *port)
2651 {
2652 int type = port->type;
2653
2654 if (type >= ARRAY_SIZE(uart_config))
2655 type = 0;
2656 return uart_config[type].name;
2657 }
2658
2659 static struct uart_ops serial8250_pops = {
2660 .tx_empty = serial8250_tx_empty,
2661 .set_mctrl = serial8250_set_mctrl,
2662 .get_mctrl = serial8250_get_mctrl,
2663 .stop_tx = serial8250_stop_tx,
2664 .start_tx = serial8250_start_tx,
2665 .stop_rx = serial8250_stop_rx,
2666 .enable_ms = serial8250_enable_ms,
2667 .break_ctl = serial8250_break_ctl,
2668 .startup = serial8250_startup,
2669 .shutdown = serial8250_shutdown,
2670 .set_termios = serial8250_set_termios,
2671 .set_ldisc = serial8250_set_ldisc,
2672 .pm = serial8250_pm,
2673 .type = serial8250_type,
2674 .release_port = serial8250_release_port,
2675 .request_port = serial8250_request_port,
2676 .config_port = serial8250_config_port,
2677 .verify_port = serial8250_verify_port,
2678 #ifdef CONFIG_CONSOLE_POLL
2679 .poll_get_char = serial8250_get_poll_char,
2680 .poll_put_char = serial8250_put_poll_char,
2681 #endif
2682 };
2683
2684 static struct uart_8250_port serial8250_ports[UART_NR];
2685
2686 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2687 unsigned short *capabilities);
2688
serial8250_set_isa_configurator(void (* v)(int port,struct uart_port * up,unsigned short * capabilities))2689 void serial8250_set_isa_configurator(
2690 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2691 {
2692 serial8250_isa_config = v;
2693 }
2694 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2695
serial8250_isa_init_ports(void)2696 static void __init serial8250_isa_init_ports(void)
2697 {
2698 struct uart_8250_port *up;
2699 static int first = 1;
2700 int i, irqflag = 0;
2701
2702 if (!first)
2703 return;
2704 first = 0;
2705
2706 for (i = 0; i < nr_uarts; i++) {
2707 struct uart_8250_port *up = &serial8250_ports[i];
2708 struct uart_port *port = &up->port;
2709
2710 port->line = i;
2711 spin_lock_init(&port->lock);
2712
2713 init_timer(&up->timer);
2714 up->timer.function = serial8250_timeout;
2715
2716 /*
2717 * ALPHA_KLUDGE_MCR needs to be killed.
2718 */
2719 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2720 up->mcr_force = ALPHA_KLUDGE_MCR;
2721
2722 port->ops = &serial8250_pops;
2723 }
2724
2725 if (share_irqs)
2726 irqflag = IRQF_SHARED;
2727
2728 for (i = 0, up = serial8250_ports;
2729 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2730 i++, up++) {
2731 struct uart_port *port = &up->port;
2732
2733 port->iobase = old_serial_port[i].port;
2734 port->irq = irq_canonicalize(old_serial_port[i].irq);
2735 port->irqflags = old_serial_port[i].irqflags;
2736 port->uartclk = old_serial_port[i].baud_base * 16;
2737 port->flags = old_serial_port[i].flags;
2738 port->hub6 = old_serial_port[i].hub6;
2739 port->membase = old_serial_port[i].iomem_base;
2740 port->iotype = old_serial_port[i].io_type;
2741 port->regshift = old_serial_port[i].iomem_reg_shift;
2742 set_io_from_upio(port);
2743 port->irqflags |= irqflag;
2744 if (serial8250_isa_config != NULL)
2745 serial8250_isa_config(i, &up->port, &up->capabilities);
2746
2747 }
2748 }
2749
2750 static void
serial8250_init_fixed_type_port(struct uart_8250_port * up,unsigned int type)2751 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2752 {
2753 up->port.type = type;
2754 up->port.fifosize = uart_config[type].fifo_size;
2755 up->capabilities = uart_config[type].flags;
2756 up->tx_loadsz = uart_config[type].tx_loadsz;
2757 }
2758
2759 static void __init
serial8250_register_ports(struct uart_driver * drv,struct device * dev)2760 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2761 {
2762 int i;
2763
2764 for (i = 0; i < nr_uarts; i++) {
2765 struct uart_8250_port *up = &serial8250_ports[i];
2766 up->cur_iotype = 0xFF;
2767 }
2768
2769 serial8250_isa_init_ports();
2770
2771 for (i = 0; i < nr_uarts; i++) {
2772 struct uart_8250_port *up = &serial8250_ports[i];
2773
2774 up->port.dev = dev;
2775
2776 if (up->port.flags & UPF_FIXED_TYPE)
2777 serial8250_init_fixed_type_port(up, up->port.type);
2778
2779 uart_add_one_port(drv, &up->port);
2780 }
2781 }
2782
2783 #ifdef CONFIG_SERIAL_8250_CONSOLE
2784
serial8250_console_putchar(struct uart_port * port,int ch)2785 static void serial8250_console_putchar(struct uart_port *port, int ch)
2786 {
2787 struct uart_8250_port *up =
2788 container_of(port, struct uart_8250_port, port);
2789
2790 wait_for_xmitr(up, UART_LSR_THRE);
2791 serial_port_out(port, UART_TX, ch);
2792 }
2793
2794 /*
2795 * Print a string to the serial port trying not to disturb
2796 * any possible real use of the port...
2797 *
2798 * The console_lock must be held when we get here.
2799 */
2800 static void
serial8250_console_write(struct console * co,const char * s,unsigned int count)2801 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2802 {
2803 struct uart_8250_port *up = &serial8250_ports[co->index];
2804 struct uart_port *port = &up->port;
2805 unsigned long flags;
2806 unsigned int ier;
2807 int locked = 1;
2808
2809 touch_nmi_watchdog();
2810
2811 local_irq_save(flags);
2812 if (port->sysrq) {
2813 /* serial8250_handle_irq() already took the lock */
2814 locked = 0;
2815 } else if (oops_in_progress) {
2816 locked = spin_trylock(&port->lock);
2817 } else
2818 spin_lock(&port->lock);
2819
2820 /*
2821 * First save the IER then disable the interrupts
2822 */
2823 ier = serial_port_in(port, UART_IER);
2824
2825 if (up->capabilities & UART_CAP_UUE)
2826 serial_port_out(port, UART_IER, UART_IER_UUE);
2827 else
2828 serial_port_out(port, UART_IER, 0);
2829
2830 uart_console_write(port, s, count, serial8250_console_putchar);
2831
2832 /*
2833 * Finally, wait for transmitter to become empty
2834 * and restore the IER
2835 */
2836 wait_for_xmitr(up, BOTH_EMPTY);
2837 serial_port_out(port, UART_IER, ier);
2838
2839 /*
2840 * The receive handling will happen properly because the
2841 * receive ready bit will still be set; it is not cleared
2842 * on read. However, modem control will not, we must
2843 * call it if we have saved something in the saved flags
2844 * while processing with interrupts off.
2845 */
2846 if (up->msr_saved_flags)
2847 serial8250_modem_status(up);
2848
2849 if (locked)
2850 spin_unlock(&port->lock);
2851 local_irq_restore(flags);
2852 }
2853
serial8250_console_setup(struct console * co,char * options)2854 static int __init serial8250_console_setup(struct console *co, char *options)
2855 {
2856 struct uart_port *port;
2857 int baud = 9600;
2858 int bits = 8;
2859 int parity = 'n';
2860 int flow = 'n';
2861
2862 /*
2863 * Check whether an invalid uart number has been specified, and
2864 * if so, search for the first available port that does have
2865 * console support.
2866 */
2867 if (co->index >= nr_uarts)
2868 co->index = 0;
2869 port = &serial8250_ports[co->index].port;
2870 if (!port->iobase && !port->membase)
2871 return -ENODEV;
2872
2873 if (options)
2874 uart_parse_options(options, &baud, &parity, &bits, &flow);
2875
2876 return uart_set_options(port, co, baud, parity, bits, flow);
2877 }
2878
serial8250_console_early_setup(void)2879 static int serial8250_console_early_setup(void)
2880 {
2881 return serial8250_find_port_for_earlycon();
2882 }
2883
2884 static struct console serial8250_console = {
2885 .name = "ttyS",
2886 .write = serial8250_console_write,
2887 .device = uart_console_device,
2888 .setup = serial8250_console_setup,
2889 .early_setup = serial8250_console_early_setup,
2890 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2891 .index = -1,
2892 .data = &serial8250_reg,
2893 };
2894
serial8250_console_init(void)2895 static int __init serial8250_console_init(void)
2896 {
2897 if (nr_uarts > UART_NR)
2898 nr_uarts = UART_NR;
2899
2900 serial8250_isa_init_ports();
2901 register_console(&serial8250_console);
2902 return 0;
2903 }
2904 console_initcall(serial8250_console_init);
2905
serial8250_find_port(struct uart_port * p)2906 int serial8250_find_port(struct uart_port *p)
2907 {
2908 int line;
2909 struct uart_port *port;
2910
2911 for (line = 0; line < nr_uarts; line++) {
2912 port = &serial8250_ports[line].port;
2913 if (uart_match_port(p, port))
2914 return line;
2915 }
2916 return -ENODEV;
2917 }
2918
2919 #define SERIAL8250_CONSOLE &serial8250_console
2920 #else
2921 #define SERIAL8250_CONSOLE NULL
2922 #endif
2923
2924 static struct uart_driver serial8250_reg = {
2925 .owner = THIS_MODULE,
2926 .driver_name = "serial",
2927 .dev_name = "ttyS",
2928 .major = TTY_MAJOR,
2929 .minor = 64,
2930 .cons = SERIAL8250_CONSOLE,
2931 };
2932
2933 /*
2934 * early_serial_setup - early registration for 8250 ports
2935 *
2936 * Setup an 8250 port structure prior to console initialisation. Use
2937 * after console initialisation will cause undefined behaviour.
2938 */
early_serial_setup(struct uart_port * port)2939 int __init early_serial_setup(struct uart_port *port)
2940 {
2941 struct uart_port *p;
2942
2943 if (port->line >= ARRAY_SIZE(serial8250_ports))
2944 return -ENODEV;
2945
2946 serial8250_isa_init_ports();
2947 p = &serial8250_ports[port->line].port;
2948 p->iobase = port->iobase;
2949 p->membase = port->membase;
2950 p->irq = port->irq;
2951 p->irqflags = port->irqflags;
2952 p->uartclk = port->uartclk;
2953 p->fifosize = port->fifosize;
2954 p->regshift = port->regshift;
2955 p->iotype = port->iotype;
2956 p->flags = port->flags;
2957 p->mapbase = port->mapbase;
2958 p->private_data = port->private_data;
2959 p->type = port->type;
2960 p->line = port->line;
2961
2962 set_io_from_upio(p);
2963 if (port->serial_in)
2964 p->serial_in = port->serial_in;
2965 if (port->serial_out)
2966 p->serial_out = port->serial_out;
2967 if (port->handle_irq)
2968 p->handle_irq = port->handle_irq;
2969 else
2970 p->handle_irq = serial8250_default_handle_irq;
2971
2972 return 0;
2973 }
2974
2975 /**
2976 * serial8250_suspend_port - suspend one serial port
2977 * @line: serial line number
2978 *
2979 * Suspend one serial port.
2980 */
serial8250_suspend_port(int line)2981 void serial8250_suspend_port(int line)
2982 {
2983 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2984 }
2985
2986 /**
2987 * serial8250_resume_port - resume one serial port
2988 * @line: serial line number
2989 *
2990 * Resume one serial port.
2991 */
serial8250_resume_port(int line)2992 void serial8250_resume_port(int line)
2993 {
2994 struct uart_8250_port *up = &serial8250_ports[line];
2995 struct uart_port *port = &up->port;
2996
2997 if (up->capabilities & UART_NATSEMI) {
2998 /* Ensure it's still in high speed mode */
2999 serial_port_out(port, UART_LCR, 0xE0);
3000
3001 ns16550a_goto_highspeed(up);
3002
3003 serial_port_out(port, UART_LCR, 0);
3004 port->uartclk = 921600*16;
3005 }
3006 uart_resume_port(&serial8250_reg, port);
3007 }
3008
3009 /*
3010 * Register a set of serial devices attached to a platform device. The
3011 * list is terminated with a zero flags entry, which means we expect
3012 * all entries to have at least UPF_BOOT_AUTOCONF set.
3013 */
serial8250_probe(struct platform_device * dev)3014 static int __devinit serial8250_probe(struct platform_device *dev)
3015 {
3016 struct plat_serial8250_port *p = dev->dev.platform_data;
3017 struct uart_port port;
3018 int ret, i, irqflag = 0;
3019
3020 memset(&port, 0, sizeof(struct uart_port));
3021
3022 if (share_irqs)
3023 irqflag = IRQF_SHARED;
3024
3025 for (i = 0; p && p->flags != 0; p++, i++) {
3026 port.iobase = p->iobase;
3027 port.membase = p->membase;
3028 port.irq = p->irq;
3029 port.irqflags = p->irqflags;
3030 port.uartclk = p->uartclk;
3031 port.regshift = p->regshift;
3032 port.iotype = p->iotype;
3033 port.flags = p->flags;
3034 port.mapbase = p->mapbase;
3035 port.hub6 = p->hub6;
3036 port.private_data = p->private_data;
3037 port.type = p->type;
3038 port.serial_in = p->serial_in;
3039 port.serial_out = p->serial_out;
3040 port.handle_irq = p->handle_irq;
3041 port.set_termios = p->set_termios;
3042 port.pm = p->pm;
3043 port.dev = &dev->dev;
3044 port.irqflags |= irqflag;
3045 ret = serial8250_register_port(&port);
3046 if (ret < 0) {
3047 dev_err(&dev->dev, "unable to register port at index %d "
3048 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3049 p->iobase, (unsigned long long)p->mapbase,
3050 p->irq, ret);
3051 }
3052 }
3053 return 0;
3054 }
3055
3056 /*
3057 * Remove serial ports registered against a platform device.
3058 */
serial8250_remove(struct platform_device * dev)3059 static int __devexit serial8250_remove(struct platform_device *dev)
3060 {
3061 int i;
3062
3063 for (i = 0; i < nr_uarts; i++) {
3064 struct uart_8250_port *up = &serial8250_ports[i];
3065
3066 if (up->port.dev == &dev->dev)
3067 serial8250_unregister_port(i);
3068 }
3069 return 0;
3070 }
3071
serial8250_suspend(struct platform_device * dev,pm_message_t state)3072 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3073 {
3074 int i;
3075
3076 for (i = 0; i < UART_NR; i++) {
3077 struct uart_8250_port *up = &serial8250_ports[i];
3078
3079 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3080 uart_suspend_port(&serial8250_reg, &up->port);
3081 }
3082
3083 return 0;
3084 }
3085
serial8250_resume(struct platform_device * dev)3086 static int serial8250_resume(struct platform_device *dev)
3087 {
3088 int i;
3089
3090 for (i = 0; i < UART_NR; i++) {
3091 struct uart_8250_port *up = &serial8250_ports[i];
3092
3093 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3094 serial8250_resume_port(i);
3095 }
3096
3097 return 0;
3098 }
3099
3100 static struct platform_driver serial8250_isa_driver = {
3101 .probe = serial8250_probe,
3102 .remove = __devexit_p(serial8250_remove),
3103 .suspend = serial8250_suspend,
3104 .resume = serial8250_resume,
3105 .driver = {
3106 .name = "serial8250",
3107 .owner = THIS_MODULE,
3108 },
3109 };
3110
3111 /*
3112 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3113 * in the table in include/asm/serial.h
3114 */
3115 static struct platform_device *serial8250_isa_devs;
3116
3117 /*
3118 * serial8250_register_port and serial8250_unregister_port allows for
3119 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3120 * modems and PCI multiport cards.
3121 */
3122 static DEFINE_MUTEX(serial_mutex);
3123
serial8250_find_match_or_unused(struct uart_port * port)3124 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3125 {
3126 int i;
3127
3128 /*
3129 * First, find a port entry which matches.
3130 */
3131 for (i = 0; i < nr_uarts; i++)
3132 if (uart_match_port(&serial8250_ports[i].port, port))
3133 return &serial8250_ports[i];
3134
3135 /*
3136 * We didn't find a matching entry, so look for the first
3137 * free entry. We look for one which hasn't been previously
3138 * used (indicated by zero iobase).
3139 */
3140 for (i = 0; i < nr_uarts; i++)
3141 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3142 serial8250_ports[i].port.iobase == 0)
3143 return &serial8250_ports[i];
3144
3145 /*
3146 * That also failed. Last resort is to find any entry which
3147 * doesn't have a real port associated with it.
3148 */
3149 for (i = 0; i < nr_uarts; i++)
3150 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3151 return &serial8250_ports[i];
3152
3153 return NULL;
3154 }
3155
3156 /**
3157 * serial8250_register_port - register a serial port
3158 * @port: serial port template
3159 *
3160 * Configure the serial port specified by the request. If the
3161 * port exists and is in use, it is hung up and unregistered
3162 * first.
3163 *
3164 * The port is then probed and if necessary the IRQ is autodetected
3165 * If this fails an error is returned.
3166 *
3167 * On success the port is ready to use and the line number is returned.
3168 */
serial8250_register_port(struct uart_port * port)3169 int serial8250_register_port(struct uart_port *port)
3170 {
3171 struct uart_8250_port *uart;
3172 int ret = -ENOSPC;
3173
3174 if (port->uartclk == 0)
3175 return -EINVAL;
3176
3177 mutex_lock(&serial_mutex);
3178
3179 uart = serial8250_find_match_or_unused(port);
3180 if (uart) {
3181 uart_remove_one_port(&serial8250_reg, &uart->port);
3182
3183 uart->port.iobase = port->iobase;
3184 uart->port.membase = port->membase;
3185 uart->port.irq = port->irq;
3186 uart->port.irqflags = port->irqflags;
3187 uart->port.uartclk = port->uartclk;
3188 uart->port.fifosize = port->fifosize;
3189 uart->port.regshift = port->regshift;
3190 uart->port.iotype = port->iotype;
3191 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3192 uart->port.mapbase = port->mapbase;
3193 uart->port.private_data = port->private_data;
3194 if (port->dev)
3195 uart->port.dev = port->dev;
3196
3197 if (port->flags & UPF_FIXED_TYPE)
3198 serial8250_init_fixed_type_port(uart, port->type);
3199
3200 set_io_from_upio(&uart->port);
3201 /* Possibly override default I/O functions. */
3202 if (port->serial_in)
3203 uart->port.serial_in = port->serial_in;
3204 if (port->serial_out)
3205 uart->port.serial_out = port->serial_out;
3206 if (port->handle_irq)
3207 uart->port.handle_irq = port->handle_irq;
3208 /* Possibly override set_termios call */
3209 if (port->set_termios)
3210 uart->port.set_termios = port->set_termios;
3211 if (port->pm)
3212 uart->port.pm = port->pm;
3213
3214 if (serial8250_isa_config != NULL)
3215 serial8250_isa_config(0, &uart->port,
3216 &uart->capabilities);
3217
3218 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3219 if (ret == 0)
3220 ret = uart->port.line;
3221 }
3222 mutex_unlock(&serial_mutex);
3223
3224 return ret;
3225 }
3226 EXPORT_SYMBOL(serial8250_register_port);
3227
3228 /**
3229 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3230 * @line: serial line number
3231 *
3232 * Remove one serial port. This may not be called from interrupt
3233 * context. We hand the port back to the our control.
3234 */
serial8250_unregister_port(int line)3235 void serial8250_unregister_port(int line)
3236 {
3237 struct uart_8250_port *uart = &serial8250_ports[line];
3238
3239 mutex_lock(&serial_mutex);
3240 uart_remove_one_port(&serial8250_reg, &uart->port);
3241 if (serial8250_isa_devs) {
3242 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3243 uart->port.type = PORT_UNKNOWN;
3244 uart->port.dev = &serial8250_isa_devs->dev;
3245 uart->capabilities = uart_config[uart->port.type].flags;
3246 uart_add_one_port(&serial8250_reg, &uart->port);
3247 } else {
3248 uart->port.dev = NULL;
3249 }
3250 mutex_unlock(&serial_mutex);
3251 }
3252 EXPORT_SYMBOL(serial8250_unregister_port);
3253
serial8250_init(void)3254 static int __init serial8250_init(void)
3255 {
3256 int ret;
3257
3258 if (nr_uarts > UART_NR)
3259 nr_uarts = UART_NR;
3260
3261 printk(KERN_INFO "Serial: 8250/16550 driver, "
3262 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3263 share_irqs ? "en" : "dis");
3264
3265 #ifdef CONFIG_SPARC
3266 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3267 #else
3268 serial8250_reg.nr = UART_NR;
3269 ret = uart_register_driver(&serial8250_reg);
3270 #endif
3271 if (ret)
3272 goto out;
3273
3274 serial8250_isa_devs = platform_device_alloc("serial8250",
3275 PLAT8250_DEV_LEGACY);
3276 if (!serial8250_isa_devs) {
3277 ret = -ENOMEM;
3278 goto unreg_uart_drv;
3279 }
3280
3281 ret = platform_device_add(serial8250_isa_devs);
3282 if (ret)
3283 goto put_dev;
3284
3285 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3286
3287 ret = platform_driver_register(&serial8250_isa_driver);
3288 if (ret == 0)
3289 goto out;
3290
3291 platform_device_del(serial8250_isa_devs);
3292 put_dev:
3293 platform_device_put(serial8250_isa_devs);
3294 unreg_uart_drv:
3295 #ifdef CONFIG_SPARC
3296 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3297 #else
3298 uart_unregister_driver(&serial8250_reg);
3299 #endif
3300 out:
3301 return ret;
3302 }
3303
serial8250_exit(void)3304 static void __exit serial8250_exit(void)
3305 {
3306 struct platform_device *isa_dev = serial8250_isa_devs;
3307
3308 /*
3309 * This tells serial8250_unregister_port() not to re-register
3310 * the ports (thereby making serial8250_isa_driver permanently
3311 * in use.)
3312 */
3313 serial8250_isa_devs = NULL;
3314
3315 platform_driver_unregister(&serial8250_isa_driver);
3316 platform_device_unregister(isa_dev);
3317
3318 #ifdef CONFIG_SPARC
3319 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3320 #else
3321 uart_unregister_driver(&serial8250_reg);
3322 #endif
3323 }
3324
3325 module_init(serial8250_init);
3326 module_exit(serial8250_exit);
3327
3328 EXPORT_SYMBOL(serial8250_suspend_port);
3329 EXPORT_SYMBOL(serial8250_resume_port);
3330
3331 MODULE_LICENSE("GPL");
3332 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3333
3334 module_param(share_irqs, uint, 0644);
3335 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3336 " (unsafe)");
3337
3338 module_param(nr_uarts, uint, 0644);
3339 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3340
3341 module_param(skip_txen_test, uint, 0644);
3342 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3343
3344 #ifdef CONFIG_SERIAL_8250_RSA
3345 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3346 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3347 #endif
3348 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
3349